From 0fe5cf7257c80d23ffba15e87fa3478bce6c823b Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Tue, 28 Apr 2020 08:58:33 +0000 Subject: [PATCH] Fixed bug #1088. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13595 27425a3e-05d8-49a3-a47f-9c15f0e5edd8 --- os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c | 83 +++++++++++------- os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.h | 8 +- os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c | 84 ++++++++++++------- os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.h | 8 +- readme.txt | 6 +- testhal/STM32/multi/UART/.cproject | 1 + 6 files changed, 127 insertions(+), 63 deletions(-) diff --git a/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c b/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c index eaaeeda36..d7da0467d 100644 --- a/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c +++ b/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c @@ -193,7 +193,7 @@ static void uart_enter_rx_idle_loop(UARTDriver *uartp) { mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TCIE; dmaStreamSetMemory0(uartp->dmarx, &uartp->rxbuf); dmaStreamSetTransactionSize(uartp->dmarx, 1); - dmaStreamSetMode(uartp->dmarx, uartp->dmamode | mode); + dmaStreamSetMode(uartp->dmarx, uartp->dmarxmode | mode); dmaStreamEnable(uartp->dmarx); } @@ -525,7 +525,8 @@ void uart_lld_init(void) { #if STM32_UART_USE_USART1 uartObjectInit(&UARTD1); UARTD1.usart = USART1; - UARTD1.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD1.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD1.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD1.dmarx = NULL; UARTD1.dmatx = NULL; #endif @@ -533,7 +534,8 @@ void uart_lld_init(void) { #if STM32_UART_USE_USART2 uartObjectInit(&UARTD2); UARTD2.usart = USART2; - UARTD2.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD2.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD2.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD2.dmarx = NULL; UARTD2.dmatx = NULL; #endif @@ -541,7 +543,8 @@ void uart_lld_init(void) { #if STM32_UART_USE_USART3 uartObjectInit(&UARTD3); UARTD3.usart = USART3; - UARTD3.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD3.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD3.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD3.dmarx = NULL; UARTD3.dmatx = NULL; #endif @@ -549,7 +552,8 @@ void uart_lld_init(void) { #if STM32_UART_USE_UART4 uartObjectInit(&UARTD4); UARTD4.usart = UART4; - UARTD4.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD4.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD4.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD4.dmarx = NULL; UARTD4.dmatx = NULL; #endif @@ -557,7 +561,8 @@ void uart_lld_init(void) { #if STM32_UART_USE_UART5 uartObjectInit(&UARTD5); UARTD5.usart = UART5; - UARTD5.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD5.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD5.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD5.dmarx = NULL; UARTD5.dmatx = NULL; #endif @@ -565,6 +570,8 @@ void uart_lld_init(void) { #if STM32_UART_USE_USART6 uartObjectInit(&UARTD6); UARTD6.usart = USART6; + UARTD6.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD6.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD6.dmarx = NULL; UARTD6.dmatx = NULL; #endif @@ -572,7 +579,8 @@ void uart_lld_init(void) { #if STM32_UART_USE_UART7 uartObjectInit(&UARTD7); UARTD7.usart = UART7; - UARTD7.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD7.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD7.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD7.dmarx = NULL; UARTD7.dmatx = NULL; #endif @@ -580,7 +588,8 @@ void uart_lld_init(void) { #if STM32_UART_USE_UART8 uartObjectInit(&UARTD8); UARTD8.usart = UART8; - UARTD8.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD8.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD8.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD8.dmarx = NULL; UARTD8.dmatx = NULL; #endif @@ -611,8 +620,10 @@ void uart_lld_start(UARTDriver *uartp) { rccEnableUSART1(true); nvicEnableVector(STM32_USART1_NUMBER, STM32_UART_USART1_IRQ_PRIORITY); - uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY); + uartp->dmarxmode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY); + uartp->dmatxmode |= STM32_DMA_CR_CHSEL(USART1_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY); } #endif @@ -631,8 +642,10 @@ void uart_lld_start(UARTDriver *uartp) { rccEnableUSART2(true); nvicEnableVector(STM32_USART2_NUMBER, STM32_UART_USART2_IRQ_PRIORITY); - uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY); + uartp->dmarxmode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY); + uartp->dmatxmode |= STM32_DMA_CR_CHSEL(USART2_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY); } #endif @@ -651,8 +664,10 @@ void uart_lld_start(UARTDriver *uartp) { rccEnableUSART3(true); nvicEnableVector(STM32_USART3_NUMBER, STM32_UART_USART3_IRQ_PRIORITY); - uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY); + uartp->dmarxmode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY); + uartp->dmatxmode |= STM32_DMA_CR_CHSEL(USART3_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY); } #endif @@ -677,8 +692,10 @@ void uart_lld_start(UARTDriver *uartp) { rccEnableUART4(true); nvicEnableVector(STM32_UART4_NUMBER, STM32_UART_UART4_IRQ_PRIORITY); - uartp->dmamode |= STM32_DMA_CR_CHSEL(UART4_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY); + uartp->dmarxmode |= STM32_DMA_CR_CHSEL(UART4_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY); + uartp->dmatxmode |= STM32_DMA_CR_CHSEL(UART4_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY); } #endif @@ -703,8 +720,10 @@ void uart_lld_start(UARTDriver *uartp) { rccEnableUART5(true); nvicEnableVector(STM32_UART5_NUMBER, STM32_UART_UART5_IRQ_PRIORITY); - uartp->dmamode |= STM32_DMA_CR_CHSEL(UART5_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY); + uartp->dmarxmode |= STM32_DMA_CR_CHSEL(UART5_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY); + uartp->dmatxmode |= STM32_DMA_CR_CHSEL(UART5_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY); } #endif @@ -723,8 +742,10 @@ void uart_lld_start(UARTDriver *uartp) { rccEnableUSART6(true); nvicEnableVector(STM32_USART6_NUMBER, STM32_UART_USART6_IRQ_PRIORITY); - uartp->dmamode |= STM32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY); + uartp->dmarxmode |= STM32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY); + uartp->dmatxmode |= STM32_DMA_CR_CHSEL(USART6_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY); } #endif @@ -749,8 +770,10 @@ void uart_lld_start(UARTDriver *uartp) { rccEnableUART7(true); nvicEnableVector(STM32_UART7_NUMBER, STM32_UART_UART7_IRQ_PRIORITY); - uartp->dmamode |= STM32_DMA_CR_CHSEL(UART7_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_UART7_DMA_PRIORITY); + uartp->dmarxmode |= STM32_DMA_CR_CHSEL(UART7_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_UART7_DMA_PRIORITY); + uartp->dmatxmode |= STM32_DMA_CR_CHSEL(UART7_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_UART7_DMA_PRIORITY); } #endif @@ -775,15 +798,19 @@ void uart_lld_start(UARTDriver *uartp) { rccEnableUART8(true); nvicEnableVector(STM32_UART8_NUMBER, STM32_UART_UART8_IRQ_PRIORITY); - uartp->dmamode |= STM32_DMA_CR_CHSEL(UART8_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_UART8_DMA_PRIORITY); + uartp->dmarxmode |= STM32_DMA_CR_CHSEL(UART8_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_UART8_DMA_PRIORITY); + uartp->dmatxmode |= STM32_DMA_CR_CHSEL(UART8_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_UART8_DMA_PRIORITY); } #endif /* Static DMA setup, the transfer size depends on the USART settings, it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/ - if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M) - uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; + if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M) { + uartp->dmarxmode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; + uartp->dmatxmode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; + } dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->DR); dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->DR); uartp->rxbuf = 0; @@ -892,7 +919,7 @@ void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) { /* TX DMA channel preparation.*/ dmaStreamSetMemory0(uartp->dmatx, txbuf); dmaStreamSetTransactionSize(uartp->dmatx, n); - dmaStreamSetMode(uartp->dmatx, uartp->dmamode | STM32_DMA_CR_DIR_M2P | + dmaStreamSetMode(uartp->dmatx, uartp->dmatxmode | STM32_DMA_CR_DIR_M2P | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE); /* Only enable TC interrupt if there's a callback attached to it or @@ -948,7 +975,7 @@ void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) { /* RX DMA channel preparation.*/ dmaStreamSetMemory0(uartp->dmarx, rxbuf); dmaStreamSetTransactionSize(uartp->dmarx, n); - dmaStreamSetMode(uartp->dmarx, uartp->dmamode | STM32_DMA_CR_DIR_P2M | + dmaStreamSetMode(uartp->dmarx, uartp->dmarxmode | STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE); /* Starting transfer.*/ diff --git a/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.h b/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.h index ea4047325..ae0f4d36d 100644 --- a/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.h +++ b/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.h @@ -676,9 +676,13 @@ struct UARTDriver { */ USART_TypeDef *usart; /** - * @brief DMA mode bit mask. + * @brief Receive DMA mode bit mask. */ - uint32_t dmamode; + uint32_t dmarxmode; + /** + * @brief Send DMA mode bit mask. + */ + uint32_t dmatxmode; /** * @brief Receive DMA channel. */ diff --git a/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c b/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c index 038bdb967..37877168a 100644 --- a/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c +++ b/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c @@ -223,7 +223,7 @@ static void uart_enter_rx_idle_loop(UARTDriver *uartp) { mode = STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_CIRC | STM32_DMA_CR_TCIE; dmaStreamSetMemory0(uartp->dmarx, &uartp->rxbuf); dmaStreamSetTransactionSize(uartp->dmarx, 1); - dmaStreamSetMode(uartp->dmarx, uartp->dmamode | mode); + dmaStreamSetMode(uartp->dmarx, uartp->dmarxmode | mode); dmaStreamEnable(uartp->dmarx); } @@ -535,7 +535,8 @@ void uart_lld_init(void) { uartObjectInit(&UARTD1); UARTD1.usart = USART1; UARTD1.clock = STM32_USART1CLK; - UARTD1.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD1.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD1.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD1.dmarx = NULL; UARTD1.dmatx = NULL; #if !defined(STM32_USART1_SUPPRESS_ISR) && defined(STM32_USART1_NUMBER) @@ -547,7 +548,8 @@ void uart_lld_init(void) { uartObjectInit(&UARTD2); UARTD2.usart = USART2; UARTD2.clock = STM32_USART2CLK; - UARTD2.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD2.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD2.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD2.dmarx = NULL; UARTD2.dmatx = NULL; #if !defined(STM32_USART2_SUPPRESS_ISR) && defined(STM32_USART2_NUMBER) @@ -559,7 +561,8 @@ void uart_lld_init(void) { uartObjectInit(&UARTD3); UARTD3.usart = USART3; UARTD3.clock = STM32_USART3CLK; - UARTD3.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD3.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD3.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD3.dmarx = NULL; UARTD3.dmatx = NULL; #if !defined(STM32_USART3_SUPPRESS_ISR) && defined(STM32_USART3_NUMBER) @@ -571,7 +574,8 @@ void uart_lld_init(void) { uartObjectInit(&UARTD4); UARTD4.usart = UART4; UARTD4.clock = STM32_UART4CLK; - UARTD4.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD4.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD4.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD4.dmarx = NULL; UARTD4.dmatx = NULL; #if !defined(STM32_UART4_SUPPRESS_ISR) && defined(STM32_UART4_NUMBER) @@ -583,7 +587,8 @@ void uart_lld_init(void) { uartObjectInit(&UARTD5); UARTD5.usart = UART5; UARTD5.clock = STM32_UART5CLK; - UARTD5.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD5.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD5.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD5.dmarx = NULL; UARTD5.dmatx = NULL; #if !defined(STM32_UART5_SUPPRESS_ISR) && defined(STM32_UART5_NUMBER) @@ -595,7 +600,8 @@ void uart_lld_init(void) { uartObjectInit(&UARTD6); UARTD6.usart = USART6; UARTD6.clock = STM32_USART6CLK; - UARTD6.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD6.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD6.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD6.dmarx = NULL; UARTD6.dmatx = NULL; #if !defined(STM32_USART6_SUPPRESS_ISR) && defined(STM32_USART6_NUMBER) @@ -607,7 +613,8 @@ void uart_lld_init(void) { uartObjectInit(&UARTD7); UARTD7.usart = UART7; UARTD7.clock = STM32_UART7CLK; - UARTD7.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD7.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD7.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD7.dmarx = NULL; UARTD7.dmatx = NULL; #if !defined(STM32_UART7_SUPPRESS_ISR) && defined(STM32_UART7_NUMBER) @@ -619,7 +626,8 @@ void uart_lld_init(void) { uartObjectInit(&UARTD8); UARTD8.usart = UART8; UARTD8.clock = STM32_UART8CLK; - UARTD8.dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD8.dmarxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; + UARTD8.dmatxmode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; UARTD8.dmarx = NULL; UARTD8.dmatx = NULL; #if !defined(STM32_UART8_SUPPRESS_ISR) && defined(STM32_UART8_NUMBER) @@ -652,8 +660,10 @@ void uart_lld_start(UARTDriver *uartp) { osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream"); rccEnableUSART1(true); - uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY); + uartp->dmarxmode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY); + uartp->dmatxmode |= STM32_DMA_CR_CHSEL(USART1_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY); #if STM32_DMA_SUPPORTS_DMAMUX dmaSetRequestSource(uartp->dmarx, STM32_DMAMUX1_USART1_RX); dmaSetRequestSource(uartp->dmatx, STM32_DMAMUX1_USART1_TX); @@ -675,8 +685,10 @@ void uart_lld_start(UARTDriver *uartp) { osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream"); rccEnableUSART2(true); - uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY); + uartp->dmarxmode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY); + uartp->dmatxmode |= STM32_DMA_CR_CHSEL(USART2_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY); #if STM32_DMA_SUPPORTS_DMAMUX dmaSetRequestSource(uartp->dmarx, STM32_DMAMUX1_USART2_RX); dmaSetRequestSource(uartp->dmatx, STM32_DMAMUX1_USART2_TX); @@ -698,8 +710,10 @@ void uart_lld_start(UARTDriver *uartp) { osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream"); rccEnableUSART3(true); - uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY); + uartp->dmarxmode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY); + uartp->dmatxmode |= STM32_DMA_CR_CHSEL(USART3_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY); #if STM32_DMA_SUPPORTS_DMAMUX dmaSetRequestSource(uartp->dmarx, STM32_DMAMUX1_USART3_RX); dmaSetRequestSource(uartp->dmatx, STM32_DMAMUX1_USART3_TX); @@ -721,8 +735,10 @@ void uart_lld_start(UARTDriver *uartp) { osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream"); rccEnableUART4(true); - uartp->dmamode |= STM32_DMA_CR_CHSEL(UART4_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY); + uartp->dmarxmode |= STM32_DMA_CR_CHSEL(UART4_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY); + uartp->dmatxmode |= STM32_DMA_CR_CHSEL(UART4_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY); #if STM32_DMA_SUPPORTS_DMAMUX dmaSetRequestSource(uartp->dmarx, STM32_DMAMUX1_UART4_RX); dmaSetRequestSource(uartp->dmatx, STM32_DMAMUX1_UART4_TX); @@ -744,8 +760,10 @@ void uart_lld_start(UARTDriver *uartp) { osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream"); rccEnableUART5(true); - uartp->dmamode |= STM32_DMA_CR_CHSEL(UART5_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY); + uartp->dmarxmode |= STM32_DMA_CR_CHSEL(UART5_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY); + uartp->dmatxmode |= STM32_DMA_CR_CHSEL(UART5_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY); #if STM32_DMA_SUPPORTS_DMAMUX dmaSetRequestSource(uartp->dmarx, STM32_DMAMUX1_UART5_RX); dmaSetRequestSource(uartp->dmatx, STM32_DMAMUX1_UART5_TX); @@ -767,8 +785,10 @@ void uart_lld_start(UARTDriver *uartp) { osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream"); rccEnableUSART6(true); - uartp->dmamode |= STM32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY); + uartp->dmarxmode |= STM32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY); + uartp->dmatxmode |= STM32_DMA_CR_CHSEL(USART6_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY); #if STM32_DMA_SUPPORTS_DMAMUX dmaSetRequestSource(uartp->dmarx, STM32_DMAMUX1_USART6_RX); dmaSetRequestSource(uartp->dmatx, STM32_DMAMUX1_USART6_TX); @@ -790,8 +810,10 @@ void uart_lld_start(UARTDriver *uartp) { osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream"); rccEnableUART7(true); - uartp->dmamode |= STM32_DMA_CR_CHSEL(UART7_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_UART7_DMA_PRIORITY); + uartp->dmarxmode |= STM32_DMA_CR_CHSEL(UART7_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_UART7_DMA_PRIORITY); + uartp->dmatxmode |= STM32_DMA_CR_CHSEL(UART7_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_UART7_DMA_PRIORITY); #if STM32_DMA_SUPPORTS_DMAMUX dmaSetRequestSource(uartp->dmarx, STM32_DMAMUX1_UART7_RX); dmaSetRequestSource(uartp->dmatx, STM32_DMAMUX1_UART7_TX); @@ -813,8 +835,10 @@ void uart_lld_start(UARTDriver *uartp) { osalDbgAssert(uartp->dmatx != NULL, "unable to allocate stream"); rccEnableUART8(true); - uartp->dmamode |= STM32_DMA_CR_CHSEL(UART8_RX_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_UART_UART8_DMA_PRIORITY); + uartp->dmarxmode |= STM32_DMA_CR_CHSEL(UART8_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_UART8_DMA_PRIORITY); + uartp->dmatxmode |= STM32_DMA_CR_CHSEL(UART8_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_UART_UART8_DMA_PRIORITY); #if STM32_DMA_SUPPORTS_DMAMUX dmaSetRequestSource(uartp->dmarx, STM32_DMAMUX1_UART8_RX); dmaSetRequestSource(uartp->dmatx, STM32_DMAMUX1_UART8_TX); @@ -824,8 +848,10 @@ void uart_lld_start(UARTDriver *uartp) { /* Static DMA setup, the transfer size depends on the USART settings, it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/ - if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M0) - uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; + if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M0) { + uartp->dmarxmode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; + uartp->dmatxmode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; + } dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->RDR); dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->TDR); uartp->rxbuf = 0; @@ -926,7 +952,7 @@ void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf) { /* TX DMA channel preparation.*/ dmaStreamSetMemory0(uartp->dmatx, txbuf); dmaStreamSetTransactionSize(uartp->dmatx, n); - dmaStreamSetMode(uartp->dmatx, uartp->dmamode | STM32_DMA_CR_DIR_M2P | + dmaStreamSetMode(uartp->dmatx, uartp->dmatxmode | STM32_DMA_CR_DIR_M2P | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE); /* Only enable TC interrupt if there's a callback attached to it or @@ -982,7 +1008,7 @@ void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf) { /* RX DMA channel preparation.*/ dmaStreamSetMemory0(uartp->dmarx, rxbuf); dmaStreamSetTransactionSize(uartp->dmarx, n); - dmaStreamSetMode(uartp->dmarx, uartp->dmamode | STM32_DMA_CR_DIR_P2M | + dmaStreamSetMode(uartp->dmarx, uartp->dmarxmode | STM32_DMA_CR_DIR_P2M | STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE); /* Starting transfer.*/ diff --git a/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.h b/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.h index 6e4c17299..ec5a6949e 100644 --- a/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.h +++ b/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.h @@ -759,9 +759,13 @@ struct UARTDriver { */ uint32_t clock; /** - * @brief DMA mode bit mask. + * @brief Receive DMA mode bit mask. */ - uint32_t dmamode; + uint32_t dmarxmode; + /** + * @brief Send DMA mode bit mask. + */ + uint32_t dmatxmode; /** * @brief Receive DMA channel. */ diff --git a/readme.txt b/readme.txt index fd8c8ef17..433c25ba4 100644 --- a/readme.txt +++ b/readme.txt @@ -74,8 +74,6 @@ ***************************************************************************** *** Next *** -- FIX: Sector count incorrect in STM32G07/8 EFL driver (bug #1085). -- FIX: Sector size incorrect in STM32F413 EFL driver (bug #1084). - NEW: Updated debug tools to be independent from the toolchain position: they now rely on the environment variable CHIBISTUDIO. - NEW: Mail Queues test implementation in CMSIS RTOS wrapper. @@ -88,6 +86,10 @@ MEMS Accelerometers. - NEW: Safer messages mechanism for sandboxes (to be backported to 20.3.1). - NEW: Added latency measurement test application. +- FIX: Fixed invalid CHSEL DMA setting in STM32 UART drivers (bug #1088) + (backported to 20.3.1)(backported to 19.1.4). +- FIX: Fixed sector count incorrect in STM32G07/8 EFL driver (bug #1085). +- FIX: Fixed sector size incorrect in STM32F413 EFL driver (bug #1084). - FIX: Fixed wrong arguments for the cacheBufferInvalidate in the STM32 SPI demo (bug #1086)(backported to 20.3.1)(backported to 19.1.4). - FIX: Fixed race condition in HAL MAC driver (bug #1083) diff --git a/testhal/STM32/multi/UART/.cproject b/testhal/STM32/multi/UART/.cproject index f926417ab..53ffecc39 100644 --- a/testhal/STM32/multi/UART/.cproject +++ b/testhal/STM32/multi/UART/.cproject @@ -224,4 +224,5 @@ +