Added support for STM32L422.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14287 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio
parent
e82a29e7c6
commit
100acdc8e8
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@ -48,9 +48,10 @@
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* @name Platform identification
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* @{
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*/
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#if defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L443xx) || \
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defined(STM32L452xx) || defined(STM32L471xx) || defined(STM32L475xx) || \
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defined(STM32L476xx) || defined(STM32L496xx) || defined(__DOXYGEN__)
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#if defined(STM32L422xx) || defined(STM32L432xx) || defined(STM32L433xx) || \
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defined(STM32L443xx) || defined(STM32L452xx) || defined(STM32L471xx) || \
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defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L496xx) || \
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defined(__DOXYGEN__)
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#define PLATFORM_NAME "STM32L4xx Ultra Low Power"
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#elif defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L4A6xx)
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@ -0,0 +1,46 @@
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# Required platform files.
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PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
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$(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/stm32_isr.c \
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$(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/hal_lld.c \
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$(CHIBIOS)/os/hal/ports/STM32/STM32L4xx/hal_efl_lld.c
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# Required include directories.
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PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
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$(CHIBIOS)/os/hal/ports/STM32/STM32L4xx
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# Optional platform files.
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ifeq ($(USE_SMART_BUILD),yes)
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# Configuration files directory
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ifeq ($(HALCONFDIR),)
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ifeq ($(CONFDIR),)
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HALCONFDIR = .
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else
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HALCONFDIR := $(CONFDIR)
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endif
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endif
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HALCONF := $(strip $(shell cat $(HALCONFDIR)/halconf.h | egrep -e "\#define"))
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else
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endif
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# Drivers compatible with the platform.
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include $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv3/driver.mk
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include $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/driver.mk
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include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
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include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv3/driver.mk
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include $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/driver.mk
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include $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/driver.mk
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include $(CHIBIOS)/os/hal/ports/STM32/LLD/RNGv1/driver.mk
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include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv3/driver.mk
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include $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv1/driver.mk
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include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv2/driver.mk
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include $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/driver.mk
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include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk
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include $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/driver.mk
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include $(CHIBIOS)/os/hal/ports/STM32/LLD/xWDGv1/driver.mk
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# Shared variables
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ALLCSRC += $(PLATFORMSRC)
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ALLINC += $(PLATFORMINC)
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@ -57,6 +57,246 @@
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#define STM32_RCC_PLLSAI2_HAS_Q FALSE
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#define STM32_RCC_PLLSAI2_HAS_R TRUE
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/*===========================================================================*/
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/* STM32L422xx */
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/*===========================================================================*/
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#if defined(STM32L422xx) || defined(__DOXYGEN__)
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/* Enabling RTC-related EXTI lines.*/
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#define STM32_RTC_ENABLE_ALL_EXTI() do { \
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extiEnableGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI) | \
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EXTI_MASK1(STM32_RTC_TAMP_STAMP_EXTI) | \
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EXTI_MASK1(STM32_RTC_WKUP_EXTI), \
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EXTI_MODE_RISING_EDGE | EXTI_MODE_ACTION_INTERRUPT); \
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} while (false)
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/* Clearing EXTI interrupts. */
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#define STM32_RTC_CLEAR_ALL_EXTI() do { \
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extiClearGroup1(EXTI_MASK1(STM32_RTC_ALARM_EXTI) | \
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EXTI_MASK1(STM32_RTC_TAMP_STAMP_EXTI) | \
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EXTI_MASK1(STM32_RTC_WKUP_EXTI)); \
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} while (false)
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/* Masks used to preserve state of RTC and TAMP register reserved bits. */
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#define STM32_RTC_CR_MASK 0xE7FFFF7F
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#define STM32_RTC_PRER_MASK 0x007F7FFF
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#define STM32_TAMP_CR1_MASK 0x003C0003
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#define STM32_TAMP_CR2_MASK 0x030300FF
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#define STM32_TAMP_FLTCR_MASK 0x000000FF
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#define STM32_TAMP_IER_MASK 0x003C0003
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/* Clock attributes.*/
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#define STM32_RCC_HAS_HSI48 TRUE
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\
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STM32_DMA_STREAM_ID_MSK(2, 3))
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#define STM32_ADC1_DMA_CHN 0x00000000
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#define STM32_HAS_ADC2 TRUE
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#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
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STM32_DMA_STREAM_ID_MSK(2, 4))
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#define STM32_ADC2_DMA_CHN 0x00000000
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_ADC4 FALSE
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/* CAN attributes.*/
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#define STM32_HAS_CAN1 FALSE
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#define STM32_HAS_CAN2 FALSE
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#define STM32_HAS_CAN3 FALSE
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/* DAC attributes.*/
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#define STM32_HAS_DAC1_CH1 FALSE
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#define STM32_HAS_DAC1_CH2 FALSE
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#define STM32_HAS_DAC2_CH1 FALSE
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#define STM32_HAS_DAC2_CH2 FALSE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA TRUE
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#define STM32_DMA_SUPPORTS_DMAMUX FALSE
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#define STM32_DMA_SUPPORTS_CSELR TRUE
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#define STM32_DMA1_NUM_CHANNELS 7
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#define STM32_DMA2_NUM_CHANNELS 7
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/* ETH attributes.*/
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#define STM32_HAS_ETH FALSE
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/* EXTI attributes.*/
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/* TODO à verifier */
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#define STM32_EXTI_NUM_LINES 40
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#define STM32_EXTI_IMR1_MASK 0xFF820000U
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#define STM32_EXTI_IMR2_MASK 0xFFFFFF87U
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/* Flash attributes.*/
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#define STM32_FLASH_NUMBER_OF_BANKS 1
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#if !defined(STM32_FLASH_SECTORS_PER_BANK) || defined(__DOXYGEN__)
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#define STM32_FLASH_SECTORS_PER_BANK 256 /* Maximum, can be redefined.*/
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#endif
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/* GPIO attributes.*/
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD FALSE
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#define STM32_HAS_GPIOE FALSE
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#define STM32_HAS_GPIOF FALSE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_GPIOI FALSE
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#define STM32_HAS_GPIOJ FALSE
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#define STM32_HAS_GPIOK FALSE
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#define STM32_GPIO_EN_MASK (RCC_AHB2ENR_GPIOAEN | \
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RCC_AHB2ENR_GPIOBEN | \
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RCC_AHB2ENR_GPIOCEN)
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
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STM32_DMA_STREAM_ID_MSK(2, 6))
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#define STM32_I2C1_RX_DMA_CHN 0x03500000
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#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6) |\
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STM32_DMA_STREAM_ID_MSK(2, 7))
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#define STM32_I2C1_TX_DMA_CHN 0x05300000
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#define STM32_HAS_I2C3 TRUE
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#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
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#define STM32_I2C3_RX_DMA_CHN 0x00000300
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#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
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#define STM32_I2C3_TX_DMA_CHN 0x00000030
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#define STM32_HAS_I2C2 FALSE
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#define STM32_HAS_I2C4 FALSE
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/* QUADSPI attributes.*/
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#define STM32_HAS_QUADSPI1 TRUE
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#define STM32_QUADSPI1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
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STM32_DMA_STREAM_ID_MSK(2, 7))
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#define STM32_QUADSPI1_DMA_CHN 0x03050000
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/* SDMMC attributes.*/
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#define STM32_HAS_SDMMC1 FALSE
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#define STM32_HAS_SDMMC2 FALSE
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/* SPI attributes.*/
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#define STM32_HAS_SPI1 TRUE
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#define STM32_SPI1_SUPPORTS_I2S FALSE
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#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
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STM32_DMA_STREAM_ID_MSK(2, 3))
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#define STM32_SPI1_RX_DMA_CHN 0x00000410
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#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
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STM32_DMA_STREAM_ID_MSK(2, 4))
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#define STM32_SPI1_TX_DMA_CHN 0x00004100
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#define STM32_HAS_SPI3 FALSE
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#define STM32_HAS_SPI2 FALSE
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#define STM32_HAS_SPI4 FALSE
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#define STM32_HAS_SPI5 FALSE
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#define STM32_HAS_SPI6 FALSE
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/* TIM attributes.*/
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#define STM32_TIM_MAX_CHANNELS 6
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#define STM32_HAS_TIM1 TRUE
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#define STM32_TIM1_IS_32BITS FALSE
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#define STM32_TIM1_CHANNELS 6
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#define STM32_HAS_TIM2 TRUE
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#define STM32_TIM2_IS_32BITS TRUE
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#define STM32_TIM2_CHANNELS 4
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#define STM32_HAS_TIM6 TRUE
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#define STM32_TIM6_IS_32BITS FALSE
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#define STM32_TIM6_CHANNELS 0
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#define STM32_HAS_TIM7 TRUE
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#define STM32_TIM7_IS_32BITS FALSE
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#define STM32_TIM7_CHANNELS 0
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#define STM32_HAS_TIM15 TRUE
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#define STM32_TIM15_IS_32BITS FALSE
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#define STM32_TIM15_CHANNELS 2/* SPI attributes. */
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#define STM32_HAS_SPIR FALSE
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#define STM32_HAS_TIM16 TRUE
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#define STM32_TIM16_IS_32BITS FALSE
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#define STM32_TIM16_CHANNELS 2
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#define STM32_HAS_TIM3 FALSE
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#define STM32_HAS_TIM4 FALSE
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#define STM32_HAS_TIM5 FALSE
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#define STM32_HAS_TIM8 FALSE
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#define STM32_HAS_TIM9 FALSE
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#define STM32_HAS_TIM10 FALSE
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#define STM32_HAS_TIM11 FALSE
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#define STM32_HAS_TIM12 FALSE
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#define STM32_HAS_TIM13 FALSE
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#define STM32_HAS_TIM14 FALSE
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#define STM32_HAS_TIM17 FALSE
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#define STM32_HAS_TIM18 FALSE
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#define STM32_HAS_TIM19 FALSE
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#define STM32_HAS_TIM20 FALSE
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#define STM32_HAS_TIM21 FALSE
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#define STM32_HAS_TIM22 FALSE
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/* USART attributes.*/
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#define STM32_HAS_USART1 TRUE
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#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
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STM32_DMA_STREAM_ID_MSK(2, 7))
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#define STM32_USART1_RX_DMA_CHN 0x02020000
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#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
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STM32_DMA_STREAM_ID_MSK(2, 6))
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#define STM32_USART1_TX_DMA_CHN 0x00202000
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#define STM32_HAS_USART2 TRUE
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#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
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#define STM32_USART2_RX_DMA_CHN 0x00200000
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#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
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#define STM32_USART2_TX_DMA_CHN 0x02000000
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#define STM32_HAS_LPUART1 TRUE
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#define STM32_HAS_USART3 FALSE
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#define STM32_HAS_UART4 FALSE
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#define STM32_HAS_UART5 FALSE
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#define STM32_HAS_USART6 FALSE
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#define STM32_HAS_UART7 FALSE
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#define STM32_HAS_UART8 FALSE
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/* USB attributes.*/
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#define STM32_HAS_USB TRUE
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#define STM32_USB_ACCESS_SCHEME_2x16 TRUE
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#define STM32_USB_PMA_SIZE 1024
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#define STM32_USB_HAS_BCDR TRUE
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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/* IWDG attributes.*/
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#define STM32_HAS_IWDG TRUE
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#define STM32_IWDG_IS_WINDOWED TRUE
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/* LTDC attributes.*/
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#define STM32_HAS_LTDC FALSE
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/* DMA2D attributes.*/
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#define STM32_HAS_DMA2D FALSE
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/* FSMC attributes.*/
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#define STM32_HAS_FSMC TRUE
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/* CRC attributes.*/
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#define STM32_HAS_CRC TRUE
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#define STM32_CRC_PROGRAMMABLE TRUE
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#endif /* defined(STM32L422xx) */
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/*===========================================================================*/
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/* Common. */
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/*===========================================================================*/
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@ -74,6 +74,7 @@
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*****************************************************************************
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*** Next ***
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- NEW: Added support for STM32L422.
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- NEW: Added support for STM32WLx5.
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- NEW: Added initial support for RP2040.
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- NEW: Added time conversion macros and functions for monotonic time stamps
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@ -0,0 +1,262 @@
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[#ftl]
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[#--
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
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This file is part of ChibiOS.
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ChibiOS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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--]
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[@pp.dropOutputFile /]
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[#import "/@lib/libutils.ftl" as utils /]
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[#import "/@lib/liblicense.ftl" as license /]
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[@pp.changeOutputFile name="mcuconf.h" /]
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/*
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[@license.EmitLicenseAsText /]
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*/
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/*
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* STM32L4xx drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 15...0 Lowest...Highest.
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*
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* DMA priorities:
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* 0...3 Lowest...Highest.
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*/
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#ifndef MCUCONF_H
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#define MCUCONF_H
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#define STM32L4xx_MCUCONF
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#define STM32L422_MCUCONF
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/*
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* HAL driver system settings.
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*/
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#define STM32_NO_INIT ${doc.STM32_NO_INIT!"FALSE"}
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#define STM32_VOS ${doc.STM32_VOS!"STM32_VOS_RANGE1"}
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#define STM32_PVD_ENABLE ${doc.STM32_PVD_ENABLE!"FALSE"}
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#define STM32_PLS ${doc.STM32_PLS!"STM32_PLS_LEV0"}
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#define STM32_HSI16_ENABLED ${doc.STM32_HSI16_ENABLED!"FALSE"}
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#define STM32_HSI48_ENABLED ${doc.STM32_HSI48_ENABLED!"FALSE"}
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#define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"TRUE"}
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#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"FALSE"}
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#define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"FALSE"}
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#define STM32_MSIPLL_ENABLED ${doc.STM32_MSIPLL_ENABLED!"FALSE"}
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#define STM32_MSIRANGE ${doc.STM32_MSIRANGE!"STM32_MSIRANGE_4M"}
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#define STM32_MSISRANGE ${doc.STM32_MSISRANGE!"STM32_MSISRANGE_4M"}
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#define STM32_SW ${doc.STM32_SW!"STM32_SW_PLL"}
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#define STM32_PLLSRC ${doc.STM32_PLLSRC!"STM32_PLLSRC_MSI"}
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#define STM32_PLLM_VALUE ${doc.STM32_PLLM_VALUE!"1"}
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#define STM32_PLLN_VALUE ${doc.STM32_PLLN_VALUE!"80"}
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#define STM32_PLLPDIV_VALUE ${doc.STM32_PLLPDIV_VALUE!"0"}
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#define STM32_PLLP_VALUE ${doc.STM32_PLLP_VALUE!"7"}
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#define STM32_PLLQ_VALUE ${doc.STM32_PLLQ_VALUE!"6"}
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#define STM32_PLLR_VALUE ${doc.STM32_PLLR_VALUE!"4"}
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#define STM32_HPRE ${doc.STM32_HPRE!"STM32_HPRE_DIV1"}
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#define STM32_PPRE1 ${doc.STM32_PPRE1!"STM32_PPRE1_DIV1"}
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#define STM32_PPRE2 ${doc.STM32_PPRE2!"STM32_PPRE2_DIV1"}
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#define STM32_STOPWUCK ${doc.STM32_STOPWUCK!"STM32_STOPWUCK_MSI"}
|
||||
#define STM32_MCOSEL ${doc.STM32_MCOSEL!"STM32_MCOSEL_NOCLOCK"}
|
||||
#define STM32_MCOPRE ${doc.STM32_MCOPRE!"STM32_MCOPRE_DIV1"}
|
||||
#define STM32_LSCOSEL ${doc.STM32_LSCOSEL!"STM32_LSCOSEL_NOCLOCK"}
|
||||
#define STM32_PLLSAI1N_VALUE ${doc.STM32_PLLSAI1N_VALUE!"72"}
|
||||
#define STM32_PLLSAI1PDIV_VALUE ${doc.STM32_PLLSAI1PDIV_VALUE!"6"}
|
||||
#define STM32_PLLSAI1P_VALUE ${doc.STM32_PLLSAI1P_VALUE!"7"}
|
||||
#define STM32_PLLSAI1Q_VALUE ${doc.STM32_PLLSAI1Q_VALUE!"6"}
|
||||
#define STM32_PLLSAI1R_VALUE ${doc.STM32_PLLSAI1R_VALUE!"6"}
|
||||
|
||||
/*
|
||||
* Peripherals clock sources.
|
||||
*/
|
||||
#define STM32_USART1SEL ${doc.STM32_USART1SEL!"STM32_USART1SEL_SYSCLK"}
|
||||
#define STM32_USART2SEL ${doc.STM32_USART2SEL!"STM32_USART2SEL_SYSCLK"}
|
||||
#define STM32_LPUART1SEL ${doc.STM32_LPUART1SEL!"STM32_LPUART1SEL_SYSCLK"}
|
||||
#define STM32_I2C1SEL ${doc.STM32_I2C1SEL!"STM32_I2C1SEL_SYSCLK"}
|
||||
#define STM32_I2C3SEL ${doc.STM32_I2C3SEL!"STM32_I2C3SEL_SYSCLK"}
|
||||
#define STM32_LPTIM1SEL ${doc.STM32_LPTIM1SEL!"STM32_LPTIM1SEL_PCLK1"}
|
||||
#define STM32_LPTIM2SEL ${doc.STM32_LPTIM2SEL!"STM32_LPTIM2SEL_PCLK1"}
|
||||
#define STM32_SAI1SEL ${doc.STM32_SAI1SEL!"STM32_SAI1SEL_OFF"}
|
||||
#define STM32_CLK48SEL ${doc.STM32_CLK48SEL!"STM32_CLK48SEL_PLL"}
|
||||
#define STM32_ADCSEL ${doc.STM32_ADCSEL!"STM32_ADCSEL_SYSCLK"}
|
||||
#define STM32_SWPMI1SEL ${doc.STM32_SWPMI1SEL!"STM32_SWPMI1SEL_PCLK1"}
|
||||
#define STM32_RTCSEL ${doc.STM32_RTCSEL!"STM32_RTCSEL_LSI"}
|
||||
|
||||
/*
|
||||
* IRQ system settings.
|
||||
*/
|
||||
#define STM32_IRQ_EXTI0_PRIORITY ${doc.STM32_IRQ_EXTI0_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI1_PRIORITY ${doc.STM32_IRQ_EXTI1_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI2_PRIORITY ${doc.STM32_IRQ_EXTI2_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI3_PRIORITY ${doc.STM32_IRQ_EXTI3_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI4_PRIORITY ${doc.STM32_IRQ_EXTI4_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI5_9_PRIORITY ${doc.STM32_IRQ_EXTI5_9_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI10_15_PRIORITY ${doc.STM32_IRQ_EXTI10_15_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI1635_38_PRIORITY ${doc.STM32_IRQ_EXTI1635_38_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI18_PRIORITY ${doc.STM32_IRQ_EXTI18_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI19_PRIORITY ${doc.STM32_IRQ_EXTI19_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI20_PRIORITY ${doc.STM32_IRQ_EXTI20_PRIORITY!"6"}
|
||||
#define STM32_IRQ_EXTI21_22_PRIORITY ${doc.STM32_IRQ_EXTI21_22_PRIORITY!"6"}
|
||||
|
||||
#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY ${doc.STM32_IRQ_TIM1_BRK_TIM15_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY ${doc.STM32_IRQ_TIM1_UP_TIM16_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY ${doc.STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM1_CC_PRIORITY ${doc.STM32_IRQ_TIM1_CC_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM2_PRIORITY ${doc.STM32_IRQ_TIM2_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM6_PRIORITY ${doc.STM32_IRQ_TIM6_PRIORITY!"7"}
|
||||
#define STM32_IRQ_TIM7_PRIORITY ${doc.STM32_IRQ_TIM7_PRIORITY!"7"}
|
||||
|
||||
#define STM32_IRQ_USART1_PRIORITY ${doc.STM32_IRQ_USART1_PRIORITY!"12"}
|
||||
#define STM32_IRQ_USART2_PRIORITY ${doc.STM32_IRQ_USART2_PRIORITY!"12"}
|
||||
#define STM32_IRQ_LPUART1_PRIORITY ${doc.STM32_IRQ_LPUART1_PRIORITY!"12"}
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_COMPACT_SAMPLES ${doc.STM32_ADC_COMPACT_SAMPLES!"FALSE"}
|
||||
#define STM32_ADC_USE_ADC1 ${doc.STM32_ADC_USE_ADC1!"FALSE"}
|
||||
#define STM32_ADC_ADC1_DMA_STREAM ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 1)"}
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_USE_ADC2 ${doc.STM32_ADC_USE_ADC2!"FALSE"}
|
||||
#define STM32_ADC_ADC2_DMA_STREAM ${doc.STM32_ADC_ADC2_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_ADC_ADC2_DMA_PRIORITY ${doc.STM32_ADC_ADC2_DMA_PRIORITY!"2"}
|
||||
#define STM32_ADC_ADC12_IRQ_PRIORITY ${doc.STM32_ADC_ADC12_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY ${doc.STM32_ADC_ADC2_DMA_IRQ_PRIORITY!"5"}
|
||||
#define STM32_ADC_ADC123_CLOCK_MODE ${doc.STM32_ADC_ADC123_CLOCK_MODE!"ADC_CCR_CKMODE_AHB_DIV1"}
|
||||
#define STM32_ADC_ADC123_PRESC ${doc.STM32_ADC_ADC123_PRESC!"ADC_CCR_PRESC_DIV2"}
|
||||
|
||||
|
||||
/*
|
||||
* GPT driver system settings.
|
||||
*/
|
||||
#define STM32_GPT_USE_TIM1 ${doc.STM32_GPT_USE_TIM1!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM2 ${doc.STM32_GPT_USE_TIM2!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM6 ${doc.STM32_GPT_USE_TIM6!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM7 ${doc.STM32_GPT_USE_TIM7!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM15 ${doc.STM32_GPT_USE_TIM15!"FALSE"}
|
||||
#define STM32_GPT_USE_TIM16 ${doc.STM32_GPT_USE_TIM16!"FALSE"}
|
||||
|
||||
/*
|
||||
* I2C driver system settings.
|
||||
*/
|
||||
#define STM32_I2C_USE_I2C1 ${doc.STM32_I2C_USE_I2C1!"FALSE"}
|
||||
#define STM32_I2C_USE_I2C3 ${doc.STM32_I2C_USE_I2C3!"FALSE"}
|
||||
#define STM32_I2C_BUSY_TIMEOUT ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}
|
||||
#define STM32_I2C_I2C1_RX_DMA_STREAM ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_I2C_I2C1_TX_DMA_STREAM ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_I2C_I2C3_RX_DMA_STREAM ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
|
||||
#define STM32_I2C_I2C3_TX_DMA_STREAM ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
|
||||
#define STM32_I2C_I2C1_IRQ_PRIORITY ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C3_IRQ_PRIORITY ${doc.STM32_I2C_I2C3_IRQ_PRIORITY!"5"}
|
||||
#define STM32_I2C_I2C1_DMA_PRIORITY ${doc.STM32_I2C_I2C1_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_I2C3_DMA_PRIORITY ${doc.STM32_I2C_I2C3_DMA_PRIORITY!"3"}
|
||||
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) ${doc.STM32_I2C_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ICU driver system settings.
|
||||
*/
|
||||
#define STM32_ICU_USE_TIM1 ${doc.STM32_ICU_USE_TIM1!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM2 ${doc.STM32_ICU_USE_TIM2!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM15 ${doc.STM32_ICU_USE_TIM15!"FALSE"}
|
||||
#define STM32_ICU_USE_TIM16 ${doc.STM32_ICU_USE_TIM16!"FALSE"}
|
||||
|
||||
/*
|
||||
* PWM driver system settings.
|
||||
*/
|
||||
#define STM32_PWM_USE_ADVANCED ${doc.STM32_PWM_USE_ADVANCED!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM1 ${doc.STM32_PWM_USE_TIM1!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM2 ${doc.STM32_PWM_USE_TIM2!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM15 ${doc.STM32_PWM_USE_TIM15!"FALSE"}
|
||||
#define STM32_PWM_USE_TIM16 ${doc.STM32_PWM_USE_TIM16!"FALSE"}
|
||||
|
||||
/*
|
||||
* RTC driver system settings.
|
||||
*/
|
||||
#define STM32_RTC_PRESA_VALUE ${doc.STM32_RTC_PRESA_VALUE!"32"}
|
||||
#define STM32_RTC_PRESS_VALUE ${doc.STM32_RTC_PRESS_VALUE!"1024"}
|
||||
#define STM32_RTC_CR_INIT ${doc.STM32_RTC_CR_INIT!"0"}
|
||||
#define STM32_RTC_TAMPCR_INIT ${doc.STM32_RTC_TAMPCR_INIT!"0"}
|
||||
|
||||
/*
|
||||
* SERIAL driver system settings.
|
||||
*/
|
||||
#define STM32_SERIAL_USE_USART1 ${doc.STM32_SERIAL_USE_USART1!"FALSE"}
|
||||
#define STM32_SERIAL_USE_USART2 ${doc.STM32_SERIAL_USE_USART2!"FALSE"}
|
||||
#define STM32_SERIAL_USE_LPUART1 ${doc.STM32_SERIAL_USE_LPUART1!"FALSE"}
|
||||
|
||||
/*
|
||||
* SIO driver system settings.
|
||||
*/
|
||||
#define STM32_SIO_USE_USART1 ${doc.STM32_SIO_USE_USART1!"FALSE"}
|
||||
#define STM32_SIO_USE_USART2 ${doc.STM32_SIO_USE_USART2!"FALSE"}
|
||||
#define STM32_SIO_USE_LPUART1 ${doc.STM32_SIO_USE_LPUART1!"FALSE"}
|
||||
|
||||
/*
|
||||
* SPI driver system settings.
|
||||
*/
|
||||
#define STM32_SPI_USE_SPI1 ${doc.STM32_SPI_USE_SPI1!"FALSE"}
|
||||
#define STM32_SPI_SPI1_RX_DMA_STREAM ${doc.STM32_SPI_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}
|
||||
#define STM32_SPI_SPI1_TX_DMA_STREAM ${doc.STM32_SPI_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}
|
||||
#define STM32_SPI_SPI1_DMA_PRIORITY ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"}
|
||||
#define STM32_SPI_SPI1_IRQ_PRIORITY ${doc.STM32_SPI_SPI1_IRQ_PRIORITY!"10"}
|
||||
#define STM32_SPI_DMA_ERROR_HOOK(spip) ${doc.STM32_SPI_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* ST driver system settings.
|
||||
*/
|
||||
#define STM32_ST_IRQ_PRIORITY ${doc.STM32_ST_IRQ_PRIORITY!"8"}
|
||||
#define STM32_ST_USE_TIMER ${doc.STM32_ST_USE_TIMER!"2"}
|
||||
|
||||
/*
|
||||
* TRNG driver system settings.
|
||||
*/
|
||||
#define STM32_TRNG_USE_RNG1 ${doc.STM32_TRNG_USE_RNG1!"FALSE"}
|
||||
|
||||
/*
|
||||
* UART driver system settings.
|
||||
*/
|
||||
#define STM32_UART_USE_USART1 ${doc.STM32_UART_USE_USART1!"FALSE"}
|
||||
#define STM32_UART_USE_USART2 ${doc.STM32_UART_USE_USART2!"FALSE"}
|
||||
#define STM32_UART_USART1_RX_DMA_STREAM ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
#define STM32_UART_USART1_TX_DMA_STREAM ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 6)"}
|
||||
#define STM32_UART_USART2_RX_DMA_STREAM ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
|
||||
#define STM32_UART_USART2_TX_DMA_STREAM ${doc.STM32_UART_USART2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
|
||||
#define STM32_UART_DMA_ERROR_HOOK(uartp) ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
|
||||
|
||||
/*
|
||||
* USB driver system settings.
|
||||
*/
|
||||
#define STM32_USB_USE_USB1 ${doc.STM32_USB_USE_USB1!"FALSE"}
|
||||
#define STM32_USB_LOW_POWER_ON_SUSPEND ${doc.STM32_USB_LOW_POWER_ON_SUSPEND!"FALSE"}
|
||||
#define STM32_USB_USB1_HP_IRQ_PRIORITY ${doc.STM32_USB_USB1_HP_IRQ_PRIORITY!"13"}
|
||||
#define STM32_USB_USB1_LP_IRQ_PRIORITY ${doc.STM32_USB_USB1_LP_IRQ_PRIORITY!"14"}
|
||||
|
||||
/*
|
||||
* WDG driver system settings.
|
||||
*/
|
||||
#define STM32_WDG_USE_IWDG ${doc.STM32_WDG_USE_IWDG!"FALSE"}
|
||||
|
||||
/*
|
||||
* WSPI driver system settings.
|
||||
*/
|
||||
#define STM32_WSPI_USE_QUADSPI1 ${doc.STM32_WSPI_USE_QUADSPI1!"FALSE"}
|
||||
#define STM32_WSPI_QUADSPI1_DMA_STREAM ${doc.STM32_WSPI_QUADSPI1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
|
||||
#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE ${doc.STM32_WSPI_QUADSPI1_PRESCALER_VALUE!"1"}
|
||||
|
||||
#endif /* MCUCONF_H */
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
#!/bin/bash
|
||||
if [ $# -eq 2 ]
|
||||
then
|
||||
if [ $1 = "rootpath" ]
|
||||
then
|
||||
find $2 -name "mcuconf.h" -exec bash update_mcuconf_stm32l422xx.sh "{}" \;
|
||||
else
|
||||
echo "Usage: update_mcuconf_stm32l422xx.sh [rootpath <root path>]"
|
||||
fi
|
||||
elif [ $# -eq 1 ]
|
||||
then
|
||||
declare conffile=$(<$1)
|
||||
if egrep -q "STM32L422_MCUCONF" <<< "$conffile"
|
||||
then
|
||||
echo Processing: $1
|
||||
egrep -e "\#define\s+[a-zA-Z0-9_()]*\s+[^\s]" <<< "$conffile" | sed -r 's/\#define\s+([a-zA-Z0-9_]*)(\([^)]*\))?\s+/\1=/g' > ./values.txt
|
||||
if ! fmpp -q -C conf.fmpp -S ../ftl/processors/conf/mcuconf_stm32l422xx
|
||||
then
|
||||
echo
|
||||
echo "aborted"
|
||||
exit 1
|
||||
fi
|
||||
cp ./mcuconf.h $1
|
||||
rm ./mcuconf.h ./values.txt
|
||||
fi
|
||||
else
|
||||
echo "Usage: update_mcuconf_stm32l422xx.sh [rootpath <root path>]"
|
||||
echo " update_mcuconf_stm32l422xx.sh <configuration file>]"
|
||||
fi
|
||||
Loading…
Reference in New Issue