More STM32C0-related work.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@16352 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio
parent
a636ba64c7
commit
1014f947e9
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@ -72,7 +72,7 @@
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* @note Allowed values are 16 or 32 bits.
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*/
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#if !defined(CH_CFG_ST_RESOLUTION)
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#define CH_CFG_ST_RESOLUTION 32
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#define CH_CFG_ST_RESOLUTION 16
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#endif
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/**
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@ -57,7 +57,7 @@
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#define STM32_HSE_ENABLED FALSE
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#define STM32_LSI_ENABLED TRUE
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#define STM32_LSE_ENABLED TRUE
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#define STM32_SW STM32_SW_PLLRCLK
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#define STM32_SW STM32_SW_HSISYS
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#define STM32_HPRE STM32_HPRE_DIV1
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#define STM32_PPRE STM32_PPRE_DIV1
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#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
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@ -72,7 +72,7 @@
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#define STM32_USART1SEL STM32_USART1SEL_PCLK
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#define STM32_I2C1SEL STM32_I2C1SEL_PCLK
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#define STM32_I2S1SEL STM32_I2S1SEL_SYSCLK
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#define STM32_ADCSEL STM32_ADCSEL_PLLPCLK
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#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
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#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK
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/*
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@ -46,8 +46,8 @@
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/* Handling differences in ST headers.*/
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#if !defined(STM32H7XX) && !defined(STM32L4XX) && !defined(STM32L4XXP) && \
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!defined(STM32G0XX) && !defined(STM32G4XX) && !defined(STM32WBXX) && \
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!defined(STM32WLXX)
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!defined(STM32C0XX) && !defined(STM32G0XX) && !defined(STM32G4XX) && \
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!defined(STM32WBXX) && !defined(STM32WLXX)
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#define EMR1 EMR
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#define IMR1 IMR
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#define PR1 PR
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@ -0,0 +1,92 @@
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file RCCv1/stm32_bd.inc
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* @brief Shared backup domain handler.
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*
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* @addtogroup STM32_BD_V3_HANDLER
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* @{
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*/
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief Initializes the backup domain.
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*/
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__STATIC_INLINE void bd_init(void) {
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uint32_t bdcr;
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/* Current settings.*/
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bdcr = RCC->CSR1;
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#if HAL_USE_RTC
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/* RTC enable.*/
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if ((bdcr & RCC_CSR1_RTCEN) == 0U) {
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bdcr |= RCC_CSR1_RTCEN;
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}
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#endif
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/* Selectors.*/
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bdcr &= ~(STM32_RTCSEL_MASK | STM32_LSCOSEL_MASK);
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bdcr |= STM32_RTCSEL | STM32_LSCOSEL;
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/* Final settings.*/
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RCC->CSR1 = bdcr;
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}
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/**
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* @brief Resets the backup domain.
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* @note WARNING! Changing RTC clock source impossible without reset
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* of the whole BKP domain.
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*/
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__STATIC_INLINE void bd_reset(void) {
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/* Reset BKP domain if different clock source selected.*/
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if ((RCC->CSR1 & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
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/* Backup domain reset.*/
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RCC->CSR1 = RCC_CSR1_RTCRST;
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RCC->CSR1 = 0U;
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}
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/** @} */
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@ -95,7 +95,7 @@ __STATIC_INLINE void hsi48_disable(void) {
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__STATIC_INLINE void hsi48_init(void) {
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#if STM32_HSI48_ENABLED
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#if (defined(RCC_CRRCR_HSI48ON) || defined(RCC_CR_HSI48ON)) && STM32_HSI48_ENABLED
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/* HSI activation.*/
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hsi48_enable();
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#endif
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@ -0,0 +1,106 @@
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file RCCv1/stm32_lse_v3.inc
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* @brief Shared LSE clock handler.
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*
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* @addtogroup STM32_LSE_V3_HANDLER
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* @{
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*/
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/* Registry checks for robustness.*/
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#if !defined(STM32_RCC_HAS_LSE)
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#error "STM32_RCC_HAS_LSE not defined in stm32_registry.h"
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#endif
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/* Checks on configurations.*/
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#if !defined(STM32_LSE_ENABLED)
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#error "STM32_LSE_ENABLED not defined in mcuconf.h"
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#endif
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#if !defined(STM32_LSECLK)
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#error "STM32_LSECLK not defined in board.h"
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#endif
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#if !defined(STM32_LSEDRV)
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#error "STM32_LSEDRV not defined in board.h"
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#endif
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/* Check on limits.*/
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#if !defined(STM32_LSECLK_MAX)
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#error "STM32_LSECLK_MAX not defined in hal_lld.h"
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#endif
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#if !defined(STM32_LSECLK_MIN)
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#error "STM32_LSECLK_MIN not defined in hal_lld.h"
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#endif
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#if STM32_LSE_ENABLED
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#if (STM32_LSECLK == 0)
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#error "LSE frequency not defined"
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#endif
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#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
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#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
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#endif
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#endif
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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__STATIC_INLINE void lse_init(void) {
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#if STM32_LSE_ENABLED
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/* LSE activation.*/
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#if defined(STM32_LSE_BYPASS)
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/* LSE Bypass.*/
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RCC->CSR1 |= STM32_LSEDRV | RCC_CSR1_LSEON | RCC_CSR1_LSESYSEN | RCC_CSR1_LSEBYP;
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#else
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/* No LSE Bypass.*/
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RCC->CSR1 |= STM32_LSEDRV | RCC_CSR1_LSEON;
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while ((RCC->CSR1 & RCC_CSR1_LSERDY) != RCC_CSR1_LSERDY) {
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}
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#endif
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#endif
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/** @} */
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@ -0,0 +1,113 @@
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file RCCv1/stm32_lsi.inc
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* @brief Shared LSI clock handler.
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*
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* @addtogroup STM32_LSI_V3_HANDLER
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* @{
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*/
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/**
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* @brief LSI clock frequency.
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*/
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#define STM32_LSIRCCLK 32000U
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/**
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* @name RCC_CSR2 register bits definitions
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* @{
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*/
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#define STM32_LSIPRE_MASK (1U << RCC_CSR2_LSIPRE_Pos)
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#define STM32_LSIPRE_NODIV (0U << RCC_CSR2_LSIPRE_Pos)
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#define STM32_LSIPRE_DIV128 (1U << RCC_CSR2_LSIPRE_Pos)
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/* Registry checks for robustness.*/
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#if !defined(STM32_RCC_HAS_LSI)
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#error "STM32_RCC_HAS_LSI not defined in stm32_registry.h"
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#endif
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#if !defined(STM32_RCC_HAS_LSI_PRESCALER)
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#error "STM32_RCC_HAS_LSI_PRESCALER not defined in stm32_registry.h"
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#endif
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/* Checks on configurations.*/
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#if !defined(STM32_LSI_ENABLED)
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#error "STM32_LSI_ENABLED not defined in mcuconf.h"
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#endif
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#if STM32_RCC_HAS_LSI_PRESCALER || defined(__DOXYGEN__)
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#if !defined(STM32_LSIPRE)
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#error "STM32_LSIPRE not defined in mcuconf.h"
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#endif
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/**
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* @brief LSI frequency.
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*/
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#if (STM32_LSIPRE == STM32_LSIPRE_NODIV) || defined(__DOXYGEN__)
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#define STM32_LSICLK (STM32_LSIRCCLK)
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#elif STM32_LSIPRE == STM32_LSIPRE_DIV128
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#define STM32_LSICLK (STM32_LSIRCCLK / 128U)
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#else
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#error "invalid STM32_LSIPRE value specified"
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#endif
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#else /* !STM32_RCC_HAS_LSI_PRESCALER */
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#define STM32_LSIPRE 0U
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#define STM32_LSICLK (STM32_LSIRCCLK)
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#endif /* !STM32_RCC_HAS_LSI_PRESCALER */
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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__STATIC_INLINE void lsi_init(void) {
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#if STM32_LSI_ENABLED
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/* LSI activation.*/
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RCC->CSR2 |= STM32_LSIPRE | RCC_CSR2_LSION;
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while ((RCC->CSR2 & RCC_CSR2_LSIRDY) == 0U) {
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}
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#endif
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/** @} */
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@ -61,8 +61,8 @@
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#elif defined(STM32L4XX) || defined(STM32L4XXP) || defined(STM32G4XX) || \
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defined(STM32L5XX) || defined(STM32WBXX) || defined(STM32WLXX)
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#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM1_STOP
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#elif defined(STM32G0XX)
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#define ST_ENABLE_STOP() DBG->APBFZ1 |= DBG_APB_FZ1_DBG_TIM1_STOP
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#elif defined(STM32G0XX) || defined(STM32C0XX)
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#define ST_ENABLE_STOP() DBG->APBFZ2 |= DBG_APB_FZ2_DBG_TIM1_STOP
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#elif defined(STM32H7XX)
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#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM1
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#else
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@ -88,7 +88,7 @@
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#elif defined(STM32L4XX) || defined(STM32L4XXP) || defined(STM32G4XX) || \
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defined(STM32L5XX) || defined(STM32WBXX) || defined(STM32WLXX)
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#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM2_STOP
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#elif defined(STM32G0XX)
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#elif defined(STM32G0XX) || defined(STM32C0XX)
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#define ST_ENABLE_STOP() DBG->APBFZ1 |= DBG_APB_FZ1_DBG_TIM2_STOP
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#elif defined(STM32H7XX)
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#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM2
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@ -115,7 +115,7 @@
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#elif defined(STM32L4XX) || defined(STM32L4XXP) || defined(STM32G4XX) || \
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defined(STM32L5XX) || defined(STM32WBXX)
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#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM3_STOP
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#elif defined(STM32G0XX)
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#elif defined(STM32G0XX) || defined(STM32C0XX)
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#define ST_ENABLE_STOP() DBG->APBFZ1 |= DBG_APB_FZ1_DBG_TIM3_STOP
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#elif defined(STM32H7XX)
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#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM3
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@ -344,6 +344,8 @@
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#elif defined(STM32L4XX) || defined(STM32L4XXP) || defined(STM32G4XX) || \
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defined(STM32L5XX) || defined(STM32WBXX)
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#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM14_STOP
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#elif defined(STM32G0XX) || defined(STM32C0XX)
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#define ST_ENABLE_STOP() DBG->APBFZ2 |= DBG_APB_FZ2_DBG_TIM14_STOP
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#elif defined(STM32H7XX)
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#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM14
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#else
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@ -394,6 +396,8 @@
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#elif defined(STM32L4XX) || defined(STM32L4XXP) || defined(STM32G4XX) || \
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defined(STM32L5XX) || defined(STM32WLXX)
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#define ST_ENABLE_STOP() DBGMCU->APB2FZ |= DBGMCU_APB2FZ_DBG_TIM16_STOP
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#elif defined(STM32G0XX) || defined(STM32C0XX)
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#define ST_ENABLE_STOP() DBG->APBFZ2 |= DBG_APB_FZ2_DBG_TIM16_STOP
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#elif defined(STM32WBXX)
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#define ST_ENABLE_STOP() DBGMCU->APB2FZR |= DBGMCU_APB2FZR_DBG_TIM16_STOP
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#elif defined(STM32H7XX)
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@ -421,6 +425,8 @@
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#elif defined(STM32L4XX) || defined(STM32L4XXP) || defined(STM32G4XX) || \
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defined(STM32L5XX) || defined(STM32WLXX)
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#define ST_ENABLE_STOP() DBGMCU->APB2FZ |= DBGMCU_APB2FZ_DBG_TIM17_STOP
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#elif defined(STM32G0XX) || defined(STM32C0XX)
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#define ST_ENABLE_STOP() DBG->APBFZ2 |= DBG_APB_FZ2_DBG_TIM17_STOP
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#elif defined(STM32WBXX)
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#define ST_ENABLE_STOP() DBGMCU->APB2FZR |= DBGMCU_APB2FZR_DBG_TIM17_STOP
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#elif defined(STM32H7XX)
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@ -71,7 +71,7 @@ uint32_t SystemCoreClock = STM32_HCLK;
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/* Driver local functions. */
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/*===========================================================================*/
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#include "stm32_bd.inc"
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#include "stm32_bd_v3.inc"
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/**
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* @brief Safe setting of flash ACR register.
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@ -11,7 +11,7 @@
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distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
limitations under the License.f
|
||||
*/
|
||||
|
||||
/**
|
||||
|
|
@ -121,26 +121,6 @@
|
|||
#define STM32_SW_LSI (3U << 0)
|
||||
#define STM32_SW_LSE (4U << 0)
|
||||
|
||||
#define STM32_HPRE_DIV_MASK (15U << 8)
|
||||
#define STM32_HPRE_DIV_FIELD(n) ((n) << 8)
|
||||
#define STM32_HPRE_DIV1 STM32_HPRE_DIV_FIELD(0U)
|
||||
#define STM32_HPRE_DIV2 STM32_HPRE_DIV_FIELD(8U)
|
||||
#define STM32_HPRE_DIV4 STM32_HPRE_DIV_FIELD(9U)
|
||||
#define STM32_HPRE_DIV8 STM32_HPRE_DIV_FIELD(10U)
|
||||
#define STM32_HPRE_DIV16 STM32_HPRE_DIV_FIELD(11U)
|
||||
#define STM32_HPRE_DIV64 STM32_HPRE_DIV_FIELD(12U)
|
||||
#define STM32_HPRE_DIV128 STM32_HPRE_DIV_FIELD(13U)
|
||||
#define STM32_HPRE_DIV256 STM32_HPRE_DIV_FIELD(14U)
|
||||
#define STM32_HPRE_DIV512 STM32_HPRE_DIV_FIELD(15U)
|
||||
|
||||
#define STM32_PPRE_DIV_MASK (15U << 12)
|
||||
#define STM32_PPRE_DIV_FIELD(n) ((n) << 12)
|
||||
#define STM32_PPRE_DIV1 STM32_PPRE_DIV_FIELD(0U)
|
||||
#define STM32_PPRE_DIV2 STM32_PPRE_DIV_FIELD(4U)
|
||||
#define STM32_PPRE_DIV4 STM32_PPRE_DIV_FIELD(5U)
|
||||
#define STM32_PPRE_DIV8 STM32_PPRE_DIV_FIELD(6U)
|
||||
#define STM32_PPRE_DIV16 STM32_PPRE_DIV_FIELD(7U)
|
||||
|
||||
#define STM32_MCO2SEL_MASK (7U << 16)
|
||||
#define STM32_MCO2SEL_FIELD(n) ((n) << 16)
|
||||
#define STM32_MCO2SEL_NOCLOCK STM32_MCO2SEL_FIELD(0U)
|
||||
|
|
@ -524,8 +504,8 @@
|
|||
/** @} */
|
||||
|
||||
/* Clock handlers.*/
|
||||
#include "stm32_lse.inc"
|
||||
#include "stm32_lsi.inc"
|
||||
#include "stm32_lse_v3.inc"
|
||||
#include "stm32_lsi_v3.inc"
|
||||
#include "stm32_hsi48.inc"
|
||||
#include "stm32_hse.inc"
|
||||
|
||||
|
|
|
|||
|
|
@ -1,8 +1,7 @@
|
|||
# Required platform files.
|
||||
PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/STM32C0xx/stm32_isr.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/STM32C0xx/hal_lld.c \
|
||||
$(CHIBIOS)/os/hal/ports/STM32/STM32C0xx/hal_efl_lld.c
|
||||
$(CHIBIOS)/os/hal/ports/STM32/STM32C0xx/hal_lld.c
|
||||
|
||||
# Required include directories.
|
||||
PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
|
||||
|
|
|
|||
|
|
@ -68,7 +68,7 @@
|
|||
#define STM32_HSE_ENABLED ${doc.STM32_HSE_ENABLED!"FALSE"}
|
||||
#define STM32_LSI_ENABLED ${doc.STM32_LSI_ENABLED!"FALSE"}
|
||||
#define STM32_LSE_ENABLED ${doc.STM32_LSE_ENABLED!"FALSE"}
|
||||
#define STM32_SW ${doc.STM32_SW!"STM32_SW_HSI48"}
|
||||
#define STM32_SW ${doc.STM32_SW!"STM32_SW_HSISYS"}
|
||||
#define STM32_HPRE ${doc.STM32_HPRE!"STM32_HPRE_DIV1"}
|
||||
#define STM32_PPRE ${doc.STM32_PPRE!"STM32_PPRE_DIV1"}
|
||||
#define STM32_MCOSEL ${doc.STM32_MCOSEL!"STM32_MCOSEL_NOCLOCK"}
|
||||
|
|
|
|||
Loading…
Reference in New Issue