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ChibiOS
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Fixed Bug #794 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9929 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Rocco Marco Guglielmi 2016-11-19 17:20:50 +00:00
parent cdfdb0f5ef
commit 103cd6bc02
15 changed files with 3 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
os/hal/ports/AVR/hal_icu_lld.c
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@ -53,7 +53,6 @@ static icu_registers_t regs_table[]=
#endif #endif
}; };
/*===========================================================================*/ /*===========================================================================*/
/* Driver exported variables. */ /* Driver exported variables. */
/*===========================================================================*/ /*===========================================================================*/

1
os/hal/ports/AVR/hal_pal_lld.h
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@ -227,7 +227,6 @@ typedef volatile avr_gpio_registers_t * ioportid_t;
#define IOPORTSPI1 ((volatile avr_gpio_registers_t *)&PIN_SPI1) #define IOPORTSPI1 ((volatile avr_gpio_registers_t *)&PIN_SPI1)
#endif #endif
/*===========================================================================*/ /*===========================================================================*/
/* Implementation, some of the following macros could be implemented as */ /* Implementation, some of the following macros could be implemented as */
/* functions, if so please put them in pal_lld.c. */ /* functions, if so please put them in pal_lld.c. */

1
os/hal/ports/AVR/hal_pwm_lld.c
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@ -560,7 +560,6 @@ void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
*regs_table[i].timsk &= ~(1 << (channel + 1)); *regs_table[i].timsk &= ~(1 << (channel + 1));
} }
#endif /* HAL_USE_PWM */ #endif /* HAL_USE_PWM */
/** @} */ /** @} */

1
os/hal/ports/AVR/hal_spi_lld.h
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@ -214,7 +214,6 @@ extern "C" {
uint8_t spi_lld_polled_exchange(SPIDriver *spip, uint8_t frame); uint8_t spi_lld_polled_exchange(SPIDriver *spip, uint8_t frame);
#endif #endif
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

1
os/hal/ports/STM32/LLD/SDIOv1/hal_sdc_lld.c
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@ -57,7 +57,6 @@ static union {
} u; } u;
#endif /* STM32_SDC_SDIO_UNALIGNED_SUPPORT */ #endif /* STM32_SDC_SDIO_UNALIGNED_SUPPORT */
/** /**
* @brief SDIO default configuration. * @brief SDIO default configuration.
*/ */

1
os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c
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@ -99,7 +99,6 @@ static union {
} u; } u;
#endif /* STM32_SDC_SDMMC_UNALIGNED_SUPPORT */ #endif /* STM32_SDC_SDMMC_UNALIGNED_SUPPORT */
/** /**
* @brief SDIO default configuration. * @brief SDIO default configuration.
*/ */

1
os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c
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@ -383,7 +383,6 @@ OSAL_IRQ_HANDLER(STM32_USART2_HANDLER) {
} }
#endif /* STM32_UART_USE_USART2 */ #endif /* STM32_UART_USE_USART2 */
#if defined(STM32_USART3_8_HANDLER) #if defined(STM32_USART3_8_HANDLER)
#if STM32_SERIAL_USE_USART3 || STM32_SERIAL_USE_UART4 || \ #if STM32_SERIAL_USE_USART3 || STM32_SERIAL_USE_UART4 || \
STM32_SERIAL_USE_UART5 || STM32_SERIAL_USE_USART6 || \ STM32_SERIAL_USE_UART5 || STM32_SERIAL_USE_USART6 || \

2
os/hal/ports/STM32/STM32F0xx/stm32_registry.h
View File

@ -1492,7 +1492,6 @@
#define STM32_HAS_DAC2_CH1 FALSE #define STM32_HAS_DAC2_CH1 FALSE
#define STM32_HAS_DAC2_CH2 FALSE #define STM32_HAS_DAC2_CH2 FALSE
/* DMA attributes.*/ /* DMA attributes.*/
#define STM32_ADVANCED_DMA TRUE #define STM32_ADVANCED_DMA TRUE
#define STM32_DMA_SUPPORTS_CSELR FALSE #define STM32_DMA_SUPPORTS_CSELR FALSE
@ -1714,7 +1713,6 @@
#define STM32_HAS_CRC TRUE #define STM32_HAS_CRC TRUE
#define STM32_CRC_PROGRAMMABLE TRUE #define STM32_CRC_PROGRAMMABLE TRUE
/*===========================================================================*/ /*===========================================================================*/
/* STM32F091xC, STM32F098xx. */ /* STM32F091xC, STM32F098xx. */
/*===========================================================================*/ /*===========================================================================*/

1
os/hal/ports/STM32/STM32F4xx/hal_lld.h
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@ -1945,7 +1945,6 @@
#define STM32_PLL48CLK 0 #define STM32_PLL48CLK 0
#endif /* !STM32_CLOCK48_REQUIRED */ #endif /* !STM32_CLOCK48_REQUIRED */
/** /**
* @brief Clock of timers connected to APB1 * @brief Clock of timers connected to APB1
* (Timers 2, 3, 4, 5, 6, 7, 12, 13, 14). * (Timers 2, 3, 4, 5, 6, 7, 12, 13, 14).

1
os/hal/ports/STM32/STM32L4xx/hal_lld.h
View File

@ -2073,7 +2073,6 @@
#define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_4WS #define STM32_MSI_FLASHBITS FLASH_ACR_LATENCY_4WS
#endif #endif
/*===========================================================================*/ /*===========================================================================*/
/* Driver data structures and types. */ /* Driver data structures and types. */
/*===========================================================================*/ /*===========================================================================*/

1
os/hal/ports/STM32/STM32L4xx/stm32_rcc.h
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@ -267,7 +267,6 @@
} }
/** @} */ /** @} */
/** /**
* @name ADC peripherals specific RCC operations * @name ADC peripherals specific RCC operations
* @{ * @{

1
os/hal/ports/STM32/STM32L4xx/stm32_registry.h
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@ -312,7 +312,6 @@
#define STM32_LPUART1_HANDLER Vector158 #define STM32_LPUART1_HANDLER Vector158
#define STM32_LPUART1_NUMBER 70 #define STM32_LPUART1_NUMBER 70
#define STM32_HAS_USART3 FALSE #define STM32_HAS_USART3 FALSE
#define STM32_HAS_UART4 FALSE #define STM32_HAS_UART4 FALSE
#define STM32_HAS_UART5 FALSE #define STM32_HAS_UART5 FALSE

1
os/hal/src/hal_qspi.c
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@ -92,7 +92,6 @@ void qspiStart(QSPIDriver *qspip, const QSPIConfig *config) {
osalDbgCheck((qspip != NULL) && (config != NULL)); osalDbgCheck((qspip != NULL) && (config != NULL));
osalSysLock(); osalSysLock();
osalDbgAssert((qspip->state == QSPI_STOP) || (qspip->state == QSPI_READY), osalDbgAssert((qspip->state == QSPI_STOP) || (qspip->state == QSPI_READY),

1
os/hal/src/hal_st.c
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@ -62,7 +62,6 @@ void stInit(void) {
st_lld_init(); st_lld_init();
} }
/** /**
* @brief Starts the alarm. * @brief Starts the alarm.
* @note Makes sure that no spurious alarms are triggered after * @note Makes sure that no spurious alarms are triggered after

4
readme.txt
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@ -148,7 +148,9 @@
- RT: Merged RT4. - RT: Merged RT4.
- NIL: Merged NIL2. - NIL: Merged NIL2.
- NIL: Added STM32F7 demo. - NIL: Added STM32F7 demo.
- RT: Fixed double empty lines (bug #793)(backported to 16.1.6, 3.0.6). - HAL: Fixed double empty lines in HAL (bug #794)backported to 16.1.6,
3.0.6, 2.6.10).
- RT: Fixed double empty lines in RT (bug #793)(backported to 16.1.6, 3.0.6).
- HAL: Fixed wrong entries in STM32L4 registry (bug #792)(backported to - HAL: Fixed wrong entries in STM32L4 registry (bug #792)(backported to
16.1.6). 16.1.6).
- HAL: Fixed missing ARPE bit in CR1 initialization on STM32 GPT driver - HAL: Fixed missing ARPE bit in CR1 initialization on STM32 GPT driver