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Improved make system. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11049 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio 2017-11-21 12:54:54 +00:00
parent c010f378ca
commit 10465f7238
138 changed files with 1240 additions and 663 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
os/common/abstractions/cmsis_os/cmsis_os.mk
View File

@ -2,3 +2,7 @@
CMSISRTOSSRC = ${CHIBIOS}/os/common/abstractions/cmsis_os/cmsis_os.c
CMSISRTOSINC = ${CHIBIOS}/os/common/abstractions/cmsis_os
# Shared variables
ALLCSRC += $(CMSISRTOSSRC)
ALLINC += $(CMSISRTOSINC)

4
os/common/abstractions/nasa_cfe/osal/cfe_osal.mk
View File

@ -2,3 +2,7 @@
CFEOSALSRC = $(CHIBIOS)/os/common/abstractions/nasa_cfe/osal/src/osapi.c
CFEOSALINC = $(CHIBIOS)/os/common/abstractions/nasa_cfe/osal/include
# Shared variables
ALLCSRC += $(CFEOSALSRC)
ALLINC += $(CFEOSALINC)

4
os/common/abstractions/nasa_cfe/psp/cfe_psp.mk
View File

@ -5,3 +5,7 @@ CFEPSPSRC = $(CHIBIOS)/os/common/abstractions/nasa_cfe/psp/src/cfe_psp_support.c
$(CHIBIOS)/os/common/abstractions/nasa_cfe/psp/src/cfe_psp_exception.c
CFEPSPINC = $(CHIBIOS)/os/common/abstractions/nasa_cfe/psp/include
# Shared variables
ALLCSRC += $(CFEPSPSRC)
ALLINC += $(CFEPSPINC)

5
os/common/ports/ARM/compilers/GCC/mk/port_generic.mk
View File

@ -5,3 +5,8 @@ PORTASM = $(CHIBIOS)/os/common/ports/ARM/compilers/GCC/chcoreasm.S
PORTINC = ${CHIBIOS}/os/common/ports/ARM \
${CHIBIOS}/os/common/ports/ARM/compilers/GCC
# Shared variables
ALLASM += $(PORTASM)
ALLCSRC += $(PORTSRC)
ALLINC += $(PORTINC)

5
os/common/ports/ARMCAx-TZ/compilers/GCC/mk/port_generic.mk
View File

@ -6,3 +6,8 @@ PORTASM = $(CHIBIOS)/os/common/ports/ARMCAx-TZ/compilers/GCC/chcoreasm.S \
PORTINC = ${CHIBIOS}/os/common/ports/ARMCAx-TZ \
${CHIBIOS}/os/common/ports/ARMCAx-TZ/compilers/GCC
# Shared variables
ALLASM += $(PORTASM)
ALLCSRC += $(PORTSRC)
ALLINC += $(PORTINC)

5
os/common/ports/ARMCMx/compilers/GCC/mk/port_v6m.mk
View File

@ -6,3 +6,8 @@ PORTASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/chcoreasm_v6m.S
PORTINC = $(CHIBIOS)/os/common/ports/ARMCMx \
$(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC
# Shared variables
ALLASM += $(PORTASM)
ALLCSRC += $(PORTSRC)
ALLINC += $(PORTINC)

5
os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
View File

@ -6,3 +6,8 @@ PORTASM = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.S
PORTINC = $(CHIBIOS)/os/common/ports/ARMCMx \
$(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC
# Shared variables
ALLASM += $(PORTASM)
ALLCSRC += $(PORTSRC)
ALLINC += $(PORTINC)

5
os/common/ports/AVR/compilers/GCC/mk/port.mk
View File

@ -5,3 +5,8 @@ PORTASM =
PORTINC = ${CHIBIOS}/os/common/ports/AVR \
${CHIBIOS}/os/common/ports/AVR/compilers/GCC
# Shared variables
ALLASM += $(PORTASM)
ALLCSRC += $(PORTSRC)
ALLINC += $(PORTINC)

5
os/common/ports/SIMIA32/compilers/GCC/port.mk
View File

@ -5,3 +5,8 @@ PORTASM =
PORTINC = ${CHIBIOS}/os/common/ports/SIMIA32/compilers/GCC \
${CHIBIOS}/os/common/ports/SIMIA32
# Shared variables
ALLASM += $(PORTASM)
ALLCSRC += $(PORTSRC)
ALLINC += $(PORTINC)

5
os/common/ports/e200/compilers/GCC/mk/port.mk
View File

@ -6,3 +6,8 @@ PORTASM = $(CHIBIOS)/os/common/ports/e200/compilers/GCC/ivor.S \
PORTINC = $(CHIBIOS)/os/common/ports/e200 \
$(CHIBIOS)/os/common/ports/e200/compilers/GCC
# Shared variables
ALLASM += $(PORTASM)
ALLCSRC += $(PORTSRC)
ALLINC += $(PORTINC)

5
os/common/ports/e200/compilers/GHS/mk/port.mk
View File

@ -6,3 +6,8 @@ PORTASM = $(CHIBIOS)/os/common/ports/e200/compilers/GHS/ivor.s \
PORTINC = $(CHIBIOS)/os/common/ports/e200 \
$(CHIBIOS)/os/common/ports/e200/compilers/GHS
# Shared variables
ALLASM += $(PORTASM)
ALLCSRC += $(PORTSRC)
ALLINC += $(PORTINC)

5
os/common/startup/ARM/compilers/GCC/mk/startup_lpc214x.mk
View File

@ -7,3 +7,8 @@ STARTUPASM = $(CHIBIOS)/os/common/startup/ARM/compilers/GCC/vectors.S \
STARTUPINC = ${CHIBIOS}/os/common/startup/ARM/devices/LPC214x
STARTUPLD = ${CHIBIOS}/os/common/startup/ARM/compilers/GCC/ld
# Shared variables
ALLASM += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

5
os/common/startup/ARM/compilers/GCC/mk/startup_sama5d2.mk
View File

@ -9,3 +9,8 @@ STARTUPINC = ${CHIBIOS}/os/common/startup/ARM/devices/SAMA5D2 \
$(CHIBIOS)/os/common/ext/ARM/CMSIS/Core_A/Include
STARTUPLD = ${CHIBIOS}/os/common/startup/ARM/compilers/GCC/ld
# Shared variables
ALLASM += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

5
os/common/startup/ARMCAx-TZ/compilers/GCC/mk/startup_sama5d2.mk
View File

@ -9,3 +9,8 @@ STARTUPINC = ${CHIBIOS}/os/common/startup/ARMCAx-TZ/devices/SAMA5D2 \
$(CHIBIOS)/os/common/ext/ARM/CMSIS/Core_A/Include
STARTUPLD = ${CHIBIOS}/os/common/startup/ARMCAx-TZ/compilers/GCC/ld
# Shared variables
ALLASM += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

5
os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f0xx.mk
View File

@ -10,3 +10,8 @@ STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
$(CHIBIOS)/os/common/ext/ST/STM32F0xx
STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
# Shared variables
ALLASM += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

5
os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f1xx.mk
View File

@ -10,3 +10,8 @@ STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
$(CHIBIOS)/os/common/ext/ST/STM32F1xx
STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
# Shared variables
ALLASM += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

5
os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f2xx.mk
View File

@ -10,3 +10,8 @@ STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
$(CHIBIOS)/os/common/ext/ST/STM32F2xx
STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
# Shared variables
ALLASM += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

5
os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f3xx.mk
View File

@ -10,3 +10,8 @@ STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
$(CHIBIOS)/os/common/ext/ST/STM32F3xx
STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
# Shared variables
ALLASM += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

5
os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk
View File

@ -10,3 +10,8 @@ STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
$(CHIBIOS)/os/common/ext/ST/STM32F4xx
STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
# Shared variables
ALLASM += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

5
os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f7xx.mk
View File

@ -10,3 +10,8 @@ STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
$(CHIBIOS)/os/common/ext/ST/STM32F7xx
STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
# Shared variables
ALLASM += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

5
os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l0xx.mk
View File

@ -10,3 +10,8 @@ STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
$(CHIBIOS)/os/common/ext/ST/STM32L0xx
STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
# Shared variables
ALLASM += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

5
os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l1xx.mk
View File

@ -10,3 +10,8 @@ STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
$(CHIBIOS)/os/common/ext/ST/STM32L1xx
STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
# Shared variables
ALLASM += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

5
os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32l4xx.mk
View File

@ -10,3 +10,8 @@ STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
$(CHIBIOS)/os/common/ext/ST/STM32L4xx
STARTUPLD = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/ld
# Shared variables
ALLASM += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

5
os/common/startup/e200/compilers/GCC/mk/startup_spc560bcxx.mk
View File

@ -9,3 +9,8 @@ STARTUPINC = ${CHIBIOS}/os/common/startup/e200/compilers/GCC \
${CHIBIOS}/os/common/startup/e200/devices/SPC560BCxx
STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GCC/ld
# Shared variables
ALLASM += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

5
os/common/startup/e200/compilers/GCC/mk/startup_spc560bxx.mk
View File

@ -9,3 +9,8 @@ STARTUPINC = ${CHIBIOS}/os/common/startup/e200/compilers/GCC \
${CHIBIOS}/os/common/startup/e200/devices/SPC560Bxx
STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GCC/ld
# Shared variables
ALLASM += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

5
os/common/startup/e200/compilers/GCC/mk/startup_spc560dxx.mk
View File

@ -9,3 +9,8 @@ STARTUPINC = ${CHIBIOS}/os/common/startup/e200/compilers/GCC \
${CHIBIOS}/os/common/startup/e200/devices/SPC560Dxx
STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GCC/ld
# Shared variables
ALLASM += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

5
os/common/startup/e200/compilers/GCC/mk/startup_spc560pxx.mk
View File

@ -9,3 +9,8 @@ STARTUPINC = ${CHIBIOS}/os/common/startup/e200/compilers/GCC \
${CHIBIOS}/os/common/startup/e200/devices/SPC560Pxx
STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GCC/ld
# Shared variables
ALLASM += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

5
os/common/startup/e200/compilers/GCC/mk/startup_spc563mxx.mk
View File

@ -9,3 +9,8 @@ STARTUPINC = ${CHIBIOS}/os/common/startup/e200/compilers/GCC \
${CHIBIOS}/os/common/startup/e200/devices/SPC563Mxx
STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GCC/ld
# Shared variables
ALLASM += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

5
os/common/startup/e200/compilers/GCC/mk/startup_spc564axx.mk
View File

@ -9,3 +9,8 @@ STARTUPINC = ${CHIBIOS}/os/common/startup/e200/compilers/GCC \
${CHIBIOS}/os/common/startup/e200/devices/SPC564Axx
STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GCC/ld
# Shared variables
ALLASM += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

5
os/common/startup/e200/compilers/GCC/mk/startup_spc56ecxx.mk
View File

@ -9,3 +9,8 @@ STARTUPINC = ${CHIBIOS}/os/common/startup/e200/compilers/GCC \
${CHIBIOS}/os/common/startup/e200/devices/SPC56ECxx
STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GCC/ld
# Shared variables
ALLASM += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

5
os/common/startup/e200/compilers/GCC/mk/startup_spc56elxx.mk
View File

@ -9,3 +9,8 @@ STARTUPINC = ${CHIBIOS}/os/common/startup/e200/compilers/GCC \
${CHIBIOS}/os/common/startup/e200/devices/SPC56ELxx
STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GCC/ld
# Shared variables
ALLASM += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

5
os/common/startup/e200/compilers/GHS/mk/startup_spc560bcxx.mk
View File

@ -9,3 +9,8 @@ STARTUPINC = ${CHIBIOS}/os/common/startup/e200/compilers/GHS \
${CHIBIOS}/os/common/startup/e200/devices/SPC560BCxx
STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GHS/ld
# Shared variables
ALLASM += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

5
os/common/startup/e200/compilers/GHS/mk/startup_spc560bxx.mk
View File

@ -9,3 +9,8 @@ STARTUPINC = ${CHIBIOS}/os/common/startup/e200/compilers/GHS \
${CHIBIOS}/os/common/startup/e200/devices/SPC560Bxx
STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GHS/ld
# Shared variables
ALLASM += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

5
os/common/startup/e200/compilers/GHS/mk/startup_spc560dxx.mk
View File

@ -9,3 +9,8 @@ STARTUPINC = ${CHIBIOS}/os/common/startup/e200/compilers/GHS \
${CHIBIOS}/os/common/startup/e200/devices/SPC560Dxx
STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GHS/ld
# Shared variables
ALLASM += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

5
os/common/startup/e200/compilers/GHS/mk/startup_spc560pxx.mk
View File

@ -9,3 +9,8 @@ STARTUPINC = ${CHIBIOS}/os/common/startup/e200/compilers/GHS \
${CHIBIOS}/os/common/startup/e200/devices/SPC560Pxx
STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GHS/ld
# Shared variables
ALLASM += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

5
os/common/startup/e200/compilers/GHS/mk/startup_spc563mxx.mk
View File

@ -9,3 +9,8 @@ STARTUPINC = ${CHIBIOS}/os/common/startup/e200/compilers/GHS \
${CHIBIOS}/os/common/startup/e200/devices/SPC563Mxx
STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GHS/ld
# Shared variables
ALLASM += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

5
os/common/startup/e200/compilers/GHS/mk/startup_spc564axx.mk
View File

@ -9,3 +9,8 @@ STARTUPINC = ${CHIBIOS}/os/common/startup/e200/compilers/GHS \
${CHIBIOS}/os/common/startup/e200/devices/SPC564Axx
STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GHS/ld
# Shared variables
ALLASM += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

5
os/common/startup/e200/compilers/GHS/mk/startup_spc56ecxx.mk
View File

@ -9,3 +9,8 @@ STARTUPINC = ${CHIBIOS}/os/common/startup/e200/compilers/GHS \
${CHIBIOS}/os/common/startup/e200/devices/SPC56ECxx
STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GHS/ld
# Shared variables
ALLASM += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

5
os/common/startup/e200/compilers/GHS/mk/startup_spc56elxx.mk
View File

@ -9,3 +9,8 @@ STARTUPINC = ${CHIBIOS}/os/common/startup/e200/compilers/GHS \
${CHIBIOS}/os/common/startup/e200/devices/SPC56ELxx
STARTUPLD = ${CHIBIOS}/os/common/startup/e200/compilers/GHS/ld
# Shared variables
ALLASM += $(STARTUPASM)
ALLCSRC += $(STARTUPSRC)
ALLINC += $(STARTUPINC)

4
os/ex/Micron/m25q.mk
View File

@ -6,3 +6,7 @@ M25QSRC := $(CHIBIOS)/os/hal/lib/peripherals/flash/hal_flash.c \
# Required include directories
M25QINC := $(CHIBIOS)/os/hal/lib/peripherals/flash \
$(CHIBIOS)/os/ex/Micron
# Shared variables
ALLCSRC += $(M25QSRC)
ALLINC += $(M25QINC)

4
os/hal/boards/MIKROE_CLICKER2_STM32/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/MIKROE_CLICKER_2_FOR_STM32/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/MIKROE_CLICKER_2_FOR_STM32
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/OLIMEX_STM32_E407/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/OLIMEX_STM32_E407/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/OLIMEX_STM32_E407
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/OLIMEX_STM32_E407_REV_D/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/OLIMEX_STM32_E407_REV_D/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/OLIMEX_STM32_E407_REV_D
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/OLIMEX_STM32_H407/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/OLIMEX_STM32_H407/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/OLIMEX_STM32_H407
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_NUCLEO144_F207ZG/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F207ZG/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F207ZG
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_NUCLEO144_F303ZE/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F303ZE/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F303ZE
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

13
os/hal/boards/ST_NUCLEO144_F412ZG/board.c
View File

@ -14,6 +14,11 @@
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)
@ -59,14 +64,6 @@ const PALConfig pal_default_config = {
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
#endif
#if STM32_HAS_GPIOJ
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
#endif
#if STM32_HAS_GPIOK
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
#endif
};
#endif

363
os/hal/boards/ST_NUCLEO144_F412ZG/board.h
View File

@ -14,8 +14,13 @@
limitations under the License.
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#ifndef BOARD_H
#define BOARD_H
/*
* Setup for STMicroelectronics STM32 Nucleo144-F412ZG board.
@ -625,22 +630,22 @@
PIN_ODR_HIGH(GPIOA_SWDIO) | \
PIN_ODR_HIGH(GPIOA_SWCLK) | \
PIN_ODR_HIGH(GPIOA_ZIO_D20))
#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ZIO_D32, 0) | \
PIN_AFIO_AF(GPIOA_PIN1, 0) | \
PIN_AFIO_AF(GPIOA_ZIO_A8, 0) | \
PIN_AFIO_AF(GPIOA_ARD_A0, 0) | \
PIN_AFIO_AF(GPIOA_ZIO_D24, 0) | \
PIN_AFIO_AF(GPIOA_ARD_D13, 0) | \
PIN_AFIO_AF(GPIOA_ARD_D12, 0) | \
PIN_AFIO_AF(GPIOA_ARD_D11, 0))
#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_USB_SOF, 10) | \
PIN_AFIO_AF(GPIOA_USB_VBUS, 0) | \
PIN_AFIO_AF(GPIOA_USB_ID, 10) | \
PIN_AFIO_AF(GPIOA_USB_DM, 10) | \
PIN_AFIO_AF(GPIOA_USB_DP, 10) | \
PIN_AFIO_AF(GPIOA_SWDIO, 0) | \
PIN_AFIO_AF(GPIOA_SWCLK, 0) | \
PIN_AFIO_AF(GPIOA_ZIO_D20, 6))
#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ZIO_D32, 0U) | \
PIN_AFIO_AF(GPIOA_PIN1, 0U) | \
PIN_AFIO_AF(GPIOA_ZIO_A8, 0U) | \
PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \
PIN_AFIO_AF(GPIOA_ZIO_D24, 0U) | \
PIN_AFIO_AF(GPIOA_ARD_D13, 0U) | \
PIN_AFIO_AF(GPIOA_ARD_D12, 0U) | \
PIN_AFIO_AF(GPIOA_ARD_D11, 0U))
#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_USB_SOF, 10U) | \
PIN_AFIO_AF(GPIOA_USB_VBUS, 0U) | \
PIN_AFIO_AF(GPIOA_USB_ID, 10U) | \
PIN_AFIO_AF(GPIOA_USB_DM, 10U) | \
PIN_AFIO_AF(GPIOA_USB_DP, 10U) | \
PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \
PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \
PIN_AFIO_AF(GPIOA_ZIO_D20, 6U))
/*
* GPIOB setup:
@ -742,22 +747,22 @@
PIN_ODR_HIGH(GPIOB_ZIO_D18) | \
PIN_ODR_LOW(GPIOB_LED3) | \
PIN_ODR_HIGH(GPIOB_ZIO_D17))
#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ZIO_D33, 0) | \
PIN_AFIO_AF(GPIOB_ZIO_A6, 0) | \
PIN_AFIO_AF(GPIOB_ZIO_D27, 0) | \
PIN_AFIO_AF(GPIOB_ZIO_D23, 0) | \
PIN_AFIO_AF(GPIOB_ZIO_D25, 0) | \
PIN_AFIO_AF(GPIOB_ZIO_D22, 0) | \
PIN_AFIO_AF(GPIOB_ZIO_D26, 0) | \
PIN_AFIO_AF(GPIOB_LED2, 0))
#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_ARD_D15, 0) | \
PIN_AFIO_AF(GPIOB_ARD_D14, 0) | \
PIN_AFIO_AF(GPIOB_ZIO_D36, 0) | \
PIN_AFIO_AF(GPIOB_ZIO_D35, 0) | \
PIN_AFIO_AF(GPIOB_ZIO_D19, 0) | \
PIN_AFIO_AF(GPIOB_ZIO_D18, 0) | \
PIN_AFIO_AF(GPIOB_LED3, 0) | \
PIN_AFIO_AF(GPIOB_ZIO_D17, 0))
#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ZIO_D33, 0U) | \
PIN_AFIO_AF(GPIOB_ZIO_A6, 0U) | \
PIN_AFIO_AF(GPIOB_ZIO_D27, 0U) | \
PIN_AFIO_AF(GPIOB_ZIO_D23, 0U) | \
PIN_AFIO_AF(GPIOB_ZIO_D25, 0U) | \
PIN_AFIO_AF(GPIOB_ZIO_D22, 0U) | \
PIN_AFIO_AF(GPIOB_ZIO_D26, 0U) | \
PIN_AFIO_AF(GPIOB_LED2, 0U))
#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_ARD_D15, 0U) | \
PIN_AFIO_AF(GPIOB_ARD_D14, 0U) | \
PIN_AFIO_AF(GPIOB_ZIO_D36, 0U) | \
PIN_AFIO_AF(GPIOB_ZIO_D35, 0U) | \
PIN_AFIO_AF(GPIOB_ZIO_D19, 0U) | \
PIN_AFIO_AF(GPIOB_ZIO_D18, 0U) | \
PIN_AFIO_AF(GPIOB_LED3, 0U) | \
PIN_AFIO_AF(GPIOB_ZIO_D17, 0U))
/*
* GPIOC setup:
@ -859,22 +864,22 @@
PIN_ODR_HIGH(GPIOC_BUTTON) | \
PIN_ODR_HIGH(GPIOC_OSC32_IN) | \
PIN_ODR_HIGH(GPIOC_OSC32_OUT))
#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ARD_A1, 0) | \
PIN_AFIO_AF(GPIOC_ARD_A3, 0) | \
PIN_AFIO_AF(GPIOC_ZIO_A7, 0) | \
PIN_AFIO_AF(GPIOC_ARD_A2, 0) | \
PIN_AFIO_AF(GPIOC_ARD_A4, 0) | \
PIN_AFIO_AF(GPIOC_ARD_A5, 0) | \
PIN_AFIO_AF(GPIOC_ZIO_D16, 0) | \
PIN_AFIO_AF(GPIOC_ZIO_D21, 0))
#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_ZIO_D43, 0) | \
PIN_AFIO_AF(GPIOC_ZIO_D44, 0) | \
PIN_AFIO_AF(GPIOC_ZIO_D45, 0) | \
PIN_AFIO_AF(GPIOC_ZIO_D46, 0) | \
PIN_AFIO_AF(GPIOC_ZIO_D47, 0) | \
PIN_AFIO_AF(GPIOC_BUTTON, 0) | \
PIN_AFIO_AF(GPIOC_OSC32_IN, 0) | \
PIN_AFIO_AF(GPIOC_OSC32_OUT, 0))
#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ARD_A1, 0U) | \
PIN_AFIO_AF(GPIOC_ARD_A3, 0U) | \
PIN_AFIO_AF(GPIOC_ZIO_A7, 0U) | \
PIN_AFIO_AF(GPIOC_ARD_A2, 0U) | \
PIN_AFIO_AF(GPIOC_ARD_A4, 0U) | \
PIN_AFIO_AF(GPIOC_ARD_A5, 0U) | \
PIN_AFIO_AF(GPIOC_ZIO_D16, 0U) | \
PIN_AFIO_AF(GPIOC_ZIO_D21, 0U))
#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_ZIO_D43, 0U) | \
PIN_AFIO_AF(GPIOC_ZIO_D44, 0U) | \
PIN_AFIO_AF(GPIOC_ZIO_D45, 0U) | \
PIN_AFIO_AF(GPIOC_ZIO_D46, 0U) | \
PIN_AFIO_AF(GPIOC_ZIO_D47, 0U) | \
PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \
PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \
PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U))
/*
* GPIOD setup:
@ -976,22 +981,22 @@
PIN_ODR_HIGH(GPIOD_ZIO_D28) | \
PIN_ODR_HIGH(GPIOD_ARD_D10) | \
PIN_ODR_HIGH(GPIOD_ARD_D9))
#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_ZIO_D67, 0) | \
PIN_AFIO_AF(GPIOD_ZIO_D66, 0) | \
PIN_AFIO_AF(GPIOD_ZIO_D48, 0) | \
PIN_AFIO_AF(GPIOD_ZIO_D55, 0) | \
PIN_AFIO_AF(GPIOD_ZIO_D54, 0) | \
PIN_AFIO_AF(GPIOD_ZIO_D53, 0) | \
PIN_AFIO_AF(GPIOD_ZIO_D52, 0) | \
PIN_AFIO_AF(GPIOD_ZIO_D51, 0))
#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_USART3_RX, 7) | \
PIN_AFIO_AF(GPIOD_USART3_TX, 7) | \
PIN_AFIO_AF(GPIOD_PIN10, 0) | \
PIN_AFIO_AF(GPIOD_ZIO_D30, 0) | \
PIN_AFIO_AF(GPIOD_ZIO_D29, 0) | \
PIN_AFIO_AF(GPIOD_ZIO_D28, 0) | \
PIN_AFIO_AF(GPIOD_ARD_D10, 0) | \
PIN_AFIO_AF(GPIOD_ARD_D9, 0))
#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_ZIO_D67, 0U) | \
PIN_AFIO_AF(GPIOD_ZIO_D66, 0U) | \
PIN_AFIO_AF(GPIOD_ZIO_D48, 0U) | \
PIN_AFIO_AF(GPIOD_ZIO_D55, 0U) | \
PIN_AFIO_AF(GPIOD_ZIO_D54, 0U) | \
PIN_AFIO_AF(GPIOD_ZIO_D53, 0U) | \
PIN_AFIO_AF(GPIOD_ZIO_D52, 0U) | \
PIN_AFIO_AF(GPIOD_ZIO_D51, 0U))
#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_USART3_RX, 7U) | \
PIN_AFIO_AF(GPIOD_USART3_TX, 7U) | \
PIN_AFIO_AF(GPIOD_PIN10, 0U) | \
PIN_AFIO_AF(GPIOD_ZIO_D30, 0U) | \
PIN_AFIO_AF(GPIOD_ZIO_D29, 0U) | \
PIN_AFIO_AF(GPIOD_ZIO_D28, 0U) | \
PIN_AFIO_AF(GPIOD_ARD_D10, 0U) | \
PIN_AFIO_AF(GPIOD_ARD_D9, 0U))
/*
* GPIOE setup:
@ -1093,22 +1098,22 @@
PIN_ODR_HIGH(GPIOE_ARD_D3) | \
PIN_ODR_HIGH(GPIOE_ZIO_D38) | \
PIN_ODR_HIGH(GPIOE_ZIO_D37))
#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_ZIO_D34, 0) | \
PIN_AFIO_AF(GPIOE_PIN1, 0) | \
PIN_AFIO_AF(GPIOE_ZIO_D31, 0) | \
PIN_AFIO_AF(GPIOE_ZIO_D60, 0) | \
PIN_AFIO_AF(GPIOE_ZIO_D57, 0) | \
PIN_AFIO_AF(GPIOE_ZIO_D58, 0) | \
PIN_AFIO_AF(GPIOE_ZIO_D59, 0) | \
PIN_AFIO_AF(GPIOE_ZIO_D41, 0))
#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_ZIO_D42, 0) | \
PIN_AFIO_AF(GPIOE_ARD_D6, 0) | \
PIN_AFIO_AF(GPIOE_ZIO_D40, 0) | \
PIN_AFIO_AF(GPIOE_ARD_D5, 0) | \
PIN_AFIO_AF(GPIOE_ZIO_D39, 0) | \
PIN_AFIO_AF(GPIOE_ARD_D3, 0) | \
PIN_AFIO_AF(GPIOE_ZIO_D38, 0) | \
PIN_AFIO_AF(GPIOE_ZIO_D37, 0))
#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_ZIO_D34, 0U) | \
PIN_AFIO_AF(GPIOE_PIN1, 0U) | \
PIN_AFIO_AF(GPIOE_ZIO_D31, 0U) | \
PIN_AFIO_AF(GPIOE_ZIO_D60, 0U) | \
PIN_AFIO_AF(GPIOE_ZIO_D57, 0U) | \
PIN_AFIO_AF(GPIOE_ZIO_D58, 0U) | \
PIN_AFIO_AF(GPIOE_ZIO_D59, 0U) | \
PIN_AFIO_AF(GPIOE_ZIO_D41, 0U))
#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_ZIO_D42, 0U) | \
PIN_AFIO_AF(GPIOE_ARD_D6, 0U) | \
PIN_AFIO_AF(GPIOE_ZIO_D40, 0U) | \
PIN_AFIO_AF(GPIOE_ARD_D5, 0U) | \
PIN_AFIO_AF(GPIOE_ZIO_D39, 0U) | \
PIN_AFIO_AF(GPIOE_ARD_D3, 0U) | \
PIN_AFIO_AF(GPIOE_ZIO_D38, 0U) | \
PIN_AFIO_AF(GPIOE_ZIO_D37, 0U))
/*
* GPIOF setup:
@ -1210,22 +1215,22 @@
PIN_ODR_HIGH(GPIOF_ARD_D7) | \
PIN_ODR_HIGH(GPIOF_ARD_D4) | \
PIN_ODR_HIGH(GPIOF_ARD_D2))
#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_ZIO_D68, 0) | \
PIN_AFIO_AF(GPIOF_ZIO_D69, 0) | \
PIN_AFIO_AF(GPIOF_ZIO_D70, 0) | \
PIN_AFIO_AF(GPIOF_PIN3, 0) | \
PIN_AFIO_AF(GPIOF_PIN4, 0) | \
PIN_AFIO_AF(GPIOF_PIN5, 0) | \
PIN_AFIO_AF(GPIOF_PIN6, 0) | \
PIN_AFIO_AF(GPIOF_ZIO_D62, 0))
#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_ZIO_D61, 0) | \
PIN_AFIO_AF(GPIOF_ZIO_D63, 0) | \
PIN_AFIO_AF(GPIOF_PIN10, 0) | \
PIN_AFIO_AF(GPIOF_PIN11, 0) | \
PIN_AFIO_AF(GPIOF_ARD_D8, 0) | \
PIN_AFIO_AF(GPIOF_ARD_D7, 0) | \
PIN_AFIO_AF(GPIOF_ARD_D4, 0) | \
PIN_AFIO_AF(GPIOF_ARD_D2, 0))
#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_ZIO_D68, 0U) | \
PIN_AFIO_AF(GPIOF_ZIO_D69, 0U) | \
PIN_AFIO_AF(GPIOF_ZIO_D70, 0U) | \
PIN_AFIO_AF(GPIOF_PIN3, 0U) | \
PIN_AFIO_AF(GPIOF_PIN4, 0U) | \
PIN_AFIO_AF(GPIOF_PIN5, 0U) | \
PIN_AFIO_AF(GPIOF_PIN6, 0U) | \
PIN_AFIO_AF(GPIOF_ZIO_D62, 0U))
#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_ZIO_D61, 0U) | \
PIN_AFIO_AF(GPIOF_ZIO_D63, 0U) | \
PIN_AFIO_AF(GPIOF_PIN10, 0U) | \
PIN_AFIO_AF(GPIOF_PIN11, 0U) | \
PIN_AFIO_AF(GPIOF_ARD_D8, 0U) | \
PIN_AFIO_AF(GPIOF_ARD_D7, 0U) | \
PIN_AFIO_AF(GPIOF_ARD_D4, 0U) | \
PIN_AFIO_AF(GPIOF_ARD_D2, 0U))
/*
* GPIOG setup:
@ -1327,22 +1332,22 @@
PIN_ODR_HIGH(GPIOG_PIN13) | \
PIN_ODR_HIGH(GPIOG_ARD_D1) | \
PIN_ODR_HIGH(GPIOG_PIN15))
#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_ZIO_D65, 0) | \
PIN_AFIO_AF(GPIOG_ZIO_D64, 0) | \
PIN_AFIO_AF(GPIOG_ZIO_D49, 0) | \
PIN_AFIO_AF(GPIOG_ZIO_D50, 0) | \
PIN_AFIO_AF(GPIOG_PIN4, 0) | \
PIN_AFIO_AF(GPIOG_PIN5, 0) | \
PIN_AFIO_AF(GPIOG_USB_GPIO_OUT, 0) | \
PIN_AFIO_AF(GPIOG_USB_GPIO_IN, 0))
#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0) | \
PIN_AFIO_AF(GPIOG_ARD_D0, 0) | \
PIN_AFIO_AF(GPIOG_PIN10, 0) | \
PIN_AFIO_AF(GPIOG_PIN11, 0) | \
PIN_AFIO_AF(GPIOG_PIN12, 0) | \
PIN_AFIO_AF(GPIOG_PIN13, 0) | \
PIN_AFIO_AF(GPIOG_ARD_D1, 0) | \
PIN_AFIO_AF(GPIOG_PIN15, 0))
#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_ZIO_D65, 0U) | \
PIN_AFIO_AF(GPIOG_ZIO_D64, 0U) | \
PIN_AFIO_AF(GPIOG_ZIO_D49, 0U) | \
PIN_AFIO_AF(GPIOG_ZIO_D50, 0U) | \
PIN_AFIO_AF(GPIOG_PIN4, 0U) | \
PIN_AFIO_AF(GPIOG_PIN5, 0U) | \
PIN_AFIO_AF(GPIOG_USB_GPIO_OUT, 0U) | \
PIN_AFIO_AF(GPIOG_USB_GPIO_IN, 0U))
#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \
PIN_AFIO_AF(GPIOG_ARD_D0, 0U) | \
PIN_AFIO_AF(GPIOG_PIN10, 0U) | \
PIN_AFIO_AF(GPIOG_PIN11, 0U) | \
PIN_AFIO_AF(GPIOG_PIN12, 0U) | \
PIN_AFIO_AF(GPIOG_PIN13, 0U) | \
PIN_AFIO_AF(GPIOG_ARD_D1, 0U) | \
PIN_AFIO_AF(GPIOG_PIN15, 0U))
/*
* GPIOH setup:
@ -1444,22 +1449,22 @@
PIN_ODR_HIGH(GPIOH_PIN13) | \
PIN_ODR_HIGH(GPIOH_PIN14) | \
PIN_ODR_HIGH(GPIOH_PIN15))
#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0) | \
PIN_AFIO_AF(GPIOH_OSC_OUT, 0) | \
PIN_AFIO_AF(GPIOH_PIN2, 0) | \
PIN_AFIO_AF(GPIOH_PIN3, 0) | \
PIN_AFIO_AF(GPIOH_PIN4, 0) | \
PIN_AFIO_AF(GPIOH_PIN5, 0) | \
PIN_AFIO_AF(GPIOH_PIN6, 0) | \
PIN_AFIO_AF(GPIOH_PIN7, 0))
#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \
PIN_AFIO_AF(GPIOH_PIN9, 0) | \
PIN_AFIO_AF(GPIOH_PIN10, 0) | \
PIN_AFIO_AF(GPIOH_PIN11, 0) | \
PIN_AFIO_AF(GPIOH_PIN12, 0) | \
PIN_AFIO_AF(GPIOH_PIN13, 0) | \
PIN_AFIO_AF(GPIOH_PIN14, 0) | \
PIN_AFIO_AF(GPIOH_PIN15, 0))
#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \
PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \
PIN_AFIO_AF(GPIOH_PIN2, 0U) | \
PIN_AFIO_AF(GPIOH_PIN3, 0U) | \
PIN_AFIO_AF(GPIOH_PIN4, 0U) | \
PIN_AFIO_AF(GPIOH_PIN5, 0U) | \
PIN_AFIO_AF(GPIOH_PIN6, 0U) | \
PIN_AFIO_AF(GPIOH_PIN7, 0U))
#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \
PIN_AFIO_AF(GPIOH_PIN9, 0U) | \
PIN_AFIO_AF(GPIOH_PIN10, 0U) | \
PIN_AFIO_AF(GPIOH_PIN11, 0U) | \
PIN_AFIO_AF(GPIOH_PIN12, 0U) | \
PIN_AFIO_AF(GPIOH_PIN13, 0U) | \
PIN_AFIO_AF(GPIOH_PIN14, 0U) | \
PIN_AFIO_AF(GPIOH_PIN15, 0U))
/*
* GPIOI setup:
@ -1561,22 +1566,22 @@
PIN_ODR_HIGH(GPIOI_PIN13) | \
PIN_ODR_HIGH(GPIOI_PIN14) | \
PIN_ODR_HIGH(GPIOI_PIN15))
#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0) | \
PIN_AFIO_AF(GPIOI_PIN1, 0) | \
PIN_AFIO_AF(GPIOI_PIN2, 0) | \
PIN_AFIO_AF(GPIOI_PIN3, 0) | \
PIN_AFIO_AF(GPIOI_PIN4, 0) | \
PIN_AFIO_AF(GPIOI_PIN5, 0) | \
PIN_AFIO_AF(GPIOI_PIN6, 0) | \
PIN_AFIO_AF(GPIOI_PIN7, 0))
#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \
PIN_AFIO_AF(GPIOI_PIN9, 0) | \
PIN_AFIO_AF(GPIOI_PIN10, 0) | \
PIN_AFIO_AF(GPIOI_PIN11, 0) | \
PIN_AFIO_AF(GPIOI_PIN12, 0) | \
PIN_AFIO_AF(GPIOI_PIN13, 0) | \
PIN_AFIO_AF(GPIOI_PIN14, 0) | \
PIN_AFIO_AF(GPIOI_PIN15, 0))
#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \
PIN_AFIO_AF(GPIOI_PIN1, 0U) | \
PIN_AFIO_AF(GPIOI_PIN2, 0U) | \
PIN_AFIO_AF(GPIOI_PIN3, 0U) | \
PIN_AFIO_AF(GPIOI_PIN4, 0U) | \
PIN_AFIO_AF(GPIOI_PIN5, 0U) | \
PIN_AFIO_AF(GPIOI_PIN6, 0U) | \
PIN_AFIO_AF(GPIOI_PIN7, 0U))
#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \
PIN_AFIO_AF(GPIOI_PIN9, 0U) | \
PIN_AFIO_AF(GPIOI_PIN10, 0U) | \
PIN_AFIO_AF(GPIOI_PIN11, 0U) | \
PIN_AFIO_AF(GPIOI_PIN12, 0U) | \
PIN_AFIO_AF(GPIOI_PIN13, 0U) | \
PIN_AFIO_AF(GPIOI_PIN14, 0U) | \
PIN_AFIO_AF(GPIOI_PIN15, 0U))
/*
* GPIOJ setup:
@ -1678,22 +1683,22 @@
PIN_ODR_HIGH(GPIOJ_PIN13) | \
PIN_ODR_HIGH(GPIOJ_PIN14) | \
PIN_ODR_HIGH(GPIOJ_PIN15))
#define VAL_GPIOJ_AFRL (PIN_AFIO_AF(GPIOJ_PIN0, 0) | \
PIN_AFIO_AF(GPIOJ_PIN1, 0) | \
PIN_AFIO_AF(GPIOJ_PIN2, 0) | \
PIN_AFIO_AF(GPIOJ_PIN3, 0) | \
PIN_AFIO_AF(GPIOJ_PIN4, 0) | \
PIN_AFIO_AF(GPIOJ_PIN5, 0) | \
PIN_AFIO_AF(GPIOJ_PIN6, 0) | \
PIN_AFIO_AF(GPIOJ_PIN7, 0))
#define VAL_GPIOJ_AFRH (PIN_AFIO_AF(GPIOJ_PIN8, 0) | \
PIN_AFIO_AF(GPIOJ_PIN9, 0) | \
PIN_AFIO_AF(GPIOJ_PIN10, 0) | \
PIN_AFIO_AF(GPIOJ_PIN11, 0) | \
PIN_AFIO_AF(GPIOJ_PIN12, 0) | \
PIN_AFIO_AF(GPIOJ_PIN13, 0) | \
PIN_AFIO_AF(GPIOJ_PIN14, 0) | \
PIN_AFIO_AF(GPIOJ_PIN15, 0))
#define VAL_GPIOJ_AFRL (PIN_AFIO_AF(GPIOJ_PIN0, 0U) | \
PIN_AFIO_AF(GPIOJ_PIN1, 0U) | \
PIN_AFIO_AF(GPIOJ_PIN2, 0U) | \
PIN_AFIO_AF(GPIOJ_PIN3, 0U) | \
PIN_AFIO_AF(GPIOJ_PIN4, 0U) | \
PIN_AFIO_AF(GPIOJ_PIN5, 0U) | \
PIN_AFIO_AF(GPIOJ_PIN6, 0U) | \
PIN_AFIO_AF(GPIOJ_PIN7, 0U))
#define VAL_GPIOJ_AFRH (PIN_AFIO_AF(GPIOJ_PIN8, 0U) | \
PIN_AFIO_AF(GPIOJ_PIN9, 0U) | \
PIN_AFIO_AF(GPIOJ_PIN10, 0U) | \
PIN_AFIO_AF(GPIOJ_PIN11, 0U) | \
PIN_AFIO_AF(GPIOJ_PIN12, 0U) | \
PIN_AFIO_AF(GPIOJ_PIN13, 0U) | \
PIN_AFIO_AF(GPIOJ_PIN14, 0U) | \
PIN_AFIO_AF(GPIOJ_PIN15, 0U))
/*
* GPIOK setup:
@ -1795,22 +1800,22 @@
PIN_ODR_HIGH(GPIOK_PIN13) | \
PIN_ODR_HIGH(GPIOK_PIN14) | \
PIN_ODR_HIGH(GPIOK_PIN15))
#define VAL_GPIOK_AFRL (PIN_AFIO_AF(GPIOK_PIN0, 0) | \
PIN_AFIO_AF(GPIOK_PIN1, 0) | \
PIN_AFIO_AF(GPIOK_PIN2, 0) | \
PIN_AFIO_AF(GPIOK_PIN3, 0) | \
PIN_AFIO_AF(GPIOK_PIN4, 0) | \
PIN_AFIO_AF(GPIOK_PIN5, 0) | \
PIN_AFIO_AF(GPIOK_PIN6, 0) | \
PIN_AFIO_AF(GPIOK_PIN7, 0))
#define VAL_GPIOK_AFRH (PIN_AFIO_AF(GPIOK_PIN8, 0) | \
PIN_AFIO_AF(GPIOK_PIN9, 0) | \
PIN_AFIO_AF(GPIOK_PIN10, 0) | \
PIN_AFIO_AF(GPIOK_PIN11, 0) | \
PIN_AFIO_AF(GPIOK_PIN12, 0) | \
PIN_AFIO_AF(GPIOK_PIN13, 0) | \
PIN_AFIO_AF(GPIOK_PIN14, 0) | \
PIN_AFIO_AF(GPIOK_PIN15, 0))
#define VAL_GPIOK_AFRL (PIN_AFIO_AF(GPIOK_PIN0, 0U) | \
PIN_AFIO_AF(GPIOK_PIN1, 0U) | \
PIN_AFIO_AF(GPIOK_PIN2, 0U) | \
PIN_AFIO_AF(GPIOK_PIN3, 0U) | \
PIN_AFIO_AF(GPIOK_PIN4, 0U) | \
PIN_AFIO_AF(GPIOK_PIN5, 0U) | \
PIN_AFIO_AF(GPIOK_PIN6, 0U) | \
PIN_AFIO_AF(GPIOK_PIN7, 0U))
#define VAL_GPIOK_AFRH (PIN_AFIO_AF(GPIOK_PIN8, 0U) | \
PIN_AFIO_AF(GPIOK_PIN9, 0U) | \
PIN_AFIO_AF(GPIOK_PIN10, 0U) | \
PIN_AFIO_AF(GPIOK_PIN11, 0U) | \
PIN_AFIO_AF(GPIOK_PIN12, 0U) | \
PIN_AFIO_AF(GPIOK_PIN13, 0U) | \
PIN_AFIO_AF(GPIOK_PIN14, 0U) | \
PIN_AFIO_AF(GPIOK_PIN15, 0U))
#if !defined(_FROM_ASM_)
@ -1823,4 +1828,4 @@ extern "C" {
#endif
#endif /* _FROM_ASM_ */
#endif /* _BOARD_H_ */
#endif /* BOARD_H */

4
os/hal/boards/ST_NUCLEO144_F412ZG/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F412ZG/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F412ZG
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_NUCLEO144_F429ZI/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F429ZI/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F429ZI
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_NUCLEO144_F446ZE/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F446ZE/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F446ZE
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_NUCLEO144_F746ZG/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F746ZG/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F746ZG
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_NUCLEO144_F767ZI/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F767ZI/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_F767ZI
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_NUCLEO32_F031K6/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_F031K6/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_F031K6
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_NUCLEO32_F042K6/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_F042K6/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_F042K6
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_NUCLEO32_F303K8/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_F303K8/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_F303K8
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_NUCLEO32_L011K4/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_L011K4/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_L011K4
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_NUCLEO32_L031K6/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_L031K6/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_L031K6
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

5
os/hal/boards/ST_NUCLEO32_L432KC/board.c
View File

@ -14,6 +14,11 @@
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)

267
os/hal/boards/ST_NUCLEO32_L432KC/board.h
View File

@ -14,8 +14,13 @@
limitations under the License.
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#ifndef BOARD_H
#define BOARD_H
/*
* Setup for STMicroelectronics STM32 Nucleo32-L432KC board.
@ -352,22 +357,22 @@
PIN_ODR_HIGH(GPIOA_SWDIO) | \
PIN_ODR_HIGH(GPIOA_SWCLK) | \
PIN_ODR_HIGH(GPIOA_VCP_RX))
#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ARD_A0, 0) | \
PIN_AFIO_AF(GPIOA_ARD_A1, 0) | \
PIN_AFIO_AF(GPIOA_VCP_TX, 7) | \
PIN_AFIO_AF(GPIOA_ARD_A2, 0) | \
PIN_AFIO_AF(GPIOA_ARD_A3, 0) | \
PIN_AFIO_AF(GPIOA_ARD_A4, 0) | \
PIN_AFIO_AF(GPIOA_ARD_A5, 0) | \
PIN_AFIO_AF(GPIOA_ARD_A6, 0))
#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_ARD_D9, 0) | \
PIN_AFIO_AF(GPIOA_ARD_D1, 0) | \
PIN_AFIO_AF(GPIOA_ARD_D0, 0) | \
PIN_AFIO_AF(GPIOA_ARD_D10, 0) | \
PIN_AFIO_AF(GPIOA_ARD_D2, 0) | \
PIN_AFIO_AF(GPIOA_SWDIO, 0) | \
PIN_AFIO_AF(GPIOA_SWCLK, 0) | \
PIN_AFIO_AF(GPIOA_VCP_RX, 3))
#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \
PIN_AFIO_AF(GPIOA_ARD_A1, 0U) | \
PIN_AFIO_AF(GPIOA_VCP_TX, 7U) | \
PIN_AFIO_AF(GPIOA_ARD_A2, 0U) | \
PIN_AFIO_AF(GPIOA_ARD_A3, 0U) | \
PIN_AFIO_AF(GPIOA_ARD_A4, 0U) | \
PIN_AFIO_AF(GPIOA_ARD_A5, 0U) | \
PIN_AFIO_AF(GPIOA_ARD_A6, 0U))
#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_ARD_D9, 0U) | \
PIN_AFIO_AF(GPIOA_ARD_D1, 0U) | \
PIN_AFIO_AF(GPIOA_ARD_D0, 0U) | \
PIN_AFIO_AF(GPIOA_ARD_D10, 0U) | \
PIN_AFIO_AF(GPIOA_ARD_D2, 0U) | \
PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \
PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \
PIN_AFIO_AF(GPIOA_VCP_RX, 3U))
#define VAL_GPIOA_ASCR (PIN_ASCR_DISABLED(GPIOA_ARD_A0) | \
PIN_ASCR_DISABLED(GPIOA_ARD_A1) | \
PIN_ASCR_DISABLED(GPIOA_VCP_TX) | \
@ -501,22 +506,22 @@
PIN_ODR_HIGH(GPIOB_PIN13) | \
PIN_ODR_HIGH(GPIOB_PIN14) | \
PIN_ODR_HIGH(GPIOB_PIN15))
#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ARD_D3, 0) | \
PIN_AFIO_AF(GPIOB_ARD_D6, 0) | \
PIN_AFIO_AF(GPIOB_PIN2, 0) | \
PIN_AFIO_AF(GPIOB_ARD_D13, 0) | \
PIN_AFIO_AF(GPIOB_ARD_D12, 0) | \
PIN_AFIO_AF(GPIOB_ARD_D11, 0) | \
PIN_AFIO_AF(GPIOB_ARD_D5, 0) | \
PIN_AFIO_AF(GPIOB_ARD_D4, 0))
#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | \
PIN_AFIO_AF(GPIOB_PIN9, 0) | \
PIN_AFIO_AF(GPIOB_PIN10, 0) | \
PIN_AFIO_AF(GPIOB_PIN11, 0) | \
PIN_AFIO_AF(GPIOB_PIN12, 0) | \
PIN_AFIO_AF(GPIOB_PIN13, 0) | \
PIN_AFIO_AF(GPIOB_PIN14, 0) | \
PIN_AFIO_AF(GPIOB_PIN15, 0))
#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ARD_D3, 0U) | \
PIN_AFIO_AF(GPIOB_ARD_D6, 0U) | \
PIN_AFIO_AF(GPIOB_PIN2, 0U) | \
PIN_AFIO_AF(GPIOB_ARD_D13, 0U) | \
PIN_AFIO_AF(GPIOB_ARD_D12, 0U) | \
PIN_AFIO_AF(GPIOB_ARD_D11, 0U) | \
PIN_AFIO_AF(GPIOB_ARD_D5, 0U) | \
PIN_AFIO_AF(GPIOB_ARD_D4, 0U))
#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \
PIN_AFIO_AF(GPIOB_PIN9, 0U) | \
PIN_AFIO_AF(GPIOB_PIN10, 0U) | \
PIN_AFIO_AF(GPIOB_PIN11, 0U) | \
PIN_AFIO_AF(GPIOB_PIN12, 0U) | \
PIN_AFIO_AF(GPIOB_PIN13, 0U) | \
PIN_AFIO_AF(GPIOB_PIN14, 0U) | \
PIN_AFIO_AF(GPIOB_PIN15, 0U))
#define VAL_GPIOB_ASCR (PIN_ASCR_DISABLED(GPIOB_ARD_D3) | \
PIN_ASCR_DISABLED(GPIOB_ARD_D6) | \
PIN_ASCR_DISABLED(GPIOB_PIN2) | \
@ -650,22 +655,22 @@
PIN_ODR_HIGH(GPIOC_PIN13) | \
PIN_ODR_HIGH(GPIOC_ARD_D7) | \
PIN_ODR_HIGH(GPIOC_ARD_D8))
#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0) | \
PIN_AFIO_AF(GPIOC_PIN1, 0) | \
PIN_AFIO_AF(GPIOC_PIN2, 0) | \
PIN_AFIO_AF(GPIOC_PIN3, 0) | \
PIN_AFIO_AF(GPIOC_PIN4, 0) | \
PIN_AFIO_AF(GPIOC_PIN5, 0) | \
PIN_AFIO_AF(GPIOC_PIN6, 0) | \
PIN_AFIO_AF(GPIOC_PIN7, 0))
#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0) | \
PIN_AFIO_AF(GPIOC_PIN9, 0) | \
PIN_AFIO_AF(GPIOC_PIN10, 0) | \
PIN_AFIO_AF(GPIOC_PIN11, 0) | \
PIN_AFIO_AF(GPIOC_PIN12, 0) | \
PIN_AFIO_AF(GPIOC_PIN13, 0) | \
PIN_AFIO_AF(GPIOC_ARD_D7, 0) | \
PIN_AFIO_AF(GPIOC_ARD_D8, 0))
#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \
PIN_AFIO_AF(GPIOC_PIN1, 0U) | \
PIN_AFIO_AF(GPIOC_PIN2, 0U) | \
PIN_AFIO_AF(GPIOC_PIN3, 0U) | \
PIN_AFIO_AF(GPIOC_PIN4, 0U) | \
PIN_AFIO_AF(GPIOC_PIN5, 0U) | \
PIN_AFIO_AF(GPIOC_PIN6, 0U) | \
PIN_AFIO_AF(GPIOC_PIN7, 0U))
#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \
PIN_AFIO_AF(GPIOC_PIN9, 0U) | \
PIN_AFIO_AF(GPIOC_PIN10, 0U) | \
PIN_AFIO_AF(GPIOC_PIN11, 0U) | \
PIN_AFIO_AF(GPIOC_PIN12, 0U) | \
PIN_AFIO_AF(GPIOC_PIN13, 0U) | \
PIN_AFIO_AF(GPIOC_ARD_D7, 0U) | \
PIN_AFIO_AF(GPIOC_ARD_D8, 0U))
#define VAL_GPIOC_ASCR (PIN_ASCR_DISABLED(GPIOC_PIN0) | \
PIN_ASCR_DISABLED(GPIOC_PIN1) | \
PIN_ASCR_DISABLED(GPIOC_PIN2) | \
@ -799,22 +804,22 @@
PIN_ODR_HIGH(GPIOD_PIN13) | \
PIN_ODR_HIGH(GPIOD_PIN14) | \
PIN_ODR_HIGH(GPIOD_PIN15))
#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \
PIN_AFIO_AF(GPIOD_PIN1, 0) | \
PIN_AFIO_AF(GPIOD_PIN2, 0) | \
PIN_AFIO_AF(GPIOD_PIN3, 0) | \
PIN_AFIO_AF(GPIOD_PIN4, 0) | \
PIN_AFIO_AF(GPIOD_PIN5, 0) | \
PIN_AFIO_AF(GPIOD_PIN6, 0) | \
PIN_AFIO_AF(GPIOD_PIN7, 0))
#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \
PIN_AFIO_AF(GPIOD_PIN9, 0) | \
PIN_AFIO_AF(GPIOD_PIN10, 0) | \
PIN_AFIO_AF(GPIOD_PIN11, 0) | \
PIN_AFIO_AF(GPIOD_PIN12, 0) | \
PIN_AFIO_AF(GPIOD_PIN13, 0) | \
PIN_AFIO_AF(GPIOD_PIN14, 0) | \
PIN_AFIO_AF(GPIOD_PIN15, 0))
#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \
PIN_AFIO_AF(GPIOD_PIN1, 0U) | \
PIN_AFIO_AF(GPIOD_PIN2, 0U) | \
PIN_AFIO_AF(GPIOD_PIN3, 0U) | \
PIN_AFIO_AF(GPIOD_PIN4, 0U) | \
PIN_AFIO_AF(GPIOD_PIN5, 0U) | \
PIN_AFIO_AF(GPIOD_PIN6, 0U) | \
PIN_AFIO_AF(GPIOD_PIN7, 0U))
#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \
PIN_AFIO_AF(GPIOD_PIN9, 0U) | \
PIN_AFIO_AF(GPIOD_PIN10, 0U) | \
PIN_AFIO_AF(GPIOD_PIN11, 0U) | \
PIN_AFIO_AF(GPIOD_PIN12, 0U) | \
PIN_AFIO_AF(GPIOD_PIN13, 0U) | \
PIN_AFIO_AF(GPIOD_PIN14, 0U) | \
PIN_AFIO_AF(GPIOD_PIN15, 0U))
#define VAL_GPIOD_ASCR (PIN_ASCR_DISABLED(GPIOD_PIN0) | \
PIN_ASCR_DISABLED(GPIOD_PIN1) | \
PIN_ASCR_DISABLED(GPIOD_PIN2) | \
@ -948,22 +953,22 @@
PIN_ODR_HIGH(GPIOE_PIN13) | \
PIN_ODR_HIGH(GPIOE_PIN14) | \
PIN_ODR_HIGH(GPIOE_PIN15))
#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0) | \
PIN_AFIO_AF(GPIOE_PIN1, 0) | \
PIN_AFIO_AF(GPIOE_PIN2, 0) | \
PIN_AFIO_AF(GPIOE_PIN3, 0) | \
PIN_AFIO_AF(GPIOE_PIN4, 0) | \
PIN_AFIO_AF(GPIOE_PIN5, 0) | \
PIN_AFIO_AF(GPIOE_PIN6, 0) | \
PIN_AFIO_AF(GPIOE_PIN7, 0))
#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0) | \
PIN_AFIO_AF(GPIOE_PIN9, 0) | \
PIN_AFIO_AF(GPIOE_PIN10, 0) | \
PIN_AFIO_AF(GPIOE_PIN11, 0) | \
PIN_AFIO_AF(GPIOE_PIN12, 0) | \
PIN_AFIO_AF(GPIOE_PIN13, 0) | \
PIN_AFIO_AF(GPIOE_PIN14, 0) | \
PIN_AFIO_AF(GPIOE_PIN15, 0))
#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \
PIN_AFIO_AF(GPIOE_PIN1, 0U) | \
PIN_AFIO_AF(GPIOE_PIN2, 0U) | \
PIN_AFIO_AF(GPIOE_PIN3, 0U) | \
PIN_AFIO_AF(GPIOE_PIN4, 0U) | \
PIN_AFIO_AF(GPIOE_PIN5, 0U) | \
PIN_AFIO_AF(GPIOE_PIN6, 0U) | \
PIN_AFIO_AF(GPIOE_PIN7, 0U))
#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \
PIN_AFIO_AF(GPIOE_PIN9, 0U) | \
PIN_AFIO_AF(GPIOE_PIN10, 0U) | \
PIN_AFIO_AF(GPIOE_PIN11, 0U) | \
PIN_AFIO_AF(GPIOE_PIN12, 0U) | \
PIN_AFIO_AF(GPIOE_PIN13, 0U) | \
PIN_AFIO_AF(GPIOE_PIN14, 0U) | \
PIN_AFIO_AF(GPIOE_PIN15, 0U))
#define VAL_GPIOE_ASCR (PIN_ASCR_DISABLED(GPIOE_PIN0) | \
PIN_ASCR_DISABLED(GPIOE_PIN1) | \
PIN_ASCR_DISABLED(GPIOE_PIN2) | \
@ -1097,22 +1102,22 @@
PIN_ODR_HIGH(GPIOF_PIN13) | \
PIN_ODR_HIGH(GPIOF_PIN14) | \
PIN_ODR_HIGH(GPIOF_PIN15))
#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0) | \
PIN_AFIO_AF(GPIOF_PIN1, 0) | \
PIN_AFIO_AF(GPIOF_PIN2, 0) | \
PIN_AFIO_AF(GPIOF_PIN3, 0) | \
PIN_AFIO_AF(GPIOF_PIN4, 0) | \
PIN_AFIO_AF(GPIOF_PIN5, 0) | \
PIN_AFIO_AF(GPIOF_PIN6, 0) | \
PIN_AFIO_AF(GPIOF_PIN7, 0))
#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \
PIN_AFIO_AF(GPIOF_PIN9, 0) | \
PIN_AFIO_AF(GPIOF_PIN10, 0) | \
PIN_AFIO_AF(GPIOF_PIN11, 0) | \
PIN_AFIO_AF(GPIOF_PIN12, 0) | \
PIN_AFIO_AF(GPIOF_PIN13, 0) | \
PIN_AFIO_AF(GPIOF_PIN14, 0) | \
PIN_AFIO_AF(GPIOF_PIN15, 0))
#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \
PIN_AFIO_AF(GPIOF_PIN1, 0U) | \
PIN_AFIO_AF(GPIOF_PIN2, 0U) | \
PIN_AFIO_AF(GPIOF_PIN3, 0U) | \
PIN_AFIO_AF(GPIOF_PIN4, 0U) | \
PIN_AFIO_AF(GPIOF_PIN5, 0U) | \
PIN_AFIO_AF(GPIOF_PIN6, 0U) | \
PIN_AFIO_AF(GPIOF_PIN7, 0U))
#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \
PIN_AFIO_AF(GPIOF_PIN9, 0U) | \
PIN_AFIO_AF(GPIOF_PIN10, 0U) | \
PIN_AFIO_AF(GPIOF_PIN11, 0U) | \
PIN_AFIO_AF(GPIOF_PIN12, 0U) | \
PIN_AFIO_AF(GPIOF_PIN13, 0U) | \
PIN_AFIO_AF(GPIOF_PIN14, 0U) | \
PIN_AFIO_AF(GPIOF_PIN15, 0U))
#define VAL_GPIOF_ASCR (PIN_ASCR_DISABLED(GPIOF_PIN0) | \
PIN_ASCR_DISABLED(GPIOF_PIN1) | \
PIN_ASCR_DISABLED(GPIOF_PIN2) | \
@ -1246,22 +1251,22 @@
PIN_ODR_HIGH(GPIOG_PIN13) | \
PIN_ODR_HIGH(GPIOG_PIN14) | \
PIN_ODR_HIGH(GPIOG_PIN15))
#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0) | \
PIN_AFIO_AF(GPIOG_PIN1, 0) | \
PIN_AFIO_AF(GPIOG_PIN2, 0) | \
PIN_AFIO_AF(GPIOG_PIN3, 0) | \
PIN_AFIO_AF(GPIOG_PIN4, 0) | \
PIN_AFIO_AF(GPIOG_PIN5, 0) | \
PIN_AFIO_AF(GPIOG_PIN6, 0) | \
PIN_AFIO_AF(GPIOG_PIN7, 0))
#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0) | \
PIN_AFIO_AF(GPIOG_PIN9, 0) | \
PIN_AFIO_AF(GPIOG_PIN10, 0) | \
PIN_AFIO_AF(GPIOG_PIN11, 0) | \
PIN_AFIO_AF(GPIOG_PIN12, 0) | \
PIN_AFIO_AF(GPIOG_PIN13, 0) | \
PIN_AFIO_AF(GPIOG_PIN14, 0) | \
PIN_AFIO_AF(GPIOG_PIN15, 0))
#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \
PIN_AFIO_AF(GPIOG_PIN1, 0U) | \
PIN_AFIO_AF(GPIOG_PIN2, 0U) | \
PIN_AFIO_AF(GPIOG_PIN3, 0U) | \
PIN_AFIO_AF(GPIOG_PIN4, 0U) | \
PIN_AFIO_AF(GPIOG_PIN5, 0U) | \
PIN_AFIO_AF(GPIOG_PIN6, 0U) | \
PIN_AFIO_AF(GPIOG_PIN7, 0U))
#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \
PIN_AFIO_AF(GPIOG_PIN9, 0U) | \
PIN_AFIO_AF(GPIOG_PIN10, 0U) | \
PIN_AFIO_AF(GPIOG_PIN11, 0U) | \
PIN_AFIO_AF(GPIOG_PIN12, 0U) | \
PIN_AFIO_AF(GPIOG_PIN13, 0U) | \
PIN_AFIO_AF(GPIOG_PIN14, 0U) | \
PIN_AFIO_AF(GPIOG_PIN15, 0U))
#define VAL_GPIOG_ASCR (PIN_ASCR_DISABLED(GPIOG_PIN0) | \
PIN_ASCR_DISABLED(GPIOG_PIN1) | \
PIN_ASCR_DISABLED(GPIOG_PIN2) | \
@ -1395,22 +1400,22 @@
PIN_ODR_HIGH(GPIOH_PIN13) | \
PIN_ODR_HIGH(GPIOH_PIN14) | \
PIN_ODR_HIGH(GPIOH_PIN15))
#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_PIN0, 0) | \
PIN_AFIO_AF(GPIOH_PIN1, 0) | \
PIN_AFIO_AF(GPIOH_PIN2, 0) | \
PIN_AFIO_AF(GPIOH_PIN3, 0) | \
PIN_AFIO_AF(GPIOH_PIN4, 0) | \
PIN_AFIO_AF(GPIOH_PIN5, 0) | \
PIN_AFIO_AF(GPIOH_PIN6, 0) | \
PIN_AFIO_AF(GPIOH_PIN7, 0))
#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \
PIN_AFIO_AF(GPIOH_PIN9, 0) | \
PIN_AFIO_AF(GPIOH_PIN10, 0) | \
PIN_AFIO_AF(GPIOH_PIN11, 0) | \
PIN_AFIO_AF(GPIOH_PIN12, 0) | \
PIN_AFIO_AF(GPIOH_PIN13, 0) | \
PIN_AFIO_AF(GPIOH_PIN14, 0) | \
PIN_AFIO_AF(GPIOH_PIN15, 0))
#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_PIN0, 0U) | \
PIN_AFIO_AF(GPIOH_PIN1, 0U) | \
PIN_AFIO_AF(GPIOH_PIN2, 0U) | \
PIN_AFIO_AF(GPIOH_PIN3, 0U) | \
PIN_AFIO_AF(GPIOH_PIN4, 0U) | \
PIN_AFIO_AF(GPIOH_PIN5, 0U) | \
PIN_AFIO_AF(GPIOH_PIN6, 0U) | \
PIN_AFIO_AF(GPIOH_PIN7, 0U))
#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \
PIN_AFIO_AF(GPIOH_PIN9, 0U) | \
PIN_AFIO_AF(GPIOH_PIN10, 0U) | \
PIN_AFIO_AF(GPIOH_PIN11, 0U) | \
PIN_AFIO_AF(GPIOH_PIN12, 0U) | \
PIN_AFIO_AF(GPIOH_PIN13, 0U) | \
PIN_AFIO_AF(GPIOH_PIN14, 0U) | \
PIN_AFIO_AF(GPIOH_PIN15, 0U))
#define VAL_GPIOH_ASCR (PIN_ASCR_DISABLED(GPIOH_PIN0) | \
PIN_ASCR_DISABLED(GPIOH_PIN1) | \
PIN_ASCR_DISABLED(GPIOH_PIN2) | \
@ -1455,4 +1460,4 @@ extern "C" {
#endif
#endif /* _FROM_ASM_ */
#endif /* _BOARD_H_ */
#endif /* BOARD_H */

4
os/hal/boards/ST_NUCLEO32_L432KC/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_L432KC/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_L432KC
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_NUCLEO64_F030R8/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F030R8/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F030R8
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_NUCLEO64_F070RB/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F070RB/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F070RB
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_NUCLEO64_F072RB/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F072RB/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F072RB
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_NUCLEO64_F091RC/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F091RC/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F091RC
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_NUCLEO64_F302R8/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F302R8/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F302R8
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_NUCLEO64_F303RE/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F303RE/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F303RE
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_NUCLEO64_F334R8/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F334R8/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F334R8
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_NUCLEO64_F401RE/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F401RE/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F401RE
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

13
os/hal/boards/ST_NUCLEO64_F410RB/board.c
View File

@ -14,6 +14,11 @@
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)
@ -59,14 +64,6 @@ const PALConfig pal_default_config = {
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
#endif
#if STM32_HAS_GPIOJ
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
#endif
#if STM32_HAS_GPIOK
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
#endif
};
#endif

299
os/hal/boards/ST_NUCLEO64_F410RB/board.h
View File

@ -14,8 +14,13 @@
limitations under the License.
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#ifndef BOARD_H
#define BOARD_H
/*
* Setup for STMicroelectronics STM32 Nucleo64-F410RB board.
@ -393,22 +398,22 @@
PIN_ODR_HIGH(GPIOA_SWDIO) | \
PIN_ODR_HIGH(GPIOA_SWCLK) | \
PIN_ODR_HIGH(GPIOA_PIN15))
#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ARD_A0, 0) | \
PIN_AFIO_AF(GPIOA_ARD_A1, 0) | \
PIN_AFIO_AF(GPIOA_ARD_D1, 7) | \
PIN_AFIO_AF(GPIOA_ARD_D0, 7) | \
PIN_AFIO_AF(GPIOA_ARD_A2, 0) | \
PIN_AFIO_AF(GPIOA_LED_GREEN, 0) | \
PIN_AFIO_AF(GPIOA_ARD_D12, 0) | \
PIN_AFIO_AF(GPIOA_ARD_D11, 0))
#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_ARD_D7, 0) | \
PIN_AFIO_AF(GPIOA_ARD_D8, 0) | \
PIN_AFIO_AF(GPIOA_ARD_D2, 0) | \
PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \
PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \
PIN_AFIO_AF(GPIOA_SWDIO, 0) | \
PIN_AFIO_AF(GPIOA_SWCLK, 0) | \
PIN_AFIO_AF(GPIOA_PIN15, 0))
#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \
PIN_AFIO_AF(GPIOA_ARD_A1, 0U) | \
PIN_AFIO_AF(GPIOA_ARD_D1, 7U) | \
PIN_AFIO_AF(GPIOA_ARD_D0, 7U) | \
PIN_AFIO_AF(GPIOA_ARD_A2, 0U) | \
PIN_AFIO_AF(GPIOA_LED_GREEN, 0U) | \
PIN_AFIO_AF(GPIOA_ARD_D12, 0U) | \
PIN_AFIO_AF(GPIOA_ARD_D11, 0U))
#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_ARD_D7, 0U) | \
PIN_AFIO_AF(GPIOA_ARD_D8, 0U) | \
PIN_AFIO_AF(GPIOA_ARD_D2, 0U) | \
PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10U) | \
PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10U) | \
PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \
PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \
PIN_AFIO_AF(GPIOA_PIN15, 0U))
/*
* GPIOB setup:
@ -510,22 +515,22 @@
PIN_ODR_HIGH(GPIOB_PIN13) | \
PIN_ODR_HIGH(GPIOB_PIN14) | \
PIN_ODR_HIGH(GPIOB_PIN15))
#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ARD_A3, 0) | \
PIN_AFIO_AF(GPIOB_PIN1, 0) | \
PIN_AFIO_AF(GPIOB_PIN2, 0) | \
PIN_AFIO_AF(GPIOB_SWO, 0) | \
PIN_AFIO_AF(GPIOB_ARD_D5, 0) | \
PIN_AFIO_AF(GPIOB_ARD_D4, 0) | \
PIN_AFIO_AF(GPIOB_ARD_D10, 0) | \
PIN_AFIO_AF(GPIOB_PIN7, 0))
#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_ARD_D15, 0) | \
PIN_AFIO_AF(GPIOB_ARD_D14, 0) | \
PIN_AFIO_AF(GPIOB_ARD_D6, 0) | \
PIN_AFIO_AF(GPIOB_PIN11, 0) | \
PIN_AFIO_AF(GPIOB_PIN12, 0) | \
PIN_AFIO_AF(GPIOB_PIN13, 0) | \
PIN_AFIO_AF(GPIOB_PIN14, 0) | \
PIN_AFIO_AF(GPIOB_PIN15, 0))
#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ARD_A3, 0U) | \
PIN_AFIO_AF(GPIOB_PIN1, 0U) | \
PIN_AFIO_AF(GPIOB_PIN2, 0U) | \
PIN_AFIO_AF(GPIOB_SWO, 0U) | \
PIN_AFIO_AF(GPIOB_ARD_D5, 0U) | \
PIN_AFIO_AF(GPIOB_ARD_D4, 0U) | \
PIN_AFIO_AF(GPIOB_ARD_D10, 0U) | \
PIN_AFIO_AF(GPIOB_PIN7, 0U))
#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_ARD_D15, 0U) | \
PIN_AFIO_AF(GPIOB_ARD_D14, 0U) | \
PIN_AFIO_AF(GPIOB_ARD_D6, 0U) | \
PIN_AFIO_AF(GPIOB_PIN11, 0U) | \
PIN_AFIO_AF(GPIOB_PIN12, 0U) | \
PIN_AFIO_AF(GPIOB_PIN13, 0U) | \
PIN_AFIO_AF(GPIOB_PIN14, 0U) | \
PIN_AFIO_AF(GPIOB_PIN15, 0U))
/*
* GPIOC setup:
@ -627,22 +632,22 @@
PIN_ODR_HIGH(GPIOC_BUTTON) | \
PIN_ODR_HIGH(GPIOC_OSC32_IN) | \
PIN_ODR_HIGH(GPIOC_OSC32_OUT))
#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ARD_A5, 0) | \
PIN_AFIO_AF(GPIOC_ARD_A4, 0) | \
PIN_AFIO_AF(GPIOC_PIN2, 0) | \
PIN_AFIO_AF(GPIOC_PIN3, 0) | \
PIN_AFIO_AF(GPIOC_PIN4, 0) | \
PIN_AFIO_AF(GPIOC_PIN5, 0) | \
PIN_AFIO_AF(GPIOC_PIN6, 0) | \
PIN_AFIO_AF(GPIOC_ARD_D9, 0))
#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0) | \
PIN_AFIO_AF(GPIOC_PIN9, 0) | \
PIN_AFIO_AF(GPIOC_PIN10, 0) | \
PIN_AFIO_AF(GPIOC_PIN11, 0) | \
PIN_AFIO_AF(GPIOC_PIN12, 0) | \
PIN_AFIO_AF(GPIOC_BUTTON, 0) | \
PIN_AFIO_AF(GPIOC_OSC32_IN, 0) | \
PIN_AFIO_AF(GPIOC_OSC32_OUT, 0))
#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ARD_A5, 0U) | \
PIN_AFIO_AF(GPIOC_ARD_A4, 0U) | \
PIN_AFIO_AF(GPIOC_PIN2, 0U) | \
PIN_AFIO_AF(GPIOC_PIN3, 0U) | \
PIN_AFIO_AF(GPIOC_PIN4, 0U) | \
PIN_AFIO_AF(GPIOC_PIN5, 0U) | \
PIN_AFIO_AF(GPIOC_PIN6, 0U) | \
PIN_AFIO_AF(GPIOC_ARD_D9, 0U))
#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \
PIN_AFIO_AF(GPIOC_PIN9, 0U) | \
PIN_AFIO_AF(GPIOC_PIN10, 0U) | \
PIN_AFIO_AF(GPIOC_PIN11, 0U) | \
PIN_AFIO_AF(GPIOC_PIN12, 0U) | \
PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \
PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \
PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U))
/*
* GPIOD setup:
@ -744,22 +749,22 @@
PIN_ODR_HIGH(GPIOD_PIN13) | \
PIN_ODR_HIGH(GPIOD_PIN14) | \
PIN_ODR_HIGH(GPIOD_PIN15))
#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \
PIN_AFIO_AF(GPIOD_PIN1, 0) | \
PIN_AFIO_AF(GPIOD_PIN2, 0) | \
PIN_AFIO_AF(GPIOD_PIN3, 0) | \
PIN_AFIO_AF(GPIOD_PIN4, 0) | \
PIN_AFIO_AF(GPIOD_PIN5, 0) | \
PIN_AFIO_AF(GPIOD_PIN6, 0) | \
PIN_AFIO_AF(GPIOD_PIN7, 0))
#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \
PIN_AFIO_AF(GPIOD_PIN9, 0) | \
PIN_AFIO_AF(GPIOD_PIN10, 0) | \
PIN_AFIO_AF(GPIOD_PIN11, 0) | \
PIN_AFIO_AF(GPIOD_PIN12, 0) | \
PIN_AFIO_AF(GPIOD_PIN13, 0) | \
PIN_AFIO_AF(GPIOD_PIN14, 0) | \
PIN_AFIO_AF(GPIOD_PIN15, 0))
#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \
PIN_AFIO_AF(GPIOD_PIN1, 0U) | \
PIN_AFIO_AF(GPIOD_PIN2, 0U) | \
PIN_AFIO_AF(GPIOD_PIN3, 0U) | \
PIN_AFIO_AF(GPIOD_PIN4, 0U) | \
PIN_AFIO_AF(GPIOD_PIN5, 0U) | \
PIN_AFIO_AF(GPIOD_PIN6, 0U) | \
PIN_AFIO_AF(GPIOD_PIN7, 0U))
#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \
PIN_AFIO_AF(GPIOD_PIN9, 0U) | \
PIN_AFIO_AF(GPIOD_PIN10, 0U) | \
PIN_AFIO_AF(GPIOD_PIN11, 0U) | \
PIN_AFIO_AF(GPIOD_PIN12, 0U) | \
PIN_AFIO_AF(GPIOD_PIN13, 0U) | \
PIN_AFIO_AF(GPIOD_PIN14, 0U) | \
PIN_AFIO_AF(GPIOD_PIN15, 0U))
/*
* GPIOE setup:
@ -861,22 +866,22 @@
PIN_ODR_HIGH(GPIOE_PIN13) | \
PIN_ODR_HIGH(GPIOE_PIN14) | \
PIN_ODR_HIGH(GPIOE_PIN15))
#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0) | \
PIN_AFIO_AF(GPIOE_PIN1, 0) | \
PIN_AFIO_AF(GPIOE_PIN2, 0) | \
PIN_AFIO_AF(GPIOE_PIN3, 0) | \
PIN_AFIO_AF(GPIOE_PIN4, 0) | \
PIN_AFIO_AF(GPIOE_PIN5, 0) | \
PIN_AFIO_AF(GPIOE_PIN6, 0) | \
PIN_AFIO_AF(GPIOE_PIN7, 0))
#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0) | \
PIN_AFIO_AF(GPIOE_PIN9, 0) | \
PIN_AFIO_AF(GPIOE_PIN10, 0) | \
PIN_AFIO_AF(GPIOE_PIN11, 0) | \
PIN_AFIO_AF(GPIOE_PIN12, 0) | \
PIN_AFIO_AF(GPIOE_PIN13, 0) | \
PIN_AFIO_AF(GPIOE_PIN14, 0) | \
PIN_AFIO_AF(GPIOE_PIN15, 0))
#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \
PIN_AFIO_AF(GPIOE_PIN1, 0U) | \
PIN_AFIO_AF(GPIOE_PIN2, 0U) | \
PIN_AFIO_AF(GPIOE_PIN3, 0U) | \
PIN_AFIO_AF(GPIOE_PIN4, 0U) | \
PIN_AFIO_AF(GPIOE_PIN5, 0U) | \
PIN_AFIO_AF(GPIOE_PIN6, 0U) | \
PIN_AFIO_AF(GPIOE_PIN7, 0U))
#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \
PIN_AFIO_AF(GPIOE_PIN9, 0U) | \
PIN_AFIO_AF(GPIOE_PIN10, 0U) | \
PIN_AFIO_AF(GPIOE_PIN11, 0U) | \
PIN_AFIO_AF(GPIOE_PIN12, 0U) | \
PIN_AFIO_AF(GPIOE_PIN13, 0U) | \
PIN_AFIO_AF(GPIOE_PIN14, 0U) | \
PIN_AFIO_AF(GPIOE_PIN15, 0U))
/*
* GPIOF setup:
@ -978,22 +983,22 @@
PIN_ODR_HIGH(GPIOF_PIN13) | \
PIN_ODR_HIGH(GPIOF_PIN14) | \
PIN_ODR_HIGH(GPIOF_PIN15))
#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0) | \
PIN_AFIO_AF(GPIOF_PIN1, 0) | \
PIN_AFIO_AF(GPIOF_PIN2, 0) | \
PIN_AFIO_AF(GPIOF_PIN3, 0) | \
PIN_AFIO_AF(GPIOF_PIN4, 0) | \
PIN_AFIO_AF(GPIOF_PIN5, 0) | \
PIN_AFIO_AF(GPIOF_PIN6, 0) | \
PIN_AFIO_AF(GPIOF_PIN7, 0))
#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \
PIN_AFIO_AF(GPIOF_PIN9, 0) | \
PIN_AFIO_AF(GPIOF_PIN10, 0) | \
PIN_AFIO_AF(GPIOF_PIN11, 0) | \
PIN_AFIO_AF(GPIOF_PIN12, 0) | \
PIN_AFIO_AF(GPIOF_PIN13, 0) | \
PIN_AFIO_AF(GPIOF_PIN14, 0) | \
PIN_AFIO_AF(GPIOF_PIN15, 0))
#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \
PIN_AFIO_AF(GPIOF_PIN1, 0U) | \
PIN_AFIO_AF(GPIOF_PIN2, 0U) | \
PIN_AFIO_AF(GPIOF_PIN3, 0U) | \
PIN_AFIO_AF(GPIOF_PIN4, 0U) | \
PIN_AFIO_AF(GPIOF_PIN5, 0U) | \
PIN_AFIO_AF(GPIOF_PIN6, 0U) | \
PIN_AFIO_AF(GPIOF_PIN7, 0U))
#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \
PIN_AFIO_AF(GPIOF_PIN9, 0U) | \
PIN_AFIO_AF(GPIOF_PIN10, 0U) | \
PIN_AFIO_AF(GPIOF_PIN11, 0U) | \
PIN_AFIO_AF(GPIOF_PIN12, 0U) | \
PIN_AFIO_AF(GPIOF_PIN13, 0U) | \
PIN_AFIO_AF(GPIOF_PIN14, 0U) | \
PIN_AFIO_AF(GPIOF_PIN15, 0U))
/*
* GPIOG setup:
@ -1095,22 +1100,22 @@
PIN_ODR_HIGH(GPIOG_PIN13) | \
PIN_ODR_HIGH(GPIOG_PIN14) | \
PIN_ODR_HIGH(GPIOG_PIN15))
#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0) | \
PIN_AFIO_AF(GPIOG_PIN1, 0) | \
PIN_AFIO_AF(GPIOG_PIN2, 0) | \
PIN_AFIO_AF(GPIOG_PIN3, 0) | \
PIN_AFIO_AF(GPIOG_PIN4, 0) | \
PIN_AFIO_AF(GPIOG_PIN5, 0) | \
PIN_AFIO_AF(GPIOG_PIN6, 0) | \
PIN_AFIO_AF(GPIOG_PIN7, 0))
#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0) | \
PIN_AFIO_AF(GPIOG_PIN9, 0) | \
PIN_AFIO_AF(GPIOG_PIN10, 0) | \
PIN_AFIO_AF(GPIOG_PIN11, 0) | \
PIN_AFIO_AF(GPIOG_PIN12, 0) | \
PIN_AFIO_AF(GPIOG_PIN13, 0) | \
PIN_AFIO_AF(GPIOG_PIN14, 0) | \
PIN_AFIO_AF(GPIOG_PIN15, 0))
#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \
PIN_AFIO_AF(GPIOG_PIN1, 0U) | \
PIN_AFIO_AF(GPIOG_PIN2, 0U) | \
PIN_AFIO_AF(GPIOG_PIN3, 0U) | \
PIN_AFIO_AF(GPIOG_PIN4, 0U) | \
PIN_AFIO_AF(GPIOG_PIN5, 0U) | \
PIN_AFIO_AF(GPIOG_PIN6, 0U) | \
PIN_AFIO_AF(GPIOG_PIN7, 0U))
#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \
PIN_AFIO_AF(GPIOG_PIN9, 0U) | \
PIN_AFIO_AF(GPIOG_PIN10, 0U) | \
PIN_AFIO_AF(GPIOG_PIN11, 0U) | \
PIN_AFIO_AF(GPIOG_PIN12, 0U) | \
PIN_AFIO_AF(GPIOG_PIN13, 0U) | \
PIN_AFIO_AF(GPIOG_PIN14, 0U) | \
PIN_AFIO_AF(GPIOG_PIN15, 0U))
/*
* GPIOH setup:
@ -1212,22 +1217,22 @@
PIN_ODR_HIGH(GPIOH_PIN13) | \
PIN_ODR_HIGH(GPIOH_PIN14) | \
PIN_ODR_HIGH(GPIOH_PIN15))
#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0) | \
PIN_AFIO_AF(GPIOH_OSC_OUT, 0) | \
PIN_AFIO_AF(GPIOH_PIN2, 0) | \
PIN_AFIO_AF(GPIOH_PIN3, 0) | \
PIN_AFIO_AF(GPIOH_PIN4, 0) | \
PIN_AFIO_AF(GPIOH_PIN5, 0) | \
PIN_AFIO_AF(GPIOH_PIN6, 0) | \
PIN_AFIO_AF(GPIOH_PIN7, 0))
#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \
PIN_AFIO_AF(GPIOH_PIN9, 0) | \
PIN_AFIO_AF(GPIOH_PIN10, 0) | \
PIN_AFIO_AF(GPIOH_PIN11, 0) | \
PIN_AFIO_AF(GPIOH_PIN12, 0) | \
PIN_AFIO_AF(GPIOH_PIN13, 0) | \
PIN_AFIO_AF(GPIOH_PIN14, 0) | \
PIN_AFIO_AF(GPIOH_PIN15, 0))
#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \
PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \
PIN_AFIO_AF(GPIOH_PIN2, 0U) | \
PIN_AFIO_AF(GPIOH_PIN3, 0U) | \
PIN_AFIO_AF(GPIOH_PIN4, 0U) | \
PIN_AFIO_AF(GPIOH_PIN5, 0U) | \
PIN_AFIO_AF(GPIOH_PIN6, 0U) | \
PIN_AFIO_AF(GPIOH_PIN7, 0U))
#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \
PIN_AFIO_AF(GPIOH_PIN9, 0U) | \
PIN_AFIO_AF(GPIOH_PIN10, 0U) | \
PIN_AFIO_AF(GPIOH_PIN11, 0U) | \
PIN_AFIO_AF(GPIOH_PIN12, 0U) | \
PIN_AFIO_AF(GPIOH_PIN13, 0U) | \
PIN_AFIO_AF(GPIOH_PIN14, 0U) | \
PIN_AFIO_AF(GPIOH_PIN15, 0U))
/*
* GPIOI setup:
@ -1329,22 +1334,22 @@
PIN_ODR_HIGH(GPIOI_PIN13) | \
PIN_ODR_HIGH(GPIOI_PIN14) | \
PIN_ODR_HIGH(GPIOI_PIN15))
#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0) | \
PIN_AFIO_AF(GPIOI_PIN1, 0) | \
PIN_AFIO_AF(GPIOI_PIN2, 0) | \
PIN_AFIO_AF(GPIOI_PIN3, 0) | \
PIN_AFIO_AF(GPIOI_PIN4, 0) | \
PIN_AFIO_AF(GPIOI_PIN5, 0) | \
PIN_AFIO_AF(GPIOI_PIN6, 0) | \
PIN_AFIO_AF(GPIOI_PIN7, 0))
#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \
PIN_AFIO_AF(GPIOI_PIN9, 0) | \
PIN_AFIO_AF(GPIOI_PIN10, 0) | \
PIN_AFIO_AF(GPIOI_PIN11, 0) | \
PIN_AFIO_AF(GPIOI_PIN12, 0) | \
PIN_AFIO_AF(GPIOI_PIN13, 0) | \
PIN_AFIO_AF(GPIOI_PIN14, 0) | \
PIN_AFIO_AF(GPIOI_PIN15, 0))
#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \
PIN_AFIO_AF(GPIOI_PIN1, 0U) | \
PIN_AFIO_AF(GPIOI_PIN2, 0U) | \
PIN_AFIO_AF(GPIOI_PIN3, 0U) | \
PIN_AFIO_AF(GPIOI_PIN4, 0U) | \
PIN_AFIO_AF(GPIOI_PIN5, 0U) | \
PIN_AFIO_AF(GPIOI_PIN6, 0U) | \
PIN_AFIO_AF(GPIOI_PIN7, 0U))
#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \
PIN_AFIO_AF(GPIOI_PIN9, 0U) | \
PIN_AFIO_AF(GPIOI_PIN10, 0U) | \
PIN_AFIO_AF(GPIOI_PIN11, 0U) | \
PIN_AFIO_AF(GPIOI_PIN12, 0U) | \
PIN_AFIO_AF(GPIOI_PIN13, 0U) | \
PIN_AFIO_AF(GPIOI_PIN14, 0U) | \
PIN_AFIO_AF(GPIOI_PIN15, 0U))
#if !defined(_FROM_ASM_)
@ -1357,4 +1362,4 @@ extern "C" {
#endif
#endif /* _FROM_ASM_ */
#endif /* _BOARD_H_ */
#endif /* BOARD_H */

4
os/hal/boards/ST_NUCLEO64_F410RB/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F410RB/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F410RB
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_NUCLEO64_F411RE/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F411RE/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F411RE
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_NUCLEO64_F446RE/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F446RE/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_F446RE
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_NUCLEO64_L053R8/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_L053R8/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_L053R8
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_NUCLEO64_L073RZ/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_L073RZ/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_L073RZ
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_NUCLEO64_L152RE/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_L152RE/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_L152RE
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_NUCLEO64_L476RG/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_L476RG/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO64_L476RG
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_STM32373C_EVAL/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32373C_EVAL/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32373C_EVAL
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_STM32F072B_DISCOVERY/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F072B_DISCOVERY/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F072B_DISCOVERY
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_STM32F0_DISCOVERY/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F0_DISCOVERY/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F0_DISCOVERY
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_STM32F2_DISCOVERY/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F2_DISCOVERY/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F2_DISCOVERY
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_STM32F334_DISCOVERY/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F334_DISCOVERY/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F334_DISCOVERY
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_STM32F3_DISCOVERY/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F3_DISCOVERY/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F3_DISCOVERY
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_STM32F3_DISCOVERY_REVC/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F3_DISCOVERY_REVC/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F3_DISCOVERY_REVC
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_STM32F401C_DISCOVERY/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F401C_DISCOVERY/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F401C_DISCOVERY
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_STM32F429I_DISCOVERY/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F429I_DISCOVERY/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F429I_DISCOVERY
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

15
os/hal/boards/ST_STM32F469I_DISCOVERY/board.c
View File

@ -14,6 +14,11 @@
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)
@ -57,15 +62,7 @@ const PALConfig pal_default_config = {
#endif
#if STM32_HAS_GPIOI
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
#endif
#if STM32_HAS_GPIOJ
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
#endif
#if STM32_HAS_GPIOK
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
#endif
};
#endif

363
os/hal/boards/ST_STM32F469I_DISCOVERY/board.h
View File

@ -14,8 +14,13 @@
limitations under the License.
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#ifndef BOARD_H
#define BOARD_H
/*
* Setup for STMicroelectronics STM32F469I-Discovery board.
@ -524,22 +529,22 @@
PIN_ODR_HIGH(GPIOA_SWDIO) | \
PIN_ODR_HIGH(GPIOA_SWCLK) | \
PIN_ODR_HIGH(GPIOA_EXT_11))
#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0) | \
PIN_AFIO_AF(GPIOA_ARD_D3, 2) | \
PIN_AFIO_AF(GPIOA_ARD_D5, 2) | \
PIN_AFIO_AF(GPIOA_LCD_BL_CTRL, 2) | \
PIN_AFIO_AF(GPIOA_ARD_A5, 0) | \
PIN_AFIO_AF(GPIOA_EXT_7, 5) | \
PIN_AFIO_AF(GPIOA_ARD_D6, 2) | \
PIN_AFIO_AF(GPIOA_ARD_D9, 2))
#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_EXT_3, 0) | \
PIN_AFIO_AF(GPIOA_VBUS_FS1, 0) | \
PIN_AFIO_AF(GPIOA_USB_FS1_ID, 10) | \
PIN_AFIO_AF(GPIOA_USB_FS1_N, 10) | \
PIN_AFIO_AF(GPIOA_USB_FS1_P, 10) | \
PIN_AFIO_AF(GPIOA_SWDIO, 0) | \
PIN_AFIO_AF(GPIOA_SWCLK, 0) | \
PIN_AFIO_AF(GPIOA_EXT_11, 0))
#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON, 0U) | \
PIN_AFIO_AF(GPIOA_ARD_D3, 2U) | \
PIN_AFIO_AF(GPIOA_ARD_D5, 2U) | \
PIN_AFIO_AF(GPIOA_LCD_BL_CTRL, 2U) | \
PIN_AFIO_AF(GPIOA_ARD_A5, 0U) | \
PIN_AFIO_AF(GPIOA_EXT_7, 5U) | \
PIN_AFIO_AF(GPIOA_ARD_D6, 2U) | \
PIN_AFIO_AF(GPIOA_ARD_D9, 2U))
#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_EXT_3, 0U) | \
PIN_AFIO_AF(GPIOA_VBUS_FS1, 0U) | \
PIN_AFIO_AF(GPIOA_USB_FS1_ID, 10U) | \
PIN_AFIO_AF(GPIOA_USB_FS1_N, 10U) | \
PIN_AFIO_AF(GPIOA_USB_FS1_P, 10U) | \
PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \
PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \
PIN_AFIO_AF(GPIOA_EXT_11, 0U))
/*
* GPIOB setup:
@ -641,22 +646,22 @@
PIN_ODR_HIGH(GPIOB_EXT_10) | \
PIN_ODR_HIGH(GPIOB_ARD_D12) | \
PIN_ODR_HIGH(GPIOB_ARD_D11))
#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_EXT_RESET, 0) | \
PIN_AFIO_AF(GPIOB_ARD_A0, 0) | \
PIN_AFIO_AF(GPIOB_OTG_FS1_POWERSWITCHON, 0) |\
PIN_AFIO_AF(GPIOB_I2S3_CK, 6) | \
PIN_AFIO_AF(GPIOB_EXT_5, 5) | \
PIN_AFIO_AF(GPIOB_EXT_9, 5) | \
PIN_AFIO_AF(GPIOB_QSPI_BK1_NCS, 10) | \
PIN_AFIO_AF(GPIOB_QSPI_FS1_OVERCURRENT, 0))
#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4) | \
PIN_AFIO_AF(GPIOB_I2C1_SDA, 4) | \
PIN_AFIO_AF(GPIOB_STLK_RX, 7) | \
PIN_AFIO_AF(GPIOB_STLK_TX, 7) | \
PIN_AFIO_AF(GPIOB_EXT_12, 9) | \
PIN_AFIO_AF(GPIOB_EXT_10, 9) | \
PIN_AFIO_AF(GPIOB_ARD_D12, 5) | \
PIN_AFIO_AF(GPIOB_ARD_D11, 5))
#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_EXT_RESET, 0U) | \
PIN_AFIO_AF(GPIOB_ARD_A0, 0U) | \
PIN_AFIO_AF(GPIOB_OTG_FS1_POWERSWITCHON, 0U) |\
PIN_AFIO_AF(GPIOB_I2S3_CK, 6U) | \
PIN_AFIO_AF(GPIOB_EXT_5, 5U) | \
PIN_AFIO_AF(GPIOB_EXT_9, 5U) | \
PIN_AFIO_AF(GPIOB_QSPI_BK1_NCS, 10U) | \
PIN_AFIO_AF(GPIOB_QSPI_FS1_OVERCURRENT, 0U))
#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4U) | \
PIN_AFIO_AF(GPIOB_I2C1_SDA, 4U) | \
PIN_AFIO_AF(GPIOB_STLK_RX, 7U) | \
PIN_AFIO_AF(GPIOB_STLK_TX, 7U) | \
PIN_AFIO_AF(GPIOB_EXT_12, 9U) | \
PIN_AFIO_AF(GPIOB_EXT_10, 9U) | \
PIN_AFIO_AF(GPIOB_ARD_D12, 5U) | \
PIN_AFIO_AF(GPIOB_ARD_D11, 5U))
/*
* GPIOC setup:
@ -758,22 +763,22 @@
PIN_ODR_HIGH(GPIOC_EXT_13) | \
PIN_ODR_HIGH(GPIOC_OSC32_IN) | \
PIN_ODR_HIGH(GPIOC_OSC32_OUT))
#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_SDNWE, 12) | \
PIN_AFIO_AF(GPIOC_EXT_14, 0) | \
PIN_AFIO_AF(GPIOC_ARD_A1, 0) | \
PIN_AFIO_AF(GPIOC_ARD_A2, 0) | \
PIN_AFIO_AF(GPIOC_ARD_A3, 0) | \
PIN_AFIO_AF(GPIOC_ARD_A4, 0) | \
PIN_AFIO_AF(GPIOC_EXT_6, 8) | \
PIN_AFIO_AF(GPIOC_EXT_8, 8))
#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_USD_D0, 12) | \
PIN_AFIO_AF(GPIOC_USD_D1, 12) | \
PIN_AFIO_AF(GPIOC_USD_D2, 12) | \
PIN_AFIO_AF(GPIOC_USD_D3, 12) | \
PIN_AFIO_AF(GPIOC_USD_CLK, 12) | \
PIN_AFIO_AF(GPIOC_EXT_13, 0) | \
PIN_AFIO_AF(GPIOC_OSC32_IN, 0) | \
PIN_AFIO_AF(GPIOC_OSC32_OUT, 0))
#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_SDNWE, 12U) | \
PIN_AFIO_AF(GPIOC_EXT_14, 0U) | \
PIN_AFIO_AF(GPIOC_ARD_A1, 0U) | \
PIN_AFIO_AF(GPIOC_ARD_A2, 0U) | \
PIN_AFIO_AF(GPIOC_ARD_A3, 0U) | \
PIN_AFIO_AF(GPIOC_ARD_A4, 0U) | \
PIN_AFIO_AF(GPIOC_EXT_6, 8U) | \
PIN_AFIO_AF(GPIOC_EXT_8, 8U))
#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_USD_D0, 12U) | \
PIN_AFIO_AF(GPIOC_USD_D1, 12U) | \
PIN_AFIO_AF(GPIOC_USD_D2, 12U) | \
PIN_AFIO_AF(GPIOC_USD_D3, 12U) | \
PIN_AFIO_AF(GPIOC_USD_CLK, 12U) | \
PIN_AFIO_AF(GPIOC_EXT_13, 0U) | \
PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \
PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U))
/*
* GPIOD setup:
@ -875,22 +880,22 @@
PIN_ODR_HIGH(GPIOD_MIC_CK) | \
PIN_ODR_HIGH(GPIOD_PIN14) | \
PIN_ODR_HIGH(GPIOD_PIN15))
#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \
PIN_AFIO_AF(GPIOD_PIN1, 0) | \
PIN_AFIO_AF(GPIOD_USD_CMD, 12) | \
PIN_AFIO_AF(GPIOD_ARD_D13, 5) | \
PIN_AFIO_AF(GPIOD_LED2, 0) | \
PIN_AFIO_AF(GPIOD_LED3, 0) | \
PIN_AFIO_AF(GPIOD_MIC_DATA, 6) | \
PIN_AFIO_AF(GPIOD_PIN7, 0))
#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \
PIN_AFIO_AF(GPIOD_PIN9, 0) | \
PIN_AFIO_AF(GPIOD_PIN10, 0) | \
PIN_AFIO_AF(GPIOD_PIN11, 0) | \
PIN_AFIO_AF(GPIOD_PIN12, 0) | \
PIN_AFIO_AF(GPIOD_MIC_CK, 2) | \
PIN_AFIO_AF(GPIOD_PIN14, 0) | \
PIN_AFIO_AF(GPIOD_PIN15, 0))
#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \
PIN_AFIO_AF(GPIOD_PIN1, 0U) | \
PIN_AFIO_AF(GPIOD_USD_CMD, 12U) | \
PIN_AFIO_AF(GPIOD_ARD_D13, 5U) | \
PIN_AFIO_AF(GPIOD_LED2, 0U) | \
PIN_AFIO_AF(GPIOD_LED3, 0U) | \
PIN_AFIO_AF(GPIOD_MIC_DATA, 6U) | \
PIN_AFIO_AF(GPIOD_PIN7, 0U))
#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \
PIN_AFIO_AF(GPIOD_PIN9, 0U) | \
PIN_AFIO_AF(GPIOD_PIN10, 0U) | \
PIN_AFIO_AF(GPIOD_PIN11, 0U) | \
PIN_AFIO_AF(GPIOD_PIN12, 0U) | \
PIN_AFIO_AF(GPIOD_MIC_CK, 2U) | \
PIN_AFIO_AF(GPIOD_PIN14, 0U) | \
PIN_AFIO_AF(GPIOD_PIN15, 0U))
/*
* GPIOE setup:
@ -992,22 +997,22 @@
PIN_ODR_HIGH(GPIOE_PIN13) | \
PIN_ODR_HIGH(GPIOE_PIN14) | \
PIN_ODR_HIGH(GPIOE_PIN15))
#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_FMC_NBL0, 12) | \
PIN_AFIO_AF(GPIOE_FMC_NBL1, 12) | \
PIN_AFIO_AF(GPIOE_AUDIO_RST, 6) | \
PIN_AFIO_AF(GPIOE_SPKR_HP, 6) | \
PIN_AFIO_AF(GPIOE_SAI1_FSA, 6) | \
PIN_AFIO_AF(GPIOE_SAI1_SCKA, 6) | \
PIN_AFIO_AF(GPIOE_SAI1_SDA, 6) | \
PIN_AFIO_AF(GPIOE_PIN7, 0))
#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0) | \
PIN_AFIO_AF(GPIOE_PIN9, 0) | \
PIN_AFIO_AF(GPIOE_PIN10, 0) | \
PIN_AFIO_AF(GPIOE_PIN11, 0) | \
PIN_AFIO_AF(GPIOE_PIN12, 0) | \
PIN_AFIO_AF(GPIOE_PIN13, 0) | \
PIN_AFIO_AF(GPIOE_PIN14, 0) | \
PIN_AFIO_AF(GPIOE_PIN15, 0))
#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_FMC_NBL0, 12U) | \
PIN_AFIO_AF(GPIOE_FMC_NBL1, 12U) | \
PIN_AFIO_AF(GPIOE_AUDIO_RST, 6U) | \
PIN_AFIO_AF(GPIOE_SPKR_HP, 6U) | \
PIN_AFIO_AF(GPIOE_SAI1_FSA, 6U) | \
PIN_AFIO_AF(GPIOE_SAI1_SCKA, 6U) | \
PIN_AFIO_AF(GPIOE_SAI1_SDA, 6U) | \
PIN_AFIO_AF(GPIOE_PIN7, 0U))
#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \
PIN_AFIO_AF(GPIOE_PIN9, 0U) | \
PIN_AFIO_AF(GPIOE_PIN10, 0U) | \
PIN_AFIO_AF(GPIOE_PIN11, 0U) | \
PIN_AFIO_AF(GPIOE_PIN12, 0U) | \
PIN_AFIO_AF(GPIOE_PIN13, 0U) | \
PIN_AFIO_AF(GPIOE_PIN14, 0U) | \
PIN_AFIO_AF(GPIOE_PIN15, 0U))
/*
* GPIOF setup:
@ -1109,22 +1114,22 @@
PIN_ODR_HIGH(GPIOF_PIN13) | \
PIN_ODR_HIGH(GPIOF_PIN14) | \
PIN_ODR_HIGH(GPIOF_PIN15))
#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0) | \
PIN_AFIO_AF(GPIOF_PIN1, 0) | \
PIN_AFIO_AF(GPIOF_PIN2, 0) | \
PIN_AFIO_AF(GPIOF_PIN3, 0) | \
PIN_AFIO_AF(GPIOF_PIN4, 0) | \
PIN_AFIO_AF(GPIOF_PIN5, 0) | \
PIN_AFIO_AF(GPIOF_QSPI_BK1_IO3, 9) | \
PIN_AFIO_AF(GPIOF_QSPI_BK1_IO2, 9))
#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_QSPI_BK1_IO0, 9) | \
PIN_AFIO_AF(GPIOF_QSPI_BK1_IO1, 9) | \
PIN_AFIO_AF(GPIOF_QSPI_CLK, 9) | \
PIN_AFIO_AF(GPIOF_SDNRAS, 12) | \
PIN_AFIO_AF(GPIOF_PIN12, 0) | \
PIN_AFIO_AF(GPIOF_PIN13, 0) | \
PIN_AFIO_AF(GPIOF_PIN14, 0) | \
PIN_AFIO_AF(GPIOF_PIN15, 0))
#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \
PIN_AFIO_AF(GPIOF_PIN1, 0U) | \
PIN_AFIO_AF(GPIOF_PIN2, 0U) | \
PIN_AFIO_AF(GPIOF_PIN3, 0U) | \
PIN_AFIO_AF(GPIOF_PIN4, 0U) | \
PIN_AFIO_AF(GPIOF_PIN5, 0U) | \
PIN_AFIO_AF(GPIOF_QSPI_BK1_IO3, 9U) | \
PIN_AFIO_AF(GPIOF_QSPI_BK1_IO2, 9U))
#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_QSPI_BK1_IO0, 9U) | \
PIN_AFIO_AF(GPIOF_QSPI_BK1_IO1, 9U) | \
PIN_AFIO_AF(GPIOF_QSPI_CLK, 9U) | \
PIN_AFIO_AF(GPIOF_SDNRAS, 12U) | \
PIN_AFIO_AF(GPIOF_PIN12, 0U) | \
PIN_AFIO_AF(GPIOF_PIN13, 0U) | \
PIN_AFIO_AF(GPIOF_PIN14, 0U) | \
PIN_AFIO_AF(GPIOF_PIN15, 0U))
/*
* GPIOG setup:
@ -1226,22 +1231,22 @@
PIN_ODR_HIGH(GPIOG_ARD_D2) | \
PIN_ODR_HIGH(GPIOG_ARD_D1) | \
PIN_ODR_HIGH(GPIOG_SDNCAS))
#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0) | \
PIN_AFIO_AF(GPIOG_PIN1, 0) | \
PIN_AFIO_AF(GPIOG_USD_DETECT, 0) | \
PIN_AFIO_AF(GPIOG_PIN3, 0) | \
PIN_AFIO_AF(GPIOG_PIN4, 0) | \
PIN_AFIO_AF(GPIOG_PIN5, 0) | \
PIN_AFIO_AF(GPIOG_LED1, 0) | \
PIN_AFIO_AF(GPIOG_SAI1_MCLKA, 6))
#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_SDCLK, 12) | \
PIN_AFIO_AF(GPIOG_ARD_D0, 0) | \
PIN_AFIO_AF(GPIOG_ARD_D8, 0) | \
PIN_AFIO_AF(GPIOG_ARD_D7, 0) | \
PIN_AFIO_AF(GPIOG_ARD_D4, 0) | \
PIN_AFIO_AF(GPIOG_ARD_D2, 0) | \
PIN_AFIO_AF(GPIOG_ARD_D1, 0) | \
PIN_AFIO_AF(GPIOG_SDNCAS, 12))
#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \
PIN_AFIO_AF(GPIOG_PIN1, 0U) | \
PIN_AFIO_AF(GPIOG_USD_DETECT, 0U) | \
PIN_AFIO_AF(GPIOG_PIN3, 0U) | \
PIN_AFIO_AF(GPIOG_PIN4, 0U) | \
PIN_AFIO_AF(GPIOG_PIN5, 0U) | \
PIN_AFIO_AF(GPIOG_LED1, 0U) | \
PIN_AFIO_AF(GPIOG_SAI1_MCLKA, 6U))
#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_SDCLK, 12U) | \
PIN_AFIO_AF(GPIOG_ARD_D0, 0U) | \
PIN_AFIO_AF(GPIOG_ARD_D8, 0U) | \
PIN_AFIO_AF(GPIOG_ARD_D7, 0U) | \
PIN_AFIO_AF(GPIOG_ARD_D4, 0U) | \
PIN_AFIO_AF(GPIOG_ARD_D2, 0U) | \
PIN_AFIO_AF(GPIOG_ARD_D1, 0U) | \
PIN_AFIO_AF(GPIOG_SDNCAS, 12U))
/*
* GPIOH setup:
@ -1343,22 +1348,22 @@
PIN_ODR_HIGH(GPIOH_PIN13) | \
PIN_ODR_HIGH(GPIOH_PIN14) | \
PIN_ODR_HIGH(GPIOH_PIN15))
#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0) | \
PIN_AFIO_AF(GPIOH_OSC_OUT, 0) | \
PIN_AFIO_AF(GPIOH_SDCKE0, 12) | \
PIN_AFIO_AF(GPIOH_SDNE0, 12) | \
PIN_AFIO_AF(GPIOH_I2C2_SCL, 4) | \
PIN_AFIO_AF(GPIOH_I2C2_SDA, 4) | \
PIN_AFIO_AF(GPIOH_ARD_D10, 0) | \
PIN_AFIO_AF(GPIOH_LCD_RESET, 0))
#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \
PIN_AFIO_AF(GPIOH_PIN9, 0) | \
PIN_AFIO_AF(GPIOH_PIN10, 0) | \
PIN_AFIO_AF(GPIOH_PIN11, 0) | \
PIN_AFIO_AF(GPIOH_PIN12, 0) | \
PIN_AFIO_AF(GPIOH_PIN13, 0) | \
PIN_AFIO_AF(GPIOH_PIN14, 0) | \
PIN_AFIO_AF(GPIOH_PIN15, 0))
#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \
PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \
PIN_AFIO_AF(GPIOH_SDCKE0, 12U) | \
PIN_AFIO_AF(GPIOH_SDNE0, 12U) | \
PIN_AFIO_AF(GPIOH_I2C2_SCL, 4U) | \
PIN_AFIO_AF(GPIOH_I2C2_SDA, 4U) | \
PIN_AFIO_AF(GPIOH_ARD_D10, 0U) | \
PIN_AFIO_AF(GPIOH_LCD_RESET, 0U))
#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \
PIN_AFIO_AF(GPIOH_PIN9, 0U) | \
PIN_AFIO_AF(GPIOH_PIN10, 0U) | \
PIN_AFIO_AF(GPIOH_PIN11, 0U) | \
PIN_AFIO_AF(GPIOH_PIN12, 0U) | \
PIN_AFIO_AF(GPIOH_PIN13, 0U) | \
PIN_AFIO_AF(GPIOH_PIN14, 0U) | \
PIN_AFIO_AF(GPIOH_PIN15, 0U))
/*
* GPIOI setup:
@ -1460,22 +1465,22 @@
PIN_ODR_HIGH(GPIOI_PIN13) | \
PIN_ODR_HIGH(GPIOI_PIN14) | \
PIN_ODR_HIGH(GPIOI_PIN15))
#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0) | \
PIN_AFIO_AF(GPIOI_PIN1, 0) | \
PIN_AFIO_AF(GPIOI_PIN2, 0) | \
PIN_AFIO_AF(GPIOI_PIN3, 0) | \
PIN_AFIO_AF(GPIOI_FMC_NBL2, 12) | \
PIN_AFIO_AF(GPIOI_FMC_NBL3, 12) | \
PIN_AFIO_AF(GPIOI_PIN6, 0) | \
PIN_AFIO_AF(GPIOI_PIN7, 0))
#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \
PIN_AFIO_AF(GPIOI_PIN9, 0) | \
PIN_AFIO_AF(GPIOI_PIN10, 0) | \
PIN_AFIO_AF(GPIOI_PIN11, 0) | \
PIN_AFIO_AF(GPIOI_PIN12, 0) | \
PIN_AFIO_AF(GPIOI_PIN13, 0) | \
PIN_AFIO_AF(GPIOI_PIN14, 0) | \
PIN_AFIO_AF(GPIOI_PIN15, 0))
#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \
PIN_AFIO_AF(GPIOI_PIN1, 0U) | \
PIN_AFIO_AF(GPIOI_PIN2, 0U) | \
PIN_AFIO_AF(GPIOI_PIN3, 0U) | \
PIN_AFIO_AF(GPIOI_FMC_NBL2, 12U) | \
PIN_AFIO_AF(GPIOI_FMC_NBL3, 12U) | \
PIN_AFIO_AF(GPIOI_PIN6, 0U) | \
PIN_AFIO_AF(GPIOI_PIN7, 0U))
#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \
PIN_AFIO_AF(GPIOI_PIN9, 0U) | \
PIN_AFIO_AF(GPIOI_PIN10, 0U) | \
PIN_AFIO_AF(GPIOI_PIN11, 0U) | \
PIN_AFIO_AF(GPIOI_PIN12, 0U) | \
PIN_AFIO_AF(GPIOI_PIN13, 0U) | \
PIN_AFIO_AF(GPIOI_PIN14, 0U) | \
PIN_AFIO_AF(GPIOI_PIN15, 0U))
/*
* GPIOJ setup:
@ -1577,22 +1582,22 @@
PIN_ODR_HIGH(GPIOJ_PIN13) | \
PIN_ODR_HIGH(GPIOJ_PIN14) | \
PIN_ODR_HIGH(GPIOJ_PIN15))
#define VAL_GPIOJ_AFRL (PIN_AFIO_AF(GPIOJ_PIN0, 0) | \
PIN_AFIO_AF(GPIOJ_PIN1, 0) | \
PIN_AFIO_AF(GPIOJ_DSI_TE, 13) | \
PIN_AFIO_AF(GPIOJ_PIN3, 0) | \
PIN_AFIO_AF(GPIOJ_PIN4, 0) | \
PIN_AFIO_AF(GPIOJ_LCD_INT, 0) | \
PIN_AFIO_AF(GPIOJ_PIN6, 0) | \
PIN_AFIO_AF(GPIOJ_PIN7, 0))
#define VAL_GPIOJ_AFRH (PIN_AFIO_AF(GPIOJ_PIN8, 0) | \
PIN_AFIO_AF(GPIOJ_PIN9, 0) | \
PIN_AFIO_AF(GPIOJ_PIN10, 0) | \
PIN_AFIO_AF(GPIOJ_PIN11, 0) | \
PIN_AFIO_AF(GPIOJ_PIN12, 0) | \
PIN_AFIO_AF(GPIOJ_PIN13, 0) | \
PIN_AFIO_AF(GPIOJ_PIN14, 0) | \
PIN_AFIO_AF(GPIOJ_PIN15, 0))
#define VAL_GPIOJ_AFRL (PIN_AFIO_AF(GPIOJ_PIN0, 0U) | \
PIN_AFIO_AF(GPIOJ_PIN1, 0U) | \
PIN_AFIO_AF(GPIOJ_DSI_TE, 13U) | \
PIN_AFIO_AF(GPIOJ_PIN3, 0U) | \
PIN_AFIO_AF(GPIOJ_PIN4, 0U) | \
PIN_AFIO_AF(GPIOJ_LCD_INT, 0U) | \
PIN_AFIO_AF(GPIOJ_PIN6, 0U) | \
PIN_AFIO_AF(GPIOJ_PIN7, 0U))
#define VAL_GPIOJ_AFRH (PIN_AFIO_AF(GPIOJ_PIN8, 0U) | \
PIN_AFIO_AF(GPIOJ_PIN9, 0U) | \
PIN_AFIO_AF(GPIOJ_PIN10, 0U) | \
PIN_AFIO_AF(GPIOJ_PIN11, 0U) | \
PIN_AFIO_AF(GPIOJ_PIN12, 0U) | \
PIN_AFIO_AF(GPIOJ_PIN13, 0U) | \
PIN_AFIO_AF(GPIOJ_PIN14, 0U) | \
PIN_AFIO_AF(GPIOJ_PIN15, 0U))
/*
* GPIOK setup:
@ -1694,22 +1699,22 @@
PIN_ODR_HIGH(GPIOK_PIN13) | \
PIN_ODR_HIGH(GPIOK_PIN14) | \
PIN_ODR_HIGH(GPIOK_PIN15))
#define VAL_GPIOK_AFRL (PIN_AFIO_AF(GPIOK_PIN0, 0) | \
PIN_AFIO_AF(GPIOK_PIN1, 0) | \
PIN_AFIO_AF(GPIOK_PIN2, 0) | \
PIN_AFIO_AF(GPIOK_LED4, 0) | \
PIN_AFIO_AF(GPIOK_PIN4, 0) | \
PIN_AFIO_AF(GPIOK_PIN5, 0) | \
PIN_AFIO_AF(GPIOK_PIN6, 0) | \
PIN_AFIO_AF(GPIOK_PIN7, 0))
#define VAL_GPIOK_AFRH (PIN_AFIO_AF(GPIOK_PIN8, 0) | \
PIN_AFIO_AF(GPIOK_PIN9, 0) | \
PIN_AFIO_AF(GPIOK_PIN10, 0) | \
PIN_AFIO_AF(GPIOK_PIN11, 0) | \
PIN_AFIO_AF(GPIOK_PIN12, 0) | \
PIN_AFIO_AF(GPIOK_PIN13, 0) | \
PIN_AFIO_AF(GPIOK_PIN14, 0) | \
PIN_AFIO_AF(GPIOK_PIN15, 0))
#define VAL_GPIOK_AFRL (PIN_AFIO_AF(GPIOK_PIN0, 0U) | \
PIN_AFIO_AF(GPIOK_PIN1, 0U) | \
PIN_AFIO_AF(GPIOK_PIN2, 0U) | \
PIN_AFIO_AF(GPIOK_LED4, 0U) | \
PIN_AFIO_AF(GPIOK_PIN4, 0U) | \
PIN_AFIO_AF(GPIOK_PIN5, 0U) | \
PIN_AFIO_AF(GPIOK_PIN6, 0U) | \
PIN_AFIO_AF(GPIOK_PIN7, 0U))
#define VAL_GPIOK_AFRH (PIN_AFIO_AF(GPIOK_PIN8, 0U) | \
PIN_AFIO_AF(GPIOK_PIN9, 0U) | \
PIN_AFIO_AF(GPIOK_PIN10, 0U) | \
PIN_AFIO_AF(GPIOK_PIN11, 0U) | \
PIN_AFIO_AF(GPIOK_PIN12, 0U) | \
PIN_AFIO_AF(GPIOK_PIN13, 0U) | \
PIN_AFIO_AF(GPIOK_PIN14, 0U) | \
PIN_AFIO_AF(GPIOK_PIN15, 0U))
#if !defined(_FROM_ASM_)
@ -1722,4 +1727,4 @@ extern "C" {
#endif
#endif /* _FROM_ASM_ */
#endif /* _BOARD_H_ */
#endif /* BOARD_H */

4
os/hal/boards/ST_STM32F469I_DISCOVERY/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F469I_DISCOVERY/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F469I_DISCOVERY
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_STM32F4_DISCOVERY/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_STM32F746G_DISCOVERY/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F746G_DISCOVERY/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F746G_DISCOVERY
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_STM32F769I_DISCOVERY/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F769I_DISCOVERY/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F769I_DISCOVERY
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_STM32L053_DISCOVERY/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32L053_DISCOVERY/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32L053_DISCOVERY
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_STM32L476_DISCOVERY/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32L476_DISCOVERY/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32L476_DISCOVERY
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/boards/ST_STM32L_DISCOVERY/board.mk
View File

@ -3,3 +3,7 @@ BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32L_DISCOVERY/board.c
# Required include directories
BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32L_DISCOVERY
# Shared variables
ALLCSRC += $(BOARDSRC)
ALLINC += $(BOARDINC)

4
os/hal/hal.mk
View File

@ -111,3 +111,7 @@ endif
# Required include directories
HALINC = $(CHIBIOS)/os/hal/include
# Shared variables
ALLCSRC += $(HALSRC)
ALLINC += $(HALINC)

4
os/hal/lib/complex/mfs/mfs.mk
View File

@ -3,3 +3,7 @@ MFSSRC := $(CHIBIOS)/os/hal/lib/complex/mfs/mfs.c
# Required include directories
MFSINC := $(CHIBIOS)/os/hal/lib/complex/mfs
# Shared variables
ALLCSRC += $(MFSSRC)
ALLINC += $(MFSINC)

4
os/hal/lib/streams/streams.mk
View File

@ -4,3 +4,7 @@ STREAMSSRC = $(CHIBIOS)/os/hal/lib/streams/chprintf.c \
$(CHIBIOS)/os/hal/lib/streams/nullstreams.c
STREAMSINC = $(CHIBIOS)/os/hal/lib/streams
# Shared variables
ALLCSRC += $(STREAMSSRC)
ALLINC += $(STREAMSINC)

4
os/hal/osal/nil/osal.mk
View File

@ -3,3 +3,7 @@ OSALSRC += ${CHIBIOS}/os/hal/osal/nil/osal.c
# Required include directories
OSALINC += ${CHIBIOS}/os/hal/osal/nil
# Shared variables
ALLCSRC += $(OSALSRC)
ALLINC += $(OSALINC)

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