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ChibiOS
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Fixed documentation and indent. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12028 110e8d01-0319-4d1e-a829-52ad28d1bb01
This commit is contained in:
Rocco Marco Guglielmi 2018-05-12 12:54:48 +00:00
parent 2926007c1a
commit 11522ff1c5
1 changed files with 27 additions and 27 deletions
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54
os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h
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@ -148,7 +148,7 @@
#define STM32_HSECLK_MIN 4000000
/**
* @brief Minimum HSE clock frequency.
* @brief Minimum HSE clock frequency using an external source.
*/
#define STM32_HSECLK_BYP_MIN 1000000
@ -158,7 +158,7 @@
#define STM32_LSECLK_MAX 32768
/**
* @brief Maximum LSE clock frequency.
* @brief Maximum LSE clock frequency using an external source.
*/
#define STM32_LSECLK_BYP_MAX 1000000
@ -1673,7 +1673,7 @@
/**
* @brief STM32_PLLI2SM field.
*/
#if ((STM32_PLLI2SM_VALUE >= 2) && (STM32_PLLI2SM_VALUE <= 63)) || \
#if ((STM32_PLLI2SM_VALUE >= 2) && (STM32_PLLI2SM_VALUE <= 63)) || \
defined(__DOXYGEN__)
#define STM32_PLLI2SM (STM32_PLLI2SM_VALUE << 0)
#else
@ -1922,16 +1922,16 @@
* @brief MCO1 divider clock.
*/
#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || defined(__DOXYGEN__)
#define STM32_MCO1DIVCLK STM32_HSICLK
#define STM32_MCO1DIVCLK STM32_HSICLK
#elif STM32_MCO1SEL == STM32_MCO1SEL_LSE
#define STM32_MCO1DIVCLK STM32_LSECLK
#define STM32_MCO1DIVCLK STM32_LSECLK
#elif STM32_MCO1SEL == STM32_MCO1SEL_HSE
#define STM32_MCO1DIVCLK STM32_HSECLK
#define STM32_MCO1DIVCLK STM32_HSECLK
#elif STM32_MCO1SEL == STM32_MCO1SEL_PLL
#define STM32_MCO1DIVCLK STM32_PLLCLKOUT
#define STM32_MCO1DIVCLK STM32_PLLCLKOUT
#else
#error "invalid STM32_MCO1SEL value specified"
@ -1941,19 +1941,19 @@
* @brief MCO1 output pin clock.
*/
#if (STM32_MCO1PRE == STM32_MCO1PRE_DIV1) || defined(__DOXYGEN__)
#define STM32_MCO1CLK STM32_MCO1DIVCLK
#define STM32_MCO1CLK STM32_MCO1DIVCLK
#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV2
#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 2)
#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 2)
#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV3
#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 3)
#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 3)
#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV4
#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 4)
#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 4)
#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV5
#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 5)
#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 5)
#else
#error "invalid STM32_MCO1PRE value specified"
@ -1963,16 +1963,16 @@
* @brief MCO2 divider clock.
*/
#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || defined(__DOXYGEN__)
#define STM32_MCO2DIVCLK STM32_HSECLK
#define STM32_MCO2DIVCLK STM32_HSECLK
#elif STM32_MCO2SEL == STM32_MCO2SEL_PLL
#define STM32_MCO2DIVCLK STM32_PLLCLKOUT
#define STM32_MCO2DIVCLK STM32_PLLCLKOUT
#elif STM32_MCO2SEL == STM32_MCO2SEL_SYSCLK
#define STM32_MCO2DIVCLK STM32_SYSCLK
#define STM32_MCO2DIVCLK STM32_SYSCLK
#elif STM32_MCO2SEL == STM32_MCO2SEL_PLLI2S
#define STM32_MCO2DIVCLK STM32_PLLI2S
#define STM32_MCO2DIVCLK STM32_PLLI2S
#else
#error "invalid STM32_MCO2SEL value specified"
@ -1982,19 +1982,19 @@
* @brief MCO2 output pin clock.
*/
#if (STM32_MCO2PRE == STM32_MCO2PRE_DIV1) || defined(__DOXYGEN__)
#define STM32_MCO2CLK STM32_MCO2DIVCLK
#define STM32_MCO2CLK STM32_MCO2DIVCLK
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV2
#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 2)
#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 2)
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV3
#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 3)
#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 3)
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV4
#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 4)
#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 4)
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV5
#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 5)
#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 5)
#else
#error "invalid STM32_MCO2PRE value specified"
@ -2154,12 +2154,12 @@
/* There are differences in vector names in the various sub-families,
normalizing.*/
#if 0
#define TIM1_BRK_IRQn TIM1_BRK_TIM9_IRQn
#define TIM1_UP_IRQn TIM1_UP_TIM10_IRQn
#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM11_IRQn
#define TIM8_BRK_IRQn TIM8_BRK_TIM12_IRQn
#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn
#define TIM8_TRG_COM_IRQn TIM8_TRG_COM_TIM14_IRQn
#define TIM1_BRK_IRQn TIM1_BRK_TIM9_IRQn
#define TIM1_UP_IRQn TIM1_UP_TIM10_IRQn
#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM11_IRQn
#define TIM8_BRK_IRQn TIM8_BRK_TIM12_IRQn
#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn
#define TIM8_TRG_COM_IRQn TIM8_TRG_COM_TIM14_IRQn
#endif
/*===========================================================================*/