git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6377 35acf78f-673a-0410-8e92-d51de3d6d3f4
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@ -57,7 +57,6 @@
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#define STM32_I2SSRC STM32_I2SSRC_CKIN
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#define STM32_PLLI2SN_VALUE 192
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#define STM32_PLLI2SR_VALUE 5
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#define STM32_VOS STM32_VOS_SCALE1
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#define STM32_PVD_ENABLE FALSE
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#define STM32_PLS STM32_PLS_LEV0
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#define STM32_BKPRAM_ENABLE FALSE
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@ -153,7 +153,7 @@ void stm32_clock_init(void) {
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/* PWR initialization.*/
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#if defined(STM32F4XX) || defined(__DOXYGEN__)
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PWR->CR = STM32_VOS & STM32_VOS_MASK;
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PWR->CR = STM32_VOS;
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while ((PWR->CSR & PWR_CSR_VOSRDY) == 0)
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; /* Waits until power regulator is stable. */
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#else
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@ -191,16 +191,31 @@ void stm32_clock_init(void) {
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RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN |
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STM32_PLLM;
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR & RCC_CR_PLLRDY))
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; /* Waits until PLL is stable. */
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#if STM32_OVERDRIVE_REQUIRED
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/* Overdrive activation performed after activating the PLL in order to save
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time as recommended in RM in "Entering Over-drive mode" paragraph.*/
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PWR->CR |= PWR_CR_ODEN;
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while (!(PWR->CSR & PWR_CSR_ODRDY)
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;
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PWR->CR |= PWR_CR_ODSWEN;
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while (!(PWR->CSR & PWR_CSR_ODSWRDY)
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;
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#endif
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/* Waiting for PLL lock.*/
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while (!(RCC->CR & RCC_CR_PLLRDY))
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;
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#endif /* STM32_OVERDRIVE_REQUIRED */
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#if STM32_ACTIVATE_PLLI2S
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/* PLLI2S activation.*/
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RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN;
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RCC->CR |= RCC_CR_PLLI2SON;
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/* Waiting for PLL lock.*/
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while (!(RCC->CR & RCC_CR_PLLI2SRDY))
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; /* Waits until PLLI2S is stable. */
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;
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#endif
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/* Other clock-related settings (dividers, MCO etc).*/
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@ -53,17 +53,21 @@
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#define HAL_IMPLEMENTS_COUNTERS TRUE
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/**
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* @name Platform identification
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* @name Platform identification macros
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* @{
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*/
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#if defined(STM32F429_439xx) || defined(__DOXYGEN__)
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#define PLATFORM_NAME "STM32F429/F439 High Performance with DSP and FPU"
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#define STM32F4XX
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#elif defined(STM32F427_437xx) || defined(__DOXYGEN__)
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#define PLATFORM_NAME "STM32F427/F437 High Performance with DSP and FPU"
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#define STM32F4XX
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#elif defined(STM32F40_41xxx) || defined(__DOXYGEN__)
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#define PLATFORM_NAME "STM32F407/F417 High Performance with DSP and FPU"
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#define STM32F4XX
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#elif defined(STM32F401) || defined(__DOXYGEN__)
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#define PLATFORM_NAME "STM32F401 High Performance with DSP and FPU"
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#define STM32F4XX
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#elif defined(STM32F2XX) || defined(__DOXYGEN__)
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#define PLATFORM_NAME "STM32F2xx High Performance"
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#else
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@ -81,6 +85,11 @@
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*/
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#if defined(STM32F429_439xx) || defined(STM32F429_439xx) || \
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defined(__DOXYGEN__)
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/**
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* @brief Absolute maximum system clock.
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*/
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#define STM32_SYSCLK_MAX 180000000
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/**
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* @brief Maximum HSE clock frequency.
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*/
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@ -159,10 +168,11 @@
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/**
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* @brief Maximum SPI/I2S clock frequency.
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*/
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#define STM32_SPII2S_MAX 37500000
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#define STM32_SPII2S_MAX 45000000
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#endif /* STM32F40_41xxx */
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#if defined(STM32F40_41xxx) || defined(__DOXYGEN__)
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#define STM32_SYSCLK_MAX 168000000
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#define STM32_HSECLK_MAX 26000000
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#define STM32_HSECLK_BYP_MAX 50000000
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#define STM32_HSECLK_MIN 4000000
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@ -178,10 +188,11 @@
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#define STM32_PLLOUT_MIN 24000000
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#define STM32_PCLK1_MAX 42000000
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#define STM32_PCLK2_MAX 84000000
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#define STM32_SPII2S_MAX 37500000
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#define STM32_SPII2S_MAX 42000000
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#endif /* STM32F40_41xxx */
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#if defined(STM32F401) || defined(__DOXYGEN__)
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#define STM32_SYSCLK_MAX 84000000
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#define STM32_HSECLK_MAX 26000000
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#define STM32_HSECLK_BYP_MAX 50000000
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#define STM32_HSECLK_MIN 4000000
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@ -193,11 +204,11 @@
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#define STM32_PLLIN_MIN 950000
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#define STM32_PLLVCO_MAX 432000000
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#define STM32_PLLVCO_MIN 192000000
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#define STM32_PLLOUT_MAX 168000000
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#define STM32_PLLOUT_MAX 84000000
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#define STM32_PLLOUT_MIN 24000000
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#define STM32_PCLK1_MAX 42000000
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#define STM32_PCLK2_MAX 84000000
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#define STM32_SPII2S_MAX 37500000
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#define STM32_SPII2S_MAX 42000000
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#endif /* STM32F40_41xxx */
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#if defined(STM32F2XX)
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@ -217,7 +228,7 @@
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#define STM32_PLLOUT_MIN 24000000
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#define STM32_PCLK1_MAX 30000000
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#define STM32_PCLK2_MAX 60000000
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#define STM32_SPII2S_MAX 37500000
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#define STM32_SPII2S_MAX 30000000
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#endif /* defined(STM32F2XX) */
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/** @} */
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@ -233,24 +244,9 @@
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* @name PWR_CR register bits definitions
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* @{
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*/
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#if defined(STM32F4XX) || defined(__DOXYGEN__)
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#define STM32_VOS_MASK (1 << 14) /**< Core voltage mask. */
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#define STM32_VOS_LOW (0 << 14) /**< Core voltage set to low. */
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#define STM32_VOS_HIGH (1 << 14) /**< Core voltage set to high. */
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#endif
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#if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \
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defined(STM32F401) || defined(__DOXYGEN__)
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#define STM32_VOS_MASK (3 << 14) /**< Scale Mode mask. */
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#elif defined(STM32F40_41xxx) || defined(__DOXYGEN__)
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#define STM32_VOS_MASK (1 << 14) /**< Scale Mode mask. */
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#else
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#endif
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#define STM32_VOS_SCALE3 (1 << 14) /**< Scale 3 mode. */
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#define STM32_VOS_SCALE2 (2 << 14) /**< Scale 2 mode. */
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#define STM32_VOS_SCALE1 (3 << 14) /**< Scale 2 mode. */
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#define STM32_VOS_SCALE3 (PWR_CR_VOS_0)
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#define STM32_VOS_SCALE2 (PWR_CR_VOS_1)
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#define STM32_VOS_SCALE1 (PWR_CR_VOS_1 | PWR_CR_VOS_0)
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#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
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#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
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#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */
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@ -738,16 +734,6 @@
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#endif
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#if defined(STM32F4XX) || defined(__DOXYGEN__)
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/**
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* @brief Core voltage selection.
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* @note This setting affects all the performance and clock related
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* settings, the maximum performance is only obtainable selecting
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* the maximum voltage.
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*/
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#if !defined(STM32_VOS) || defined(__DOXYGEN__)
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#define STM32_VOS STM32_VOS_HIGH
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#endif
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/**
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* @brief Clock source for the PLLs.
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* @note This setting has only effect if the PLL is selected as the
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@ -947,14 +933,6 @@
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*
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* Generic STM32F4XX identifier for backward compatibility.
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*/
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#if defined(STM32F401xx) || defined(STM32F40_41xxx) || \
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defined(STM32F427_437xx) || defined(STM32F429_439xx)
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#define STM32F4XX
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#endif
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#if defined(STM32F4XX) || defined(__DOXYGEN__)
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/*
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* Configuration-related checks.
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@ -963,16 +941,6 @@
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#error "Using a wrong mcuconf.h file, STM32F4xx_MCUCONF not defined"
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#endif
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/**
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* @brief Maximum SYSCLK.
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* @note It is a function of the core voltage setting.
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*/
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#if (STM32_VOS == STM32_VOS_SCALE1) || defined(__DOXYGEN__)
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#define STM32_SYSCLK_MAX 168000000
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#else
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#define STM32_SYSCLK_MAX 144000000
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#endif
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#else /* !defined(STM32F4XX) */
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/*
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* Configuration-related checks.
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@ -986,16 +954,18 @@
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* @brief Maximum frequency thresholds and wait states for flash access.
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* @note The values are valid for 2.7V to 3.6V supply range.
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*/
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#if defined(STM32F4XX) || defined(__DOXYGEN__)
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#if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \
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defined(STM32F40_41xxx) || defined(__DOXYGEN__)
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#if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__)
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#define STM32_0WS_THRESHOLD 30000000
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#define STM32_1WS_THRESHOLD 60000000
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#define STM32_2WS_THRESHOLD 90000000
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#define STM32_3WS_THRESHOLD 120000000
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#define STM32_4WS_THRESHOLD 150000000
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#define STM32_5WS_THRESHOLD 168000000
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#define STM32_5WS_THRESHOLD 180000000
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#define STM32_6WS_THRESHOLD 0
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#define STM32_7WS_THRESHOLD 0
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#define STM32_8WS_THRESHOLD 0
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#elif (STM32_VDD >= 240) && (STM32_VDD < 270)
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#define STM32_0WS_THRESHOLD 24000000
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#define STM32_1WS_THRESHOLD 48000000
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#define STM32_4WS_THRESHOLD 120000000
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#define STM32_5WS_THRESHOLD 144000000
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#define STM32_6WS_THRESHOLD 168000000
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#define STM32_7WS_THRESHOLD 180000000
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#define STM32_8WS_THRESHOLD 0
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#elif (STM32_VDD >= 210) && (STM32_VDD < 240)
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#define STM32_0WS_THRESHOLD 22000000
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#define STM32_1WS_THRESHOLD 44000000
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#define STM32_2WS_THRESHOLD 66000000
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#define STM32_3WS_THRESHOLD 88000000
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#define STM32_4WS_THRESHOLD 110000000
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#define STM32_5WS_THRESHOLD 132000000
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#define STM32_6WS_THRESHOLD 154000000
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#define STM32_7WS_THRESHOLD 176000000
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#define STM32_8WS_THRESHOLD 180000000
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#elif (STM32_VDD >= 180) && (STM32_VDD < 210)
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#define STM32_0WS_THRESHOLD 20000000
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#define STM32_1WS_THRESHOLD 40000000
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#define STM32_2WS_THRESHOLD 60000000
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#define STM32_3WS_THRESHOLD 80000000
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#define STM32_4WS_THRESHOLD 100000000
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#define STM32_5WS_THRESHOLD 120000000
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#define STM32_6WS_THRESHOLD 140000000
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#define STM32_7WS_THRESHOLD 168000000
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#define STM32_8WS_THRESHOLD 0
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#else
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#error "invalid VDD voltage specified"
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#endif
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#elif defined(STM32F401)
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#if (STM32_VDD >= 270) && (STM32_VDD <= 360)
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#define STM32_0WS_THRESHOLD 30000000
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#define STM32_1WS_THRESHOLD 60000000
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#define STM32_2WS_THRESHOLD 84000000
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#define STM32_3WS_THRESHOLD 0
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#define STM32_4WS_THRESHOLD 0
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#define STM32_5WS_THRESHOLD 0
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#define STM32_6WS_THRESHOLD 0
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#define STM32_7WS_THRESHOLD 0
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#define STM32_8WS_THRESHOLD 0
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#elif (STM32_VDD >= 240) && (STM32_VDD < 270)
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#define STM32_0WS_THRESHOLD 24000000
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#define STM32_1WS_THRESHOLD 48000000
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#define STM32_2WS_THRESHOLD 72000000
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#define STM32_3WS_THRESHOLD 84000000
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#define STM32_4WS_THRESHOLD 0
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#define STM32_5WS_THRESHOLD 0
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#define STM32_6WS_THRESHOLD 0
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#define STM32_7WS_THRESHOLD 0
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#define STM32_8WS_THRESHOLD 0
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#elif (STM32_VDD >= 210) && (STM32_VDD < 240)
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#define STM32_0WS_THRESHOLD 18000000
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#define STM32_1WS_THRESHOLD 36000000
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#define STM32_2WS_THRESHOLD 54000000
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#define STM32_3WS_THRESHOLD 72000000
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#define STM32_4WS_THRESHOLD 90000000
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#define STM32_5WS_THRESHOLD 108000000
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#define STM32_6WS_THRESHOLD 120000000
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#define STM32_7WS_THRESHOLD 138000000
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#define STM32_4WS_THRESHOLD 840000000
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#define STM32_5WS_THRESHOLD 0
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#define STM32_6WS_THRESHOLD 0
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#define STM32_7WS_THRESHOLD 0
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#define STM32_8WS_THRESHOLD 0
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#elif (STM32_VDD >= 180) && (STM32_VDD < 210)
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#define STM32_0WS_THRESHOLD 16000000
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#define STM32_1WS_THRESHOLD 32000000
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#define STM32_2WS_THRESHOLD 48000000
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#define STM32_3WS_THRESHOLD 64000000
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#define STM32_4WS_THRESHOLD 80000000
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#define STM32_5WS_THRESHOLD 96000000
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#define STM32_6WS_THRESHOLD 112000000
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#define STM32_7WS_THRESHOLD 128000000
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#define STM32_4WS_THRESHOLD 800000000
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#define STM32_5WS_THRESHOLD 840000000
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#define STM32_6WS_THRESHOLD 0
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#define STM32_7WS_THRESHOLD 0
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#define STM32_8WS_THRESHOLD 0
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#else
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#error "invalid VDD voltage specified"
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#endif
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#else /* !defined(STM32F4XX) */
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#if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__)
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#else /* STM32F2XX */
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#if (STM32_VDD >= 270) && (STM32_VDD <= 360)
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#define STM32_0WS_THRESHOLD 30000000
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#define STM32_1WS_THRESHOLD 60000000
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#define STM32_2WS_THRESHOLD 90000000
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#else
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#error "invalid VDD voltage specified"
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#endif
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#endif /* !defined(STM32F4XX) */
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#endif /* STM32F2XX */
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/*
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* HSI related checks.
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#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
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#endif
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/* Calculating VOS settings, it is different for each sub-platform.*/
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#if defined(STM32F429_439xx) || defined(STM32F427_437xx) || \
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defined(__DOXYGEN__)
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#if STM32_SYSCLK <= 120000000
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#define STM32_VOS STM32_VOS_SCALE3
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#define STM32_OVERDRIVE_REQUIRED FALSE
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#elif STM32_SYSCLK <= 144000000
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#define STM32_VOS STM32_VOS_SCALE2
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#define STM32_OVERDRIVE_REQUIRED FALSE
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#elif STM32_SYSCLK <= 168000000
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#define STM32_VOS STM32_VOS_SCALE1
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#define STM32_OVERDRIVE_REQUIRED FALSE
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#else
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#define STM32_VOS STM32_VOS_SCALE1
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#define STM32_OVERDRIVE_REQUIRED TRUE
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#endif
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#elif defined(STM32F40_41xxx)
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#if STM32_SYSCLK <= 144000000
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#define STM32_VOS STM32_VOS_SCALE2
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#else
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#define STM32_VOS STM32_VOS_SCALE1
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#endif
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#define STM32_OVERDRIVE_REQUIRED FALSE
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#elif defined(STM32F401)
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#if STM32_SYSCLK <= 60000000
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#define STM32_VOS STM32_VOS_SCALE3
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#else
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#define STM32_VOS STM32_VOS_SCALE2
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#endif
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#define STM32_OVERDRIVE_REQUIRED FALSE
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#else /* STM32F2XX */
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#define STM32_OVERDRIVE_REQUIRED FALSE
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#endif
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/**
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* @brief AHB frequency.
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*/
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#define STM32_FLASHBITS 0x00000005
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#elif STM32_HCLK <= STM32_6WS_THRESHOLD
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#define STM32_FLASHBITS 0x00000006
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#else
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#elif STM32_HCLK <= STM32_7WS_THRESHOLD
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#define STM32_FLASHBITS 0x00000007
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#else
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#define STM32_FLASHBITS 0x00000008
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#endif
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/* There are differences in vector names in the various sub-families,
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