diff --git a/demos/PPC-SPC560D-GCC/mcuconf.h b/demos/PPC-SPC560D-GCC/mcuconf.h index dd1deb91e..a62a73496 100644 --- a/demos/PPC-SPC560D-GCC/mcuconf.h +++ b/demos/PPC-SPC560D-GCC/mcuconf.h @@ -23,6 +23,8 @@ * * IRQ priorities: * 1...15 Lowest...Highest. + * DMA priorities: + * 0...15 Highest...Lowest. */ #define SPC560Dxx_MCUCONF @@ -161,6 +163,15 @@ #define SPC5_PIT0_IRQ_PRIORITY 4 #define SPC5_CLOCK_FAILURE_HOOK() chSysHalt() +/* + * EDMA driver settings. + */ +#define SPC5_EDMA_CR_SETTING 0 +#define SPC5_EDMA_GROUP0_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_ERROR_IRQ_PRIO 2 +#define SPC5_EDMA_ERROR_HANDLER() chSysHalt() + /* * SERIAL driver system settings. */ @@ -182,3 +193,38 @@ SPC5_ME_PCTL_LP(2)) #define SPC5_SERIAL_LINFLEX2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ SPC5_ME_PCTL_LP(0)) + +/* + * SPI driver system settings. + */ +#define SPC5_SPI_USE_DSPI0 FALSE +#define SPC5_SPI_USE_DSPI1 FALSE +#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI0_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_IRQ_PRIO 10 +#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt() +#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) diff --git a/demos/PPC-SPC563M-GCC/mcuconf.h b/demos/PPC-SPC563M-GCC/mcuconf.h index 98e536d37..28a5790f5 100644 --- a/demos/PPC-SPC563M-GCC/mcuconf.h +++ b/demos/PPC-SPC563M-GCC/mcuconf.h @@ -23,6 +23,8 @@ * * IRQ priorities: * 1...15 Lowest...Highest. + * DMA priorities: + * 0...15 Highest...Lowest. */ #define SPC563Mxx_MCUCONF @@ -44,6 +46,25 @@ BIUCR_PFLIM_ON_MISS | \ BIUCR_BFEN) +/* + * EDMA driver settings. + */ +#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP3PRI(3) | \ + EDMA_CR_GRP2PRI(2) | \ + EDMA_CR_GRP1PRI(1) | \ + EDMA_CR_GRP0PRI(0) | \ + EDMA_CR_ERGA) +#define SPC5_EDMA_GROUP0_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_GROUP1_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_GROUP2_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_GROUP3_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_ERROR_IRQ_PRIO 2 +#define SPC5_EDMA_ERROR_HANDLER() chSysHalt() + /* * ADC driver settings. */ @@ -53,12 +74,6 @@ #define SPC5_ADC_USE_ADC1_Q3 FALSE #define SPC5_ADC_USE_ADC1_Q4 FALSE #define SPC5_ADC_USE_ADC1_Q5 FALSE -#define SPC5_ADC_FIFO0_DMA_PRIO 12 -#define SPC5_ADC_FIFO1_DMA_PRIO 12 -#define SPC5_ADC_FIFO2_DMA_PRIO 12 -#define SPC5_ADC_FIFO3_DMA_PRIO 12 -#define SPC5_ADC_FIFO4_DMA_PRIO 12 -#define SPC5_ADC_FIFO5_DMA_PRIO 12 #define SPC5_ADC_FIFO0_DMA_IRQ_PRIO 12 #define SPC5_ADC_FIFO1_DMA_IRQ_PRIO 12 #define SPC5_ADC_FIFO2_DMA_IRQ_PRIO 12 @@ -104,8 +119,6 @@ SPC5_MCR_PCSIS5 | \ SPC5_MCR_PCSIS6 | \ SPC5_MCR_PCSIS7) -#define SPC5_SPI_DSPI1_DMA_PRIO 10 -#define SPC5_SPI_DSPI2_DMA_PRIO 10 #define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 #define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10 #define SPC5_SPI_DSPI1_IRQ_PRIO 10 diff --git a/os/hal/platforms/SPC560Dxx/hal_lld.c b/os/hal/platforms/SPC560Dxx/hal_lld.c index b027e1ac4..229051979 100644 --- a/os/hal/platforms/SPC560Dxx/hal_lld.c +++ b/os/hal/platforms/SPC560Dxx/hal_lld.c @@ -96,6 +96,9 @@ void hal_lld_init(void) { PIT.CH[0].CVAL.R = reg; PIT.CH[0].TFLG.R = 1; /* Interrupt flag cleared. */ PIT.CH[0].TCTRL.R = 3; /* Timer active, interrupt enabled. */ + + /* EDMA initialization.*/ + edmaInit(); } /** diff --git a/os/hal/platforms/SPC560Dxx/platform.mk b/os/hal/platforms/SPC560Dxx/platform.mk index 6505aa352..8e6c8d73a 100644 --- a/os/hal/platforms/SPC560Dxx/platform.mk +++ b/os/hal/platforms/SPC560Dxx/platform.mk @@ -1,11 +1,13 @@ # List of all the SPC560Dxx platform files. PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/SPC560Dxx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c \ ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c \ ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1/pal_lld.c \ ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1/serial_lld.c # Required include directories PLATFORMINC = ${CHIBIOS}/os/hal/platforms/SPC560Dxx \ + ${CHIBIOS}/os/hal/platforms/SPC5xx/DSPI_v1 \ ${CHIBIOS}/os/hal/platforms/SPC5xx/EDMA_v1 \ ${CHIBIOS}/os/hal/platforms/SPC5xx/SIUL_v1 \ ${CHIBIOS}/os/hal/platforms/SPC5xx/LINFlex_v1 diff --git a/os/hal/platforms/SPC560Dxx/spc560d_registry.h b/os/hal/platforms/SPC560Dxx/spc560d_registry.h index ea5206860..72fd5b36c 100644 --- a/os/hal/platforms/SPC560Dxx/spc560d_registry.h +++ b/os/hal/platforms/SPC560Dxx/spc560d_registry.h @@ -42,6 +42,12 @@ #define SPC5_DSPI_FIFO_DEPTH 4 #define SPC5_DSPI0_PCTL 4 #define SPC5_DSPI1_PCTL 5 +#define SPC5_DSPI0_TX1_DMA_CH_ID 4 +#define SPC5_DSPI0_TX2_DMA_CH_ID 5 +#define SPC5_DSPI0_RX_DMA_CH_ID 6 +#define SPC5_DSPI1_TX1_DMA_CH_ID 7 +#define SPC5_DSPI1_TX2_DMA_CH_ID 8 +#define SPC5_DSPI1_RX_DMA_CH_ID 9 #define SPC5_DSPI0_TX1_DMA_DEV_ID 1 #define SPC5_DSPI0_TX2_DMA_DEV_ID 0 #define SPC5_DSPI0_RX_DMA_DEV_ID 2 @@ -65,6 +71,7 @@ #define SPC5_HAS_EDMA TRUE #define SPC5_EDMA_NCHANNELS 16 #define SPC5_EDMA_HAS_MUX TRUE +#define SPC5_EDMA_MUX_PCTL 23 /* LINFlex attributes.*/ #define SPC5_HAS_LINFLEX0 TRUE diff --git a/os/hal/platforms/SPC560Pxx/hal_lld.c b/os/hal/platforms/SPC560Pxx/hal_lld.c index 1a6cc24af..799908d46 100644 --- a/os/hal/platforms/SPC560Pxx/hal_lld.c +++ b/os/hal/platforms/SPC560Pxx/hal_lld.c @@ -96,6 +96,9 @@ void hal_lld_init(void) { PIT.CH[0].CVAL.R = reg; PIT.CH[0].TFLG.R = 1; /* Interrupt flag cleared. */ PIT.CH[0].TCTRL.R = 3; /* Timer active, interrupt enabled. */ + + /* EDMA initialization.*/ + edmaInit(); } /** diff --git a/os/hal/platforms/SPC563Mxx/hal_lld.c b/os/hal/platforms/SPC563Mxx/hal_lld.c index 7e2f32319..22979e61b 100644 --- a/os/hal/platforms/SPC563Mxx/hal_lld.c +++ b/os/hal/platforms/SPC563Mxx/hal_lld.c @@ -94,6 +94,9 @@ void hal_lld_init(void) { INTC.MCR.R = 0; INTC.CPR.R = 0; INTC.IACKR.R = (uint32_t)_vectors; + + /* EDMA initialization.*/ + edmaInit(); } /** diff --git a/os/hal/platforms/SPC563Mxx/spc563m_registry.h b/os/hal/platforms/SPC563Mxx/spc563m_registry.h index dc1145532..b26a65de9 100644 --- a/os/hal/platforms/SPC563Mxx/spc563m_registry.h +++ b/os/hal/platforms/SPC563Mxx/spc563m_registry.h @@ -40,12 +40,12 @@ #define SPC5_HAS_DSPI3 FALSE #define SPC5_HAS_DSPI4 FALSE #define SPC5_DSPI_FIFO_DEPTH 16 -#define SPC5_DSPI1_TX1_DMA_DEV_ID 12 -#define SPC5_DSPI1_TX2_DMA_DEV_ID 25 -#define SPC5_DSPI1_RX_DMA_DEV_ID 13 -#define SPC5_DSPI2_TX1_DMA_DEV_ID 14 -#define SPC5_DSPI2_TX2_DMA_DEV_ID 26 -#define SPC5_DSPI2_RX_DMA_DEV_ID 15 +#define SPC5_DSPI1_TX1_DMA_CH_ID 12 +#define SPC5_DSPI1_TX2_DMA_CH_ID 25 +#define SPC5_DSPI1_RX_DMA_CH_ID 13 +#define SPC5_DSPI2_TX1_DMA_CH_ID 14 +#define SPC5_DSPI2_TX2_DMA_CH_ID 26 +#define SPC5_DSPI2_RX_DMA_CH_ID 15 #define SPC5_DSPI1_EOQF_HANDLER vector132 #define SPC5_DSPI1_EOQF_NUMBER 132 #define SPC5_DSPI1_TFFF_HANDLER vector133 diff --git a/os/hal/platforms/SPC564Axx/hal_lld.c b/os/hal/platforms/SPC564Axx/hal_lld.c index 7d87468ec..f6b220c85 100644 --- a/os/hal/platforms/SPC564Axx/hal_lld.c +++ b/os/hal/platforms/SPC564Axx/hal_lld.c @@ -106,6 +106,9 @@ void hal_lld_init(void) { INTC.MCR.R = 0; INTC.CPR.R = 0; INTC.IACKR.R = (uint32_t)_vectors; + + /* EDMA initialization.*/ + edmaInit(); } /** diff --git a/os/hal/platforms/SPC56ELxx/hal_lld.c b/os/hal/platforms/SPC56ELxx/hal_lld.c index 29ca160eb..4a3976f50 100644 --- a/os/hal/platforms/SPC56ELxx/hal_lld.c +++ b/os/hal/platforms/SPC56ELxx/hal_lld.c @@ -79,6 +79,9 @@ void hal_lld_init(void) { INTC.MCR.R = 0; INTC.CPR.R = 0; INTC.IACKR.R = (uint32_t)_vectors; + + /* EDMA initialization.*/ + edmaInit(); } /** diff --git a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c b/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c index ad0e48115..f5db08a75 100644 --- a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c +++ b/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c @@ -94,7 +94,11 @@ SPIDriver SPID5; * @brief DMA configuration for DSPI0 TX1. */ static const edma_channel_config_t spi_dspi0_tx1_dma_config = { - SPC5_DSPI0_TX1_DMA_DEV_ID, SPC5_SPI_DSPI0_DMA_PRIO, SPC5_SPI_DSPI0_DMA_IRQ_PRIO, + SPC5_DSPI0_TX1_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + SPC5_DSPI0_TX1_DMA_DEV_ID, +#endif + SPC5_SPI_DSPI0_DMA_IRQ_PRIO, spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID1 }; @@ -102,7 +106,11 @@ static const edma_channel_config_t spi_dspi0_tx1_dma_config = { * @brief DMA configuration for DSPI0 TX2. */ static const edma_channel_config_t spi_dspi0_tx2_dma_config = { - SPC5_DSPI0_TX2_DMA_DEV_ID, SPC5_SPI_DSPI0_DMA_PRIO, SPC5_SPI_DSPI0_DMA_IRQ_PRIO, + SPC5_DSPI0_TX2_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + 0, +#endif + SPC5_SPI_DSPI0_DMA_IRQ_PRIO, spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID1 }; @@ -110,7 +118,11 @@ static const edma_channel_config_t spi_dspi0_tx2_dma_config = { * @brief DMA configuration for DSPI0 RX. */ static const edma_channel_config_t spi_dspi0_rx_dma_config = { - SPC5_DSPI0_RX_DMA_DEV_ID, SPC5_SPI_DSPI0_DMA_PRIO, SPC5_SPI_DSPI0_DMA_IRQ_PRIO, + SPC5_DSPI0_RX_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + SPC5_DSPI0_RX_DMA_DEV_ID, +#endif + SPC5_SPI_DSPI0_DMA_IRQ_PRIO, spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID1 }; #endif /* SPC5_SPI_USE_DSPI0 */ @@ -120,7 +132,11 @@ static const edma_channel_config_t spi_dspi0_rx_dma_config = { * @brief DMA configuration for DSPI1 TX1. */ static const edma_channel_config_t spi_dspi1_tx1_dma_config = { - SPC5_DSPI1_TX1_DMA_DEV_ID, SPC5_SPI_DSPI1_DMA_PRIO, SPC5_SPI_DSPI1_DMA_IRQ_PRIO, + SPC5_DSPI1_TX1_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + SPC5_DSPI1_TX1_DMA_DEV_ID, +#endif + SPC5_SPI_DSPI1_DMA_IRQ_PRIO, spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID2 }; @@ -128,7 +144,11 @@ static const edma_channel_config_t spi_dspi1_tx1_dma_config = { * @brief DMA configuration for DSPI1 TX2. */ static const edma_channel_config_t spi_dspi1_tx2_dma_config = { - SPC5_DSPI1_TX2_DMA_DEV_ID, SPC5_SPI_DSPI1_DMA_PRIO, SPC5_SPI_DSPI1_DMA_IRQ_PRIO, + SPC5_DSPI1_TX2_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + 0, +#endif + SPC5_SPI_DSPI1_DMA_IRQ_PRIO, spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID2 }; @@ -136,7 +156,11 @@ static const edma_channel_config_t spi_dspi1_tx2_dma_config = { * @brief DMA configuration for DSPI1 RX. */ static const edma_channel_config_t spi_dspi1_rx_dma_config = { - SPC5_DSPI1_RX_DMA_DEV_ID, SPC5_SPI_DSPI1_DMA_PRIO, SPC5_SPI_DSPI1_DMA_IRQ_PRIO, + SPC5_DSPI1_RX_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + SPC5_DSPI1_RX_DMA_DEV_ID, +#endif + SPC5_SPI_DSPI1_DMA_IRQ_PRIO, spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID2 }; #endif /* SPC5_SPI_USE_DSPI1 */ @@ -146,7 +170,11 @@ static const edma_channel_config_t spi_dspi1_rx_dma_config = { * @brief DMA configuration for DSPI2 TX1. */ static const edma_channel_config_t spi_dspi2_tx1_dma_config = { - SPC5_DSPI2_TX1_DMA_DEV_ID, SPC5_SPI_DSPI2_DMA_PRIO, SPC5_SPI_DSPI2_DMA_IRQ_PRIO, + SPC5_DSPI2_TX1_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + SPC5_DSPI2_TX1_DMA_DEV_ID, +#endif + SPC5_SPI_DSPI2_DMA_IRQ_PRIO, spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID3 }; @@ -154,7 +182,11 @@ static const edma_channel_config_t spi_dspi2_tx1_dma_config = { * @brief DMA configuration for DSPI2 TX2. */ static const edma_channel_config_t spi_dspi2_tx2_dma_config = { - SPC5_DSPI2_TX2_DMA_DEV_ID, SPC5_SPI_DSPI2_DMA_PRIO, SPC5_SPI_DSPI2_DMA_IRQ_PRIO, + SPC5_DSPI2_TX2_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + 0, +#endif + SPC5_SPI_DSPI2_DMA_IRQ_PRIO, spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID3 }; @@ -162,7 +194,11 @@ static const edma_channel_config_t spi_dspi2_tx2_dma_config = { * @brief DMA configuration for DSPI2 RX. */ static const edma_channel_config_t spi_dspi2_rx_dma_config = { - SPC5_DSPI2_RX_DMA_DEV_ID, SPC5_SPI_DSPI2_DMA_PRIO, SPC5_SPI_DSPI2_DMA_IRQ_PRIO, + SPC5_DSPI2_RX_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + SPC5_DSPI2_RX_DMA_DEV_ID, +#endif + SPC5_SPI_DSPI2_DMA_IRQ_PRIO, spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID3 }; #endif /* SPC5_SPI_USE_DSPI2 */ @@ -172,7 +208,11 @@ static const edma_channel_config_t spi_dspi2_rx_dma_config = { * @brief DMA configuration for DSPI3 TX1. */ static const edma_channel_config_t spi_dspi3_tx1_dma_config = { - SPC5_DSPI3_TX1_DMA_DEV_ID, SPC5_SPI_DSPI3_DMA_PRIO, SPC5_SPI_DSPI3_DMA_IRQ_PRIO, + SPC5_DSPI3_TX1_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + SPC5_DSPI3_TX1_DMA_DEV_ID, +#endif + SPC5_SPI_DSPI3_DMA_IRQ_PRIO, spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID4 }; @@ -180,7 +220,11 @@ static const edma_channel_config_t spi_dspi3_tx1_dma_config = { * @brief DMA configuration for DSPI3 TX2. */ static const edma_channel_config_t spi_dspi3_tx2_dma_config = { - SPC5_DSPI3_TX2_DMA_DEV_ID, SPC5_SPI_DSPI3_DMA_PRIO, SPC5_SPI_DSPI3_DMA_IRQ_PRIO, + SPC5_DSPI3_TX2_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + 0, +#endif + SPC5_SPI_DSPI3_DMA_IRQ_PRIO, spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID4 }; @@ -188,7 +232,11 @@ static const edma_channel_config_t spi_dspi3_tx2_dma_config = { * @brief DMA configuration for DSPI3 RX. */ static const edma_channel_config_t spi_dspi3_rx_dma_config = { - SPC5_DSPI3_RX_DMA_DEV_ID, SPC5_SPI_DSPI3_DMA_PRIO, SPC5_SPI_DSPI3_DMA_IRQ_PRIO, + SPC5_DSPI3_RX_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + SPC5_DSPI3_RX_DMA_DEV_ID, +#endif + SPC5_SPI_DSPI3_DMA_IRQ_PRIO, spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID4 }; #endif /* SPC5_SPI_USE_DSPI3 */ @@ -198,7 +246,11 @@ static const edma_channel_config_t spi_dspi3_rx_dma_config = { * @brief DMA configuration for DSPI4 TX1. */ static const edma_channel_config_t spi_dspi4_tx1_dma_config = { - SPC5_DSPI4_TX1_DMA_DEV_ID, SPC5_SPI_DSPI4_DMA_PRIO, SPC5_SPI_DSPI4_DMA_IRQ_PRIO, + SPC5_DSPI4_TX1_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + SPC5_DSPI4_TX1_DMA_DEV_ID, +#endif + SPC5_SPI_DSPI4_DMA_IRQ_PRIO, spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID5 }; @@ -206,7 +258,11 @@ static const edma_channel_config_t spi_dspi4_tx1_dma_config = { * @brief DMA configuration for DSPI4 TX2. */ static const edma_channel_config_t spi_dspi4_tx2_dma_config = { - SPC5_DSPI4_TX2_DMA_DEV_ID, SPC5_SPI_DSPI4_DMA_PRIO, SPC5_SPI_DSPI4_DMA_IRQ_PRIO, + SPC5_DSPI4_TX2_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + 0, +#endif + SPC5_SPI_DSPI4_DMA_IRQ_PRIO, spi_serve_tx_irq, spi_serve_dma_error_irq, &SPID5 }; @@ -214,7 +270,11 @@ static const edma_channel_config_t spi_dspi4_tx2_dma_config = { * @brief DMA configuration for DSPI4 RX. */ static const edma_channel_config_t spi_dspi4_rx_dma_config = { - SPC5_DSPI4_RX_DMA_DEV_ID, SPC5_SPI_DSPI4_DMA_PRIO, SPC5_SPI_DSPI4_DMA_IRQ_PRIO, + SPC5_DSPI4_RX_DMA_CH_ID, +#if SPC5_EDMA_HAS_MUX + SPC5_DSPI4_RX_DMA_DEV_ID, +#endif + SPC5_SPI_DSPI4_DMA_IRQ_PRIO, spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID5 }; #endif /* SPC5_SPI_USE_DSPI4 */ diff --git a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h b/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h index 95c4c72ab..b79e13a8e 100644 --- a/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h +++ b/os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h @@ -73,6 +73,14 @@ #define SPC5_SPI_USE_DSPI3 FALSE #endif +/** + * @brief SPID5 driver enable switch. + * @details If set to @p TRUE the support for DSPI4 is included. + */ +#if !defined(SPC5_SPI_USE_DSPI4) || defined(__DOXYGEN__) +#define SPC5_SPI_USE_DSPI4 FALSE +#endif + /** * @brief DSPI0 MCR PCS defaults. */ @@ -130,31 +138,17 @@ #endif /** - * @brief DSPI0 DMA priority. + * @brief DSPI4 MCR PCS defaults. */ -#if !defined(SPC5_SPI_DSPI0_DMA_PRIO) || defined(__DOXYGEN__) -#define SPC5_SPI_DSPI0_DMA_PRIO 10 -#endif - -/** - * @brief DSPI1 DMA priority. - */ -#if !defined(SPC5_SPI_DSPI1_DMA_PRIO) || defined(__DOXYGEN__) -#define SPC5_SPI_DSPI1_DMA_PRIO 10 -#endif - -/** - * @brief DSPI2 DMA priority. - */ -#if !defined(SPC5_SPI_DSPI2_DMA_PRIO) || defined(__DOXYGEN__) -#define SPC5_SPI_DSPI2_DMA_PRIO 10 -#endif - -/** - * @brief DSPI3 DMA priority. - */ -#if !defined(SPC5_SPI_DSPI3_DMA_PRIO) || defined(__DOXYGEN__) -#define SPC5_SPI_DSPI3_DMA_PRIO 10 +#if !defined(SPC5_SPI_DSPI4_MCR) || defined(__DOXYGEN__) +#define SPC5_SPI_DSPI4_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) #endif /** @@ -185,6 +179,13 @@ #define SPC5_SPI_DSPI3_DMA_IRQ_PRIO 10 #endif +/** + * @brief DSPI4 DMA IRQ priority. + */ +#if !defined(SPC5_SPI_DSPI4_DMA_IRQ_PRIO) || defined(__DOXYGEN__) +#define SPC5_SPI_DSPI4_DMA_IRQ_PRIO 10 +#endif + /** * @brief SPI DMA error hook. */ @@ -220,6 +221,13 @@ #define SPC5_SPI_DSPI3_IRQ_PRIO 10 #endif +/** + * @brief DSPI4 DMA priority. + */ +#if !defined(SPC5_SPI_DSPI4_IRQ_PRIO) || defined(__DOXYGEN__) +#define SPC5_SPI_DSPI4_IRQ_PRIO 10 +#endif + /** * @brief DSPI0 peripheral configuration when started. * @note The default configuration is 1 (always run) in run mode and diff --git a/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c b/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c index e13356197..7aad4027f 100644 --- a/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c +++ b/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c @@ -31,6 +31,15 @@ /* Driver local definitions. */ /*===========================================================================*/ +static const uint8_t g0[16] = {SPC5_EDMA_GROUP0_PRIORITIES}; +#if (SPC5_EDMA_NCHANNELS > 16) || defined(__DOXYGEN__) +static const uint8_t g1[16] = {SPC5_EDMA_GROUP1_PRIORITIES}; +#endif +#if (SPC5_EDMA_NCHANNELS > 32) || defined(__DOXYGEN__) +static const uint8_t g2[16] = {SPC5_EDMA_GROUP2_PRIORITIES}; +static const uint8_t g3[16] = {SPC5_EDMA_GROUP3_PRIORITIES}; +#endif + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -1290,64 +1299,74 @@ void edmaInit(void) { SPC5_EDMA.EEIRL.R = 0x00000000; SPC5_EDMA.IRQRL.R = 0xFFFFFFFF; SPC5_EDMA.ERL.R = 0xFFFFFFFF; - for (i = 0; i < SPC5_EDMA_NCHANNELS; i++) - SPC5_EDMA.CPR[i].R = 0; +#if SPC5_EDMA_NCHANNELS > 32 + SPC5_EDMA.ERQRH.R = 0x00000000; + SPC5_EDMA.EEIRH.R = 0x00000000; + SPC5_EDMA.IRQRH.R = 0xFFFFFFFF; + SPC5_EDMA.ERH.R = 0xFFFFFFFF; +#endif + /* Initializing all the channels with a different priority withing the + channels group.*/ + for (i = 0; i < 16; i++) { + SPC5_EDMA.CPR[i].R = g0[i]; +#if SPC5_EDMA_NCHANNELS > 16 + SPC5_EDMA.CPR[i + 16].R = g1[i]; +#endif +#if SPC5_EDMA_NCHANNELS > 32 + SPC5_EDMA.CPR[i + 32].R = g2[i]; + SPC5_EDMA.CPR[i + 48].R = g3[i]; +#endif + } /* Error interrupt source.*/ INTC.PSR[10].R = SPC5_EDMA_ERROR_IRQ_PRIO; + +#if defined(SPC5_EDMA_MUX_PCTL) + /* DMA MUX PCTL setup, only if required.*/ + halSPCSetPeripheralClockMode(SPC5_EDMA_MUX_PCTL, SPC5_EDMA_MUX_START_PCTL); +#endif } /** * @brief EDMA channel allocation. * * @param[in] ccfg channel configuration - * @return The channel TCD pointer. + * @return The channel number. * @retval EDMA_ERROR if the channel cannot be allocated. * * @special */ edma_channel_t edmaChannelAllocate(const edma_channel_config_t *ccfg) { - edma_channel_t channel; - chDbgCheck((ccfg != NULL) && ((ccfg->dma_prio & 15) < 16) && - (ccfg->dma_irq_prio < 16), + chDbgCheck((ccfg != NULL) && (ccfg->dma_irq_prio < 16), "edmaChannelAllocate"); -#if SPC5_EDMA_HAS_MUX - /* Searching for a free channel, we have the MUX so any channel is - acceptable.*/ - for (channel = 0; channel < SPC5_EDMA_NCHANNELS; channel++) - if (channels[channel] == NULL) - break; - if (channel >= SPC5_EDMA_NCHANNELS) - return EDMA_ERROR; /* No free channels. */ - - /* Programming the MUX.*/ - SPC5_DMAMUX.CHCONFIG[channel].R = (uint8_t)(0x80 | ccfg->dma_periph); -#else /* !SPC5_EDMA_HAS_MUX */ - /* There is no MUX so we can just check that the specified channels is - available.*/ - channel = (edma_channel_t)ccfg->dma_periph; - if (channels[channel] != NULL) + /* If the channel is already taken then an error is returned.*/ + if (channels[ccfg->dma_channel] != NULL) return EDMA_ERROR; /* Already taken. */ + +#if SPC5_EDMA_HAS_MUX + /* Programming the MUX.*/ + SPC5_DMAMUX.CHCONFIG[ccfg->dma_channel].R = (uint8_t)(0x80 | + ccfg->dma_periph); #endif /* !SPC5_EDMA_HAS_MUX */ /* Associating the configuration to the channel.*/ - channels[channel] = ccfg; + channels[ccfg->dma_channel] = ccfg; /* If an error callback is defined then the error interrupt source is enabled for the channel.*/ if (ccfg->dma_error_func != NULL) - SPC5_EDMA.SEEIR.R = channel; + SPC5_EDMA.SEEIR.R = (uint32_t)ccfg->dma_channel; /* Setting up IRQ priority for the selected channel.*/ - INTC.PSR[11 + channel].R = ccfg->dma_irq_prio; + INTC.PSR[11 + ccfg->dma_channel].R = ccfg->dma_irq_prio; - return channel; + return ccfg->dma_channel; } /** - * @brief EDMA channel allocation. + * @brief EDMA channel release. * * @param[in] channel the channel number * diff --git a/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h b/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h index b5e4ea8f7..e66574e4a 100644 --- a/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h +++ b/os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h @@ -36,6 +36,30 @@ */ #define EDMA_ERROR -1 +/** + * @name EDMA CR register definitions + * @{ + */ +#define EDMA_CR_CX (1U << 17) +#define EDMA_CR_ECX (1U << 16) +#define EDMA_CR_GRP3PRI_MASK (3U << 14) +#define EDMA_CR_GRP3PRI(n) ((n) << 14) +#define EDMA_CR_GRP2PRI_MASK (3U << 12) +#define EDMA_CR_GRP2PRI(n) ((n) << 12) +#define EDMA_CR_GRP1PRI_MASK (3U << 10) +#define EDMA_CR_GRP1PRI(n) ((n) << 10) +#define EDMA_CR_GRP0PRI_MASK (3U << 8) +#define EDMA_CR_GRP0PRI(n) ((n) << 8) +#define EDMA_CR_EMLM (1U << 7) +#define EDMA_CR_CLM (1U << 6) +#define EDMA_CR_HALT (1U << 5) +#define EDMA_CR_HOE (1U << 4) +#define EDMA_CR_ERGA (1U << 3) +#define EDMA_CR_ERCA (1U << 2) +#define EDMA_CR_EDBG (1U << 1) +#define EDMA_CR_EBW (1U << 0) +/** @} */ + /** * @name EDMA mode constants * @{ @@ -62,7 +86,61 @@ * @brief Default EDMA CR register initialization. */ #if !defined(SPC5_EDMA_ERROR_HANDLER) || defined(__DOXYGEN__) -#define SPC5_EDMA_CR_SETTING 0x0000C400 +#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP3PRI(3) | \ + EDMA_CR_GRP2PRI(2) | \ + EDMA_CR_GRP1PRI(1) | \ + EDMA_CR_GRP0PRI(0) | \ + EDMA_CR_ERGA) +#endif + +/** + * @brief Static priorities for channels group 0. + */ +#if !defined(SPC5_EDMA_GROUP0_PRIORITIES) || defined(__DOXYGEN__) +#define SPC5_EDMA_GROUP0_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#endif + +/** + * @brief Static priorities for channels group 1. + */ +#if !defined(SPC5_EDMA_GROUP1_PRIORITIES) || defined(__DOXYGEN__) +#define SPC5_EDMA_GROUP1_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#endif + +/** + * @brief Static priorities for channels group 2. + */ +#if !defined(SPC5_EDMA_GROUP2_PRIORITIES) || defined(__DOXYGEN__) +#define SPC5_EDMA_GROUP2_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#endif + +/** + * @brief Static priorities for channels group 3. + */ +#if !defined(SPC5_EDMA_GROUP3_PRIORITIES) || defined(__DOXYGEN__) +#define SPC5_EDMA_GROUP3_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#endif + +/** + * @brief EDMA error handler IRQ priority. + */ +#if !defined(SPC5_EDMA_ERROR_IRQ_PRIO) || defined(__DOXYGEN__) +#define SPC5_EDMA_ERROR_IRQ_PRIO 2 +#endif + +/** + * @brief EDMA peripheral configuration when started. + * @note The default configuration is 1 (always run) in run mode and + * 2 (only halt) in low power mode. The defaults of the run modes + * are defined in @p hal_lld.h. + */ +#if !defined(SPC5_EDMA_MUX_START_PCTL) || defined(__DOXYGEN__) +#define SPC5_EDMA_MUX_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) #endif /** @@ -72,13 +150,6 @@ #define SPC5_EDMA_ERROR_HANDLER() chSysHalt() #endif -/** - * @brief EDMA error handler IRQ priority. - */ -#if !defined(SPC5_EDMA_ERROR_IRQ_PRIO) || defined(__DOXYGEN__) -#define SPC5_EDMA_ERROR_IRQ_PRIO 12 -#endif - /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ @@ -648,10 +719,11 @@ typedef void (*edma_error_callback_t)(edma_channel_t channel, * @brief Type of an EDMA channel configuration structure. */ typedef struct { + edma_channel_t dma_channel; /**< @brief Channel to be allocated.*/ +#if SPC5_EDMA_HAS_MUX || defined(__DOXYGEN__) uint8_t dma_periph; /**< @brief Peripheral to be associated to the channel. */ - uint8_t dma_prio; /**< @brief Priority register value - for this channel. */ +#endif uint8_t dma_irq_prio; /**< @brief IRQ priority level for this channel. */ edma_callback_t dma_func; /**< @brief Channel callback, diff --git a/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c b/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c index 9017ec1e8..cb479fa1b 100644 --- a/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c +++ b/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c @@ -108,7 +108,7 @@ static const uint16_t pudcrs[8] = SPC5_ADC_PUDCR; * @brief DMA configuration for EQADC CFIFO0. */ static const edma_channel_config_t adc_cfifo0_dma_config = { - 0, SPC5_ADC_FIFO0_DMA_PRIO, SPC5_ADC_FIFO0_DMA_IRQ_PRIO, + 0, SPC5_ADC_FIFO0_DMA_IRQ_PRIO, NULL, adc_serve_dma_error_irq, &ADCD1 }; @@ -116,7 +116,7 @@ static const edma_channel_config_t adc_cfifo0_dma_config = { * @brief DMA configuration for EQADC RFIFO0. */ static const edma_channel_config_t adc_rfifo0_dma_config = { - 1, SPC5_ADC_FIFO0_DMA_PRIO, SPC5_ADC_FIFO0_DMA_IRQ_PRIO, + 1, SPC5_ADC_FIFO0_DMA_IRQ_PRIO, adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD1 }; #endif /* SPC5_ADC_USE_ADC0_Q0 */ @@ -126,7 +126,7 @@ static const edma_channel_config_t adc_rfifo0_dma_config = { * @brief DMA configuration for EQADC CFIFO1. */ static const edma_channel_config_t adc_cfifo1_dma_config = { - 2, SPC5_ADC_FIFO1_DMA_PRIO, SPC5_ADC_FIFO1_DMA_IRQ_PRIO, + 2, SPC5_ADC_FIFO1_DMA_IRQ_PRIO, NULL, adc_serve_dma_error_irq, &ADCD2 }; @@ -134,7 +134,7 @@ static const edma_channel_config_t adc_cfifo1_dma_config = { * @brief DMA configuration for EQADC RFIFO1. */ static const edma_channel_config_t adc_rfifo1_dma_config = { - 3, SPC5_ADC_FIFO1_DMA_PRIO, SPC5_ADC_FIFO1_DMA_IRQ_PRIO, + 3, SPC5_ADC_FIFO1_DMA_IRQ_PRIO, adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD2 }; #endif /* SPC5_ADC_USE_ADC0_Q1 */ @@ -144,7 +144,7 @@ static const edma_channel_config_t adc_rfifo1_dma_config = { * @brief DMA configuration for EQADC CFIFO2. */ static const edma_channel_config_t adc_cfifo2_dma_config = { - 4, SPC5_ADC_FIFO2_DMA_PRIO, SPC5_ADC_FIFO2_DMA_IRQ_PRIO, + 4, SPC5_ADC_FIFO2_DMA_IRQ_PRIO, NULL, adc_serve_dma_error_irq, &ADCD3 }; @@ -152,7 +152,7 @@ static const edma_channel_config_t adc_cfifo2_dma_config = { * @brief DMA configuration for EQADC RFIFO2. */ static const edma_channel_config_t adc_rfifo2_dma_config = { - 5, SPC5_ADC_FIFO2_DMA_PRIO, SPC5_ADC_FIFO2_DMA_IRQ_PRIO, + 5, SPC5_ADC_FIFO2_DMA_IRQ_PRIO, adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD3 }; #endif /* SPC5_ADC_USE_ADC0_Q2 */ @@ -162,7 +162,7 @@ static const edma_channel_config_t adc_rfifo2_dma_config = { * @brief DMA configuration for EQADC CFIFO3. */ static const edma_channel_config_t adc_cfifo3_dma_config = { - 6, SPC5_ADC_FIFO3_DMA_PRIO, SPC5_ADC_FIFO3_DMA_IRQ_PRIO, + 6, SPC5_ADC_FIFO3_DMA_IRQ_PRIO, NULL, adc_serve_dma_error_irq, &ADCD4 }; @@ -170,7 +170,7 @@ static const edma_channel_config_t adc_cfifo3_dma_config = { * @brief DMA configuration for EQADC RFIFO3. */ static const edma_channel_config_t adc_rfifo3_dma_config = { - 7, SPC5_ADC_FIFO3_DMA_PRIO, SPC5_ADC_FIFO3_DMA_IRQ_PRIO, + 7, SPC5_ADC_FIFO3_DMA_IRQ_PRIO, adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD4 }; #endif /* SPC5_ADC_USE_ADC1_Q3 */ @@ -180,7 +180,7 @@ static const edma_channel_config_t adc_rfifo3_dma_config = { * @brief DMA configuration for EQADC CFIFO4. */ static const edma_channel_config_t adc_cfifo4_dma_config = { - 8, SPC5_ADC_FIFO4_DMA_PRIO, SPC5_ADC_FIFO4_DMA_IRQ_PRIO, + 8, SPC5_ADC_FIFO4_DMA_IRQ_PRIO, NULL, adc_serve_dma_error_irq, &ADCD5 }; @@ -188,7 +188,7 @@ static const edma_channel_config_t adc_cfifo4_dma_config = { * @brief DMA configuration for EQADC RFIFO4. */ static const edma_channel_config_t adc_rfifo4_dma_config = { - 9, SPC5_ADC_FIFO4_DMA_PRIO, SPC5_ADC_FIFO4_DMA_IRQ_PRIO, + 9, SPC5_ADC_FIFO4_DMA_IRQ_PRIO, adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD5 }; #endif /* SPC5_ADC_USE_ADC1_Q4 */ @@ -198,7 +198,7 @@ static const edma_channel_config_t adc_rfifo4_dma_config = { * @brief DMA configuration for EQADC CFIFO5. */ static const edma_channel_config_t adc_cfifo5_dma_config = { - 10, SPC5_ADC_FIFO5_DMA_PRIO, SPC5_ADC_FIFO5_DMA_IRQ_PRIO, + 10, SPC5_ADC_FIFO5_DMA_IRQ_PRIO, NULL, adc_serve_dma_error_irq, &ADCD6 }; @@ -206,7 +206,7 @@ static const edma_channel_config_t adc_cfifo5_dma_config = { * @brief DMA configuration for EQADC RFIFO5. */ static const edma_channel_config_t adc_rfifo5_dma_config = { - 11, SPC5_ADC_FIFO5_DMA_PRIO, SPC5_ADC_FIFO5_DMA_IRQ_PRIO, + 11, SPC5_ADC_FIFO5_DMA_IRQ_PRIO, adc_serve_rfifo_irq, adc_serve_dma_error_irq, &ADCD6 }; #endif /* SPC5_ADC_USE_ADC1_Q5 */ diff --git a/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h b/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h index 5a16967ff..6be4ca5d4 100644 --- a/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h +++ b/os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h @@ -346,48 +346,6 @@ #define SPC5_ADC_USE_ADC1_Q5 FALSE #endif -/** - * @brief EQADC CFIFO0 and RFIFO0 DMA priority. - */ -#if !defined(SPC5_ADC_FIFO0_DMA_PRIO) || defined(__DOXYGEN__) -#define SPC5_ADC_FIFO0_DMA_PRIO 12 -#endif - -/** - * @brief EQADC CFIFO1 and RFIFO1 DMA priority. - */ -#if !defined(SPC5_ADC_FIFO1_DMA_PRIO) || defined(__DOXYGEN__) -#define SPC5_ADC_FIFO1_DMA_PRIO 12 -#endif - -/** - * @brief EQADC CFIFO2 and RFIFO2 DMA priority. - */ -#if !defined(SPC5_ADC_FIFO2_DMA_PRIO) || defined(__DOXYGEN__) -#define SPC5_ADC_FIFO2_DMA_PRIO 12 -#endif - -/** - * @brief EQADC CFIFO3 and RFIFO3 DMA priority. - */ -#if !defined(SPC5_ADC_FIFO3_DMA_PRIO) || defined(__DOXYGEN__) -#define SPC5_ADC_FIFO3_DMA_PRIO 12 -#endif - -/** - * @brief EQADC CFIFO4 and RFIFO4 DMA priority. - */ -#if !defined(SPC5_ADC_FIFO4_DMA_PRIO) || defined(__DOXYGEN__) -#define SPC5_ADC_FIFO4_DMA_PRIO 12 -#endif - -/** - * @brief EQADC CFIFO5 and RFIFO5 DMA priority. - */ -#if !defined(SPC5_ADC_FIFO5_DMA_PRIO) || defined(__DOXYGEN__) -#define SPC5_ADC_FIFO5_DMA_PRIO 12 -#endif - /** * @brief EQADC CFIFO0 and RFIFO0 DMA IRQ priority. */ diff --git a/testhal/SPC560Dxx/SPI/.cproject b/testhal/SPC560Dxx/SPI/.cproject new file mode 100644 index 000000000..a4ae17c6d --- /dev/null +++ b/testhal/SPC560Dxx/SPI/.cproject @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/SPC560Dxx/SPI/.project b/testhal/SPC560Dxx/SPI/.project new file mode 100644 index 000000000..7000648ab --- /dev/null +++ b/testhal/SPC560Dxx/SPI/.project @@ -0,0 +1,38 @@ + + + SPC560Dxx-SPI + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/boards/ST_EVB_SPC560D + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/SPC560Dxx/SPI/Makefile b/testhal/SPC560Dxx/SPI/Makefile new file mode 100644 index 000000000..833d3878a --- /dev/null +++ b/testhal/SPC560Dxx/SPI/Makefile @@ -0,0 +1,168 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# If enabled, this option allows to compile the application in VLE mode. +ifeq ($(USE_VLE),) + USE_VLE = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files +CHIBIOS = ../../.. +include $(CHIBIOS)/boards/ST_EVB_SPC560D/board.mk +include $(CHIBIOS)/os/hal/platforms/SPC560Dxx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/PPC/SPC560Dxx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +#include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/SPC560D40.ld + +# C sources here. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/shell.c \ + $(CHIBIOS)/os/various/chprintf.c \ + main.c + +# C++ sources here. +CPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +#MCU = e500mc -meabi -msdata=none -mnew-mnemonics -mregnames +MCU = e200zx -meabi -msdata=none -mnew-mnemonics -mregnames + +#TRGT = powerpc-eabi- +TRGT = ppc-vle- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = -D_SPC560P50L5_ + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/PPC/rules.mk diff --git a/testhal/SPC560Dxx/SPI/UDE/debug .wsx b/testhal/SPC560Dxx/SPI/UDE/debug .wsx new file mode 100644 index 000000000..b85ffdc0a --- /dev/null +++ b/testhal/SPC560Dxx/SPI/UDE/debug .wsx @@ -0,0 +1,273 @@ + + + debug .wsx001vQTv/gAAAQAXAAIA6AkIAAAABAAAAAAAPwAAAAAAAAAEAAAAAgAAAAAAAAAAAAAAAAAAAA==4.019.11.2012 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ProgramImagetrueUDE_0xD_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueResetImagetrueUDE_0xC_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueRestart ProgramImagetrueUDE_0x3_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueBreakpointsImagetrueUDE_0x6_{692DBD81-4A3F-11D2-B2CD-00A02457BF0F}trueToggle BreakImagetrueUDE_Ctrl_{FB7BC773-88A4-4ECE-B9B6-7189610B0735}_CoretrueImageAndTextfalseUDE_0x3_{1C85B31A-5D25-4197-9635-9C5DC28EAFD7}trueTrigger setupImagetrue5124914125Config ToolbarfalsetrueUDE_0x3_{D8F96613-6E55-48F7-AF2A-5FCE31D103FA}trueTarget ConfigurationImagetrueUDE_0xFE_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueConnect TargetImagetrueUDE_0x100_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueDisconnect TargetImagetrueUDE_0x6_{1C85B31A-5D25-4197-9635-9C5DC28EAFD7}trueSetup Target InterfaceImagetrueUDE_0x12_{D8F96613-6E55-48F7-AF2A-5FCE31D103FA}trueMCU Run ControlImagetrue6534915125Tools ToolbarfalsetrueUDE_Ctrl_{377CE046-823C-4A05-8828-13C25D345D77}_CoretrueImageAndTextfalseUDE_0xE1_{BE30DC4A-FD5D-47C1-994D-8CCEC8720E6E}trueExecution Time SetupImagetrue01002625Show Toolbarfalsefalse02002625Window Toolbarfalsefalse02252625Workspace Toolbarfalsefalse02752625Help Toolbarfalsefalse071712792300127923Platform Status Barfalsetrue07406431279740643..\..\..\..\..\Program Files\pls\UDE 4.0\StdLibrary.mso{866f82d3-fac5-43cd-8a82-0af01e46e2c5}669,1006,350,6610..\..\..\..\..\Documents and Settings\disiriog\My Documents\pls\UDE 4.0The script contains a collection of macros to save memory content into different file formats +and fill target memory rangesV:\UDE\AddOns\Macro\MacroLibrary\StdMacros1.dsm' +' $Header: /Ude/AddOns/Macro/MacroLibrary/StdMacros.dsm 3 30.04.04 9:34 Weisses $ +'_______________________________________________________ +' +' universal debug engine +' +' Standard command line macros - part 1 +' +' pls Development Tools 1999-2004 +' +' 28.04.04 SW correction for UDE 1.10 +' 03.06.03 SW initial version +'_______________________________________________________ + +'_______________________________________________________ +' +' UnAss command line function +' +' generates disassembly file +' +' command line UnAss output-file range1 [range2] [range3] ..... +' range description: +' C:<startaddress>,<length> or - code +' DB:<startaddress>,<length> or - data byte +' DW:<startaddress>,<length> or - data word +' DD:<startaddress>,<length> or - data dword +'_______________________________________________________ + +Sub UnAss(File,ParameterObj) + + set debugger = workspace.Coredebugger(0) + set DisASMObj = debugger.DisASMObj + If Not IsObject(ParameterObj) Then + MsgBox "Number of parameters wrong" + Exit Sub + End If + If IsNumeric(File) Then + MsgBox "File parameter wrong - " & File + Exit Sub + End If + DisASMObj.OutputPath = CStr(File) + bRetVal = DisASMObj.CreateStream(True,"UDE Disassembler output of current Program",False) + If bRetVal = True Then + ParmeterCnt = ParameterObj.ParameterCount + If ParmeterCnt = 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + If ( ParmeterCnt Mod 3 ) <> 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + RangeCnt = ParmeterCnt/3 + ParamIndex = 0 + For Range = 0 To RangeCnt -1 + KindOfRange = CStr(ParameterObj.Parameter(ParamIndex)) + KindOfRange = UCase(KindOfRange) + Address = CLng(ParameterObj.Parameter(ParamIndex +1)) + Length = CLng(ParameterObj.Parameter(ParamIndex +2)) + ParamIndex = ParamIndex +3 + If IsNumeric(KindOfRange) Then + If KindOfRange = 12 Then + DisASMObj.AddRange Address,Length,1 + ElseIf KindOfRange = 219 Then + DisASMObj.AddRange Address,Length,2 + ElseIf KindOfRange = 221 Then + DisASMObj.AddRange Address,Length,4 + Else + MsgBox "Invalid range type " & KindOfRange & "of range " & Range +1 + Exit Sub + End If + Else + If KindOfRange = "C" Then + DisASMObj.AddRange Address,Length,1 + ElseIf KindOfRange = "DB" Then + DisASMObj.AddRange Address,Length,2 + ElseIf KindOfRange = "DW" Then + DisASMObj.AddRange Address,Length,3 + ElseIf KindOfRange = "DD" Then + DisASMObj.AddRange Address,Length,4 + Else + MsgBox "Invalid range type " & KindOfRange & "of range " & Range +1 + Exit Sub + End If + End If + Next + DisASMObj.HexFileModeFlag = False + DisASMObj.ListModeFlag = False + DisASMObj.WriteAllRanges(False) + End If + +End Sub + +'_______________________________________________________ +' +' SaveHEX command line function +' +' generates intel-HEX file +' +' command line SaveHex output-file range1 [range2] [range3] ..... +' range description: +' <startaddress>,<length> +'_______________________________________________________ + +Sub SaveHEX(File,ParameterObj) + + set debugger = workspace.Coredebugger(0) + set DisASMObj = debugger.DisASMObj + If Not IsObject(ParameterObj) Then + MsgBox "Number of parameters wrong" + Exit Sub + End If + If IsNumeric(File) Then + MsgBox "File parameter wrong - " & File + Exit Sub + End If + DisASMObj.OutputPath = CStr(File) + bRetVal = DisASMObj.CreateStream(True,"UDE generated intel-Hex file of current Program",False) + If bRetVal = True Then + ParmeterCnt = ParameterObj.ParameterCount + If ParmeterCnt = 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + If ( ParmeterCnt Mod 2 ) <> 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + RangeCnt = ParmeterCnt/2 + ParamIndex = 0 + For Range = 0 To RangeCnt -1 + Address = CLng(ParameterObj.Parameter(ParamIndex)) + Length = CLng(ParameterObj.Parameter(ParamIndex +1)) + ParamIndex = ParamIndex +2 + DisASMObj.AddRange Address,Length,0 + Next + DisASMObj.HexFileModeFlag = True + DisASMObj.WriteAllRanges(False) + End If + +End Sub + +'_______________________________________________________ +' +' FillByte command line function +' +' fills memory range with byte pattern +' +' command line FillByte range1,pattern1 [range2,pattern2] [range3,pattern3] ..... +' range description: +' <startaddress>,<length> +'_______________________________________________________ + +Sub FillByte(ParameterObj) + + set debugger = workspace.Coredebugger(0) + set DisASMObj = debugger.DisASMObj + If Not IsObject(ParameterObj) Then + MsgBox "Number of parameters wrong" + Exit Sub + End If + ParmeterCnt = ParameterObj.ParameterCount + If ParmeterCnt = 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + If ( ParmeterCnt Mod 3 ) <> 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + RangeCnt = ParmeterCnt/3 + ParamIndex = 0 + set udearrayobj = debugger.ByteArrayObj(1) + For Range = 0 To RangeCnt -1 + Address = CLng(ParameterObj.Parameter(ParamIndex)) + Length = CLng(ParameterObj.Parameter(ParamIndex +1)) + Pattern = CLng(ParameterObj.Parameter(ParamIndex +2)) + ParamIndex = ParamIndex +3 + udearrayobj.Resize(Length) + udearrayobj.Fill(Pattern) + debugger.Write Address,udearrayobj + Next + +End Sub + +'_______________________________________________________ +' +' FillWord command line function +' +' fills memory range with word pattern +' +' command line FillWord range1,pattern1 [range2,pattern2] [range3,pattern3] ..... +' range description: +' <startaddress>,<length> +'_______________________________________________________ + +Sub FillWord(ParameterObj) + + set debugger = workspace.Coredebugger(0) + set DisASMObj = debugger.DisASMObj + If Not IsObject(ParameterObj) Then + MsgBox "Number of parameters wrong" + Exit Sub + End If + ParmeterCnt = ParameterObj.ParameterCount + If ParmeterCnt = 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + If ( ParmeterCnt Mod 3 ) <> 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + RangeCnt = ParmeterCnt/3 + ParamIndex = 0 + set udearrayobj = debugger.WordArrayObj(1) + For Range = 0 To RangeCnt -1 + Address = CLng(ParameterObj.Parameter(ParamIndex)) + Length = CLng(ParameterObj.Parameter(ParamIndex +1)/2) + Pattern = CLng(ParameterObj.Parameter(ParamIndex +2)) + ParamIndex = ParamIndex +3 + udearrayobj.Resize(Length) + udearrayobj.Fill(Pattern) + debugger.Write Address,udearrayobj + Next + +End Sub + +'_______________________________________________________ +' +' FillDWord command line function +' +' fills memory range with dword pattern +' +' command line FillDWord range1,pattern1 [range2,pattern2] [range3,pattern3] ..... +' range description: +' <startaddress>,<length> +'_______________________________________________________ + +Sub FillDWord(ParameterObj) + + set debugger = workspace.Coredebugger(0) + set DisASMObj = debugger.DisASMObj + If Not IsObject(ParameterObj) Then + MsgBox "Number of parameters wrong" + Exit Sub + End If + ParmeterCnt = ParameterObj.ParameterCount + If ParmeterCnt = 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + If ( ParmeterCnt Mod 3 ) <> 0 Then + MsgBox "Number of parameters wrong " & ParmeterCnt + Exit Sub + End If + RangeCnt = ParmeterCnt/3 + ParamIndex = 0 + set udearrayobj = debugger.DWordArrayObj(1) + For Range = 0 To RangeCnt -1 + Address = CLng(ParameterObj.Parameter(ParamIndex)) + Length = CLng(ParameterObj.Parameter(ParamIndex +1)/4) + Pattern = CLng(ParameterObj.Parameter(ParamIndex +2)) + ParamIndex = ParamIndex +3 + udearrayobj.Resize(Length) + udearrayobj.Fill(Pattern) + debugger.Write Address,udearrayobj + Next + +End Sub63VBScript24.11.2006 14:43:20:0001WS_CORE_DUOMacro_14_06_13_14_33_25_010Execute UnAss ..Macro UnAssExecute macro UnAss0210Execute SaveHEX ..Macro SaveHEXExecute macro SaveHEX0210Execute FillByte ..Macro FillByteExecute macro FillByte0110Execute FillWord ..Macro FillWordExecute macro FillWord0110Execute FillDWord ..Macro FillDWordExecute macro FillDWord0150121.11.2012 14:17:23:6457782750Target0.Controller0.Core1020.11.2012 16:19:48:3447782640Target0.Controller0.Core11021.11.2012 12:22:49:573..\main.c1,0,0,353,10940017372830Target0.Controller0.Core1114.06.2013 14:25:28:960..\..\..\os\hal\src\hal.c1,49,63,402,11570017372860Target0.Controller0.Core110214.06.2013 14:27:53:872..\..\..\os\hal\platforms\SPC5xx\SIUL_v1\pal_lld.c7372880Target0.Controller0.Core1121.11.2012 14:44:22:506..\..\..\os\kernel\src\chsys.c7372860Target0.Controller0.Core13121.11.2012 14:14:46:537AwAAAA==AQAAAA==kAAAAA==YAAAAA==TgAAAA==jQAAAA==TgAAAA==jQAAAA==TgAAAA==jgAAAA==AAAAAA==AAAAAA==AAAAAA==AAAAAA==7782520Target0.Controller0.Core10021.11.2012 14:10:10:4245380360007372850Target0.Controller0.Core10000000013.06.2013 16:10:26:035000013.06.2013 16:20:21:757<_ExtentX type="bin" size="8">UEoAAA==<_ExtentY type="bin" size="8">gysAAA==<_StockProps type="bin" size="8">AAAAAA==AgAAAA==UABDAAAAUABDAAAAAAAAAA==YAAAAA==RgB1AG4AYwB0AGkAbwBuAAAARgB1AG4AYwB0AGkAbwBuAAAAAAAAAA==QAYAAA==7372890Target0.Controller0.Core1OFF0..\build11..\build\ch.elf<Section>C:\ChibiStudio\chibios\os\kernel\src\chevents.c1Software;enabled;0;disabled;'main {C:\ChibiStudio\chibios\demos\PPC-SPC560D-GCC\main.c} .164';main.c;1;0;;$disabled; ;disabled; ;100111100verify.txt0000000004..\..\..\..\os\ports\GCC\PPC\chcore.c..\..\..\..\os\kernel\src\chsys.c..\..\..\..\os\hal\platforms\SPC5xx\DSPI_v1\spi_lld.c..\main.cstm_xpc560b_spc560d40_minimodule_debug_jtag.cfg14.06.2013 14:33:24:999 diff --git a/testhal/SPC560Dxx/SPI/UDE/stm_xpc560b_spc560d40_minimodule_debug_jtag.cfg b/testhal/SPC560Dxx/SPI/UDE/stm_xpc560b_spc560d40_minimodule_debug_jtag.cfg new file mode 100644 index 000000000..ca4a75aa0 --- /dev/null +++ b/testhal/SPC560Dxx/SPI/UDE/stm_xpc560b_spc560d40_minimodule_debug_jtag.cfg @@ -0,0 +1,160 @@ +[Main] +Signature=UDE_TARGINFO_2.0 +Description=STM XPC560B Mini Module with SPC560D40 (Jtag) +Description1=PLL set for 48MHz +Description2=FLASH programming prepared but not enabled +Description3=Write Filter for BAM Module +MCUs=Controller0 +Architecture=PowerPC +Vendor=STM +Board=XPC560B Mini Module + +[Controller0] +Family=PowerPC +Type=SPC560D40 +Enabled=1 +IntClock=48000 +MemDevs=BAMWriteFilter +ExtClock=8000 + +[Controller0.Core] +Protocol=PPCJTAG +Enabled=1 + +[Controller0.Core.LoadedAddOn] +UDEMemtool=1 + +[Controller0.Core.PpcJtagTargIntf] +PortType=FTDI +ResetWaitTime=50 +MaxJtagClk=2500 +DoSramInit=1 +UseNexus=1 +AdaptiveJtagPhaseShift=1 +ConnOption=Default +ChangeJtagClk=10000 +HaltAfterReset=1 +SimioAddr=g_JtagSimioAccess +FreezeTimers=1 +InvalidTlbOnReset=0 +InvalidateCache=0 +ForceCacheFlush=0 +IgnoreLockedLines=0 +ExecInitCmds=1 +JtagTapNumber=0 +JtagNumOfTaps=1 +JtagNumIrBefore=0 +JtagNumIrAfter=0 + +SimioAddr=g_JtagSimioAccess + +FlushCache=0 +AllowMmuSetup=1 +UseExtReset=1 +HandleWdtBug=0 +ForceEndOfReset=0 +JtagViaPod=0 +AllowResetOnCheck=0 +ChangeMsr=0 +ChangeMsrValue=0x0 +ExecOnStartCmds=0 +ExecOnHaltCmds=0 +TargetPort=Default +EnableProgramTimeMeasurement=0 +UseHwResetMode=0 +HandleNexusAccessBug=0 +DoNotEnableTrapSwBrp=0 +CommDevSel=PortType=USB,Type=FTDI +BootPasswd0=0xFEEDFACE +BootPasswd1=0xCAFEBEEF +BootPasswd2=0xFFFFFFFF +BootPasswd3=0xFFFFFFFF +BootPasswd4=0xFFFFFFFF +BootPasswd5=0xFFFFFFFF +BootPasswd6=0xFFFFFFFF +BootPasswd7=0xFFFFFFFF +JtagIoType=Jtag +ExecOnHaltCmdsWhileHalted=0 +TimerForPTM=Default +AllowBreakOnUpdateBreakpoints=0 +ClearDebugStatusOnHalt=1 +HwResetMode=Simulate +UseMasterNexusIfResetState=1 +UseLocalAddressTranslation=1 +Use64BitNexus=0 +InitSramOnlyWhenNotInitialized=0 +AllowHarrForUpdateDebugRegs=0 +DisableE2EECC=0 +UseCore0ForNexusMemoryAccessWhileRunning=0 + +[Controller0.Core.PpcJtagTargIntf.InitScript] +// setup IVOPR +// points to internal memory at 0x40000000 +SETSPR 0x3F 0x40000000 0xFFFFFFFF + +// disable watchdog +SET SWT_SR 0xC520 +SET SWT_SR 0xD928 +SET SWT_CR 0xFF00000A + +// Oscillator select +SET CGM_OCDS_SC 0x1000000 +SET CGM_OC_EN 0x1 + +// enable all modes +SET ME_MER 0x5FF + +// run mode +SET ME_DRUN_MC 0x1F0032 +SET ME_RUN_PC0 0xFE + +// enable peripherals in run and low power modes +SET ME_LP_PC0 0x500 + +// enable clocks +SET8 CGM_SC_DC0 0x80 +SET8 CGM_SC_DC1 0x80 +SET8 CGM_SC_DC2 0x80 + +// setup clock monitor +SET CMU_CSR 0x6 +SET CMU_LFREFR 0x1 +SET CMU_HFREFR 0xFFE + +// Make DRUN configuration active +SET ME_MCTL 0x30005AF0 +SET ME_MCTL 0x3000A50F +WAIT 0x5 + +// setup pll to 48MHz +SET FMPLL_CR 0x5300041 0xFFFFFFFF +// run mode +SET ME_DRUN_MC 0x1F00F4 + +// Make DRUN configuration active +SET ME_MCTL 0x30005AF0 +SET ME_MCTL 0x3000A50F +WAIT 0x5 + +// setup SSCM erro cfg for debug +SET16 SSCM_ERROR 0x3 0x3 + +[Controller0.BAMWriteFilter] +Description=BAM WriteAccess Filter +Range0Start=0xFFFFC000 +Range0Size=0x4000 +Enabled=1 +Handler=AccessFilter +Mode=ReadOnly + +[Controller0.PFLASH] +Enabled=1 +EnableMemtoolByDefault=1 + +[Controller0.DFLASH] +Enabled=1 +EnableMemtoolByDefault=1 + +[Controller0.Core.PpcJtagTargIntf.OnStartScript] + +[Controller0.Core.PpcJtagTargIntf.OnHaltScript] diff --git a/testhal/SPC560Dxx/SPI/chconf.h b/testhal/SPC560Dxx/SPI/chconf.h new file mode 100644 index 000000000..dc956ef13 --- /dev/null +++ b/testhal/SPC560Dxx/SPI/chconf.h @@ -0,0 +1,531 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE TRUE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC560Dxx/SPI/halconf.h b/testhal/SPC560Dxx/SPI/halconf.h new file mode 100644 index 000000000..fdc079aef --- /dev/null +++ b/testhal/SPC560Dxx/SPI/halconf.h @@ -0,0 +1,312 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/testhal/SPC560Dxx/SPI/main.c b/testhal/SPC560Dxx/SPI/main.c new file mode 100644 index 000000000..3aa7f2d7a --- /dev/null +++ b/testhal/SPC560Dxx/SPI/main.c @@ -0,0 +1,157 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +/* + * Maximum speed SPI configuration. + */ +static const SPIConfig hs_spicfg = { + NULL, + 0, + 0, + SPC5_CTAR_CSSCK_DIV2 | SPC5_CTAR_ASC_DIV2 | SPC5_CTAR_FMSZ(8) | + SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV2, /* CTAR0. */ + SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(1) /* PUSHR. */ +}; + +/* + * Low speed SPI configuration. + */ +static const SPIConfig ls_spicfg = { + NULL, + 0, + 0, + SPC5_CTAR_CSSCK_DIV64 | SPC5_CTAR_ASC_DIV64 | SPC5_CTAR_FMSZ(8) | + SPC5_CTAR_PBR_PRE2 | SPC5_CTAR_BR_DIV256, /* CTAR0. */ + SPC5_PUSHR_CONT | SPC5_PUSHR_PCS(0) /* PUSHR. */ +}; + +/* + * SPI TX and RX buffers. + */ +static uint8_t txbuf[512]; +static uint8_t rxbuf[512]; + +/* + * SPI bus contender 1. + */ +static WORKING_AREA(spi_thread_1_wa, 256); +static msg_t spi_thread_1(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 1"); + while (TRUE) { + spiAcquireBus(&SPID1); /* Acquire ownership of the bus. */ + palClearPad(PORT_E, PE_LED1); /* LED ON. */ + spiStart(&SPID1, &hs_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID1); /* Slave Select assertion. */ + spiExchange(&SPID1, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID1); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID1); /* Ownership release. */ + } + return 0; +} + +/* + * SPI bus contender 2. + */ +static WORKING_AREA(spi_thread_2_wa, 256); +static msg_t spi_thread_2(void *p) { + + (void)p; + chRegSetThreadName("SPI thread 2"); + while (TRUE) { + spiAcquireBus(&SPID1); /* Acquire ownership of the bus. */ + palSetPad(PORT_E, PE_LED1); /* LED OFF. */ + spiStart(&SPID1, &ls_spicfg); /* Setup transfer parameters. */ + spiSelect(&SPID1); /* Slave Select assertion. */ + spiExchange(&SPID1, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + spiUnselect(&SPID1); /* Slave Select de-assertion. */ + spiReleaseBus(&SPID1); /* Ownership release. */ + } + return 0; +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Prepare transmit pattern. + */ + for (i = 0; i < sizeof(txbuf); i++) + txbuf[i] = (uint8_t)i; + + /* Starting driver for test, DSPI_1 I/O pins setup.*/ + spiStart(&SPID1, &ls_spicfg); + SIU.PCR[14].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SCK */ + SIU.PCR[13].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* SOUT */ + SIU.PCR[15].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* CS[0] */ + SIU.PCR[35].R = PAL_MODE_OUTPUT_ALTERNATE(1); /* CS[1] */ + + /* Testing sending and receiving at the same time.*/ + spiExchange(&SPID1, 4, txbuf, rxbuf); + spiExchange(&SPID1, 32, txbuf, rxbuf); + spiExchange(&SPID1, 512, txbuf, rxbuf); + + /* Testing clock pulses without data buffering.*/ + spiIgnore(&SPID1, 4); + spiIgnore(&SPID1, 32); + + /* Testing sending data ignoring incoming data.*/ + spiSend(&SPID1, 4, txbuf); + spiSend(&SPID1, 32, txbuf); + + /* Testing receiving data while sending idle bits (high level).*/ + spiReceive(&SPID1, 4, rxbuf); + spiReceive(&SPID1, 32, rxbuf); + + /* Testing stop procedure.*/ + spiStop(&SPID1); + + /* + * Starting the transmitter and receiver threads. + */ + chThdCreateStatic(spi_thread_1_wa, sizeof(spi_thread_1_wa), + NORMALPRIO + 1, spi_thread_1, NULL); + chThdCreateStatic(spi_thread_2_wa, sizeof(spi_thread_2_wa), + NORMALPRIO + 1, spi_thread_2, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing. + */ + while (TRUE) { + chThdSleepMilliseconds(500); + palTogglePad(PORT_E, PE_LED2); + } + return 0; +} diff --git a/testhal/SPC560Dxx/SPI/mcuconf.h b/testhal/SPC560Dxx/SPI/mcuconf.h new file mode 100644 index 000000000..166be874b --- /dev/null +++ b/testhal/SPC560Dxx/SPI/mcuconf.h @@ -0,0 +1,230 @@ +/* + SPC5 HAL - Copyright (C) 2013 STMicroelectronics + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * SPC560B/Cxx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 1...15 Lowest...Highest. + * DMA priorities: + * 0...15 Highest...Lowest. + */ + +#define SPC560Dxx_MCUCONF + +/* + * HAL driver system settings. + */ +#define SPC5_NO_INIT FALSE +#define SPC5_ALLOW_OVERCLOCK FALSE +#define SPC5_DISABLE_WATCHDOG TRUE +#define SPC5_FMPLL0_IDF_VALUE 1 +#define SPC5_FMPLL0_NDIV_VALUE 48 +#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV8 +#define SPC5_XOSCDIV_VALUE 1 +#define SPC5_IRCDIV_VALUE 1 +#define SPC5_PERIPHERAL1_CLK_DIV_VALUE 2 +#define SPC5_PERIPHERAL2_CLK_DIV_VALUE 2 +#define SPC5_PERIPHERAL3_CLK_DIV_VALUE 2 +#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \ + SPC5_ME_ME_RUN2 | \ + SPC5_ME_ME_RUN3 | \ + SPC5_ME_ME_HALT0 | \ + SPC5_ME_ME_STOP0 | \ + SPC5_ME_ME_STANDBY0) +#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO) +#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_STANDBY0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \ + SPC5_ME_MC_IRCON | \ + SPC5_ME_MC_XOSC0ON | \ + SPC5_ME_MC_PLL0ON | \ + SPC5_ME_MC_CFLAON_NORMAL | \ + SPC5_ME_MC_DFLAON_NORMAL | \ + SPC5_ME_MC_MVRON) +#define SPC5_ME_RUN_PC0_BITS 0 +#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_TEST | \ + SPC5_ME_RUN_PC_SAFE | \ + SPC5_ME_RUN_PC_DRUN | \ + SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \ + SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \ + SPC5_ME_RUN_PC_RUN1 | \ + SPC5_ME_RUN_PC_RUN2 | \ + SPC5_ME_RUN_PC_RUN3) +#define SPC5_ME_LP_PC0_BITS 0 +#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0 | \ + SPC5_ME_LP_PC_STANDBY0) +#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0) +#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \ + SPC5_ME_LP_PC_STOP0) +#define SPC5_PIT0_IRQ_PRIORITY 4 +#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt() + +/* + * EDMA driver settings. + */ +#define SPC5_EDMA_CR_SETTING 0 +#define SPC5_EDMA_GROUP0_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_ERROR_IRQ_PRIO 2 +#define SPC5_EDMA_ERROR_HANDLER() chSysHalt() + +/* + * SERIAL driver system settings. + */ +#define SPC5_SERIAL_USE_LINFLEX0 TRUE +#define SPC5_SERIAL_USE_LINFLEX1 TRUE +#define SPC5_SERIAL_USE_LINFLEX2 TRUE +#define SPC5_SERIAL_LINFLEX0_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX1_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX2_PRIORITY 8 +#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SERIAL_LINFLEX2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SERIAL_LINFLEX2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) + +/* + * SPI driver system settings. + */ +#define SPC5_SPI_USE_DSPI0 TRUE +#define SPC5_SPI_USE_DSPI1 TRUE +#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \ + SPC5_MCR_PCSIS1 | \ + SPC5_MCR_PCSIS2 | \ + SPC5_MCR_PCSIS3 | \ + SPC5_MCR_PCSIS4 | \ + SPC5_MCR_PCSIS5 | \ + SPC5_MCR_PCSIS6 | \ + SPC5_MCR_PCSIS7) +#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 +#define SPC5_SPI_DSPI0_IRQ_PRIO 10 +#define SPC5_SPI_DSPI1_IRQ_PRIO 10 +#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt() +#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) +#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \ + SPC5_ME_PCTL_LP(2)) +#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \ + SPC5_ME_PCTL_LP(0)) diff --git a/testhal/SPC560Dxx/SPI/readme.txt b/testhal/SPC560Dxx/SPI/readme.txt new file mode 100644 index 000000000..baa32f272 --- /dev/null +++ b/testhal/SPC560Dxx/SPI/readme.txt @@ -0,0 +1,25 @@ +***************************************************************************** +** ChibiOS/RT HAL - SPI driver demo for SPC560Dxx. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an STMicroelectronics SPC560Dxx microcontroller installed on +XPC56xx EVB Motherboard. + +** The Demo ** + +The application demonstrates the use of the SPC560Dxx SPI driver. + +** Board Setup ** + +** Build Procedure ** + +The demo has been tested using HighTec compiler. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. + + http://www.st.com diff --git a/testhal/SPC560Pxx/SPI/main.c b/testhal/SPC560Pxx/SPI/main.c index 1178c7377..83ee0bbb1 100644 --- a/testhal/SPC560Pxx/SPI/main.c +++ b/testhal/SPC560Pxx/SPI/main.c @@ -57,7 +57,7 @@ static msg_t spi_thread_1(void *p) { chRegSetThreadName("SPI thread 1"); while (TRUE) { spiAcquireBus(&SPID1); /* Acquire ownership of the bus. */ - palClearPad(PORT_D, PD_LED1); /* LED ON. */ + palClearPad(PORT_D, PD_LED1); /* LED ON. */ spiStart(&SPID1, &hs_spicfg); /* Setup transfer parameters. */ spiSelect(&SPID1); /* Slave Select assertion. */ spiExchange(&SPID1, 512, @@ -78,7 +78,7 @@ static msg_t spi_thread_2(void *p) { chRegSetThreadName("SPI thread 2"); while (TRUE) { spiAcquireBus(&SPID1); /* Acquire ownership of the bus. */ - palSetPad(PORT_D, PD_LED1); /* LED OFF. */ + palSetPad(PORT_D, PD_LED1); /* LED OFF. */ spiStart(&SPID1, &ls_spicfg); /* Setup transfer parameters. */ spiSelect(&SPID1); /* Slave Select assertion. */ spiExchange(&SPID1, 512, diff --git a/testhal/SPC563Mxx/ADC/mcuconf.h b/testhal/SPC563Mxx/ADC/mcuconf.h index 49ae96bab..db7cfabb1 100644 --- a/testhal/SPC563Mxx/ADC/mcuconf.h +++ b/testhal/SPC563Mxx/ADC/mcuconf.h @@ -23,6 +23,8 @@ * * IRQ priorities: * 1...15 Lowest...Highest. + * DMA priorities: + * 0...15 Highest...Lowest. */ #define SPC563Mxx_MCUCONF @@ -44,6 +46,25 @@ BIUCR_PFLIM_ON_MISS | \ BIUCR_BFEN) +/* + * EDMA driver settings. + */ +#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP3PRI(3) | \ + EDMA_CR_GRP2PRI(2) | \ + EDMA_CR_GRP1PRI(1) | \ + EDMA_CR_GRP0PRI(0) | \ + EDMA_CR_ERGA) +#define SPC5_EDMA_GROUP0_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_GROUP1_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_GROUP2_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_GROUP3_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_ERROR_IRQ_PRIO 2 +#define SPC5_EDMA_ERROR_HANDLER() chSysHalt() + /* * ADC driver settings. */ @@ -53,12 +74,6 @@ #define SPC5_ADC_USE_ADC1_Q3 TRUE #define SPC5_ADC_USE_ADC1_Q4 TRUE #define SPC5_ADC_USE_ADC1_Q5 TRUE -#define SPC5_ADC_FIFO0_DMA_PRIO 12 -#define SPC5_ADC_FIFO1_DMA_PRIO 12 -#define SPC5_ADC_FIFO2_DMA_PRIO 12 -#define SPC5_ADC_FIFO3_DMA_PRIO 12 -#define SPC5_ADC_FIFO4_DMA_PRIO 12 -#define SPC5_ADC_FIFO5_DMA_PRIO 12 #define SPC5_ADC_FIFO0_DMA_IRQ_PRIO 12 #define SPC5_ADC_FIFO1_DMA_IRQ_PRIO 12 #define SPC5_ADC_FIFO2_DMA_IRQ_PRIO 12 @@ -104,8 +119,6 @@ SPC5_MCR_PCSIS5 | \ SPC5_MCR_PCSIS6 | \ SPC5_MCR_PCSIS7) -#define SPC5_SPI_DSPI1_DMA_PRIO 10 -#define SPC5_SPI_DSPI2_DMA_PRIO 10 #define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 #define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10 #define SPC5_SPI_DSPI1_IRQ_PRIO 10 diff --git a/testhal/SPC563Mxx/SPI/mcuconf.h b/testhal/SPC563Mxx/SPI/mcuconf.h index c96d6eea2..a06df4fdc 100644 --- a/testhal/SPC563Mxx/SPI/mcuconf.h +++ b/testhal/SPC563Mxx/SPI/mcuconf.h @@ -23,6 +23,8 @@ * * IRQ priorities: * 1...15 Lowest...Highest. + * DMA priorities: + * 0...15 Highest...Lowest. */ #define SPC563Mxx_MCUCONF @@ -44,6 +46,25 @@ BIUCR_PFLIM_ON_MISS | \ BIUCR_BFEN) +/* + * EDMA driver settings. + */ +#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP3PRI(3) | \ + EDMA_CR_GRP2PRI(2) | \ + EDMA_CR_GRP1PRI(1) | \ + EDMA_CR_GRP0PRI(0) | \ + EDMA_CR_ERGA) +#define SPC5_EDMA_GROUP0_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_GROUP1_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_GROUP2_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_GROUP3_PRIORITIES \ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +#define SPC5_EDMA_ERROR_IRQ_PRIO 2 +#define SPC5_EDMA_ERROR_HANDLER() chSysHalt() + /* * ADC driver settings. */ @@ -53,12 +74,6 @@ #define SPC5_ADC_USE_ADC1_Q3 FALSE #define SPC5_ADC_USE_ADC1_Q4 FALSE #define SPC5_ADC_USE_ADC1_Q5 FALSE -#define SPC5_ADC_FIFO0_DMA_PRIO 12 -#define SPC5_ADC_FIFO1_DMA_PRIO 12 -#define SPC5_ADC_FIFO2_DMA_PRIO 12 -#define SPC5_ADC_FIFO3_DMA_PRIO 12 -#define SPC5_ADC_FIFO4_DMA_PRIO 12 -#define SPC5_ADC_FIFO5_DMA_PRIO 12 #define SPC5_ADC_FIFO0_DMA_IRQ_PRIO 12 #define SPC5_ADC_FIFO1_DMA_IRQ_PRIO 12 #define SPC5_ADC_FIFO2_DMA_IRQ_PRIO 12 @@ -104,8 +119,6 @@ SPC5_MCR_PCSIS5 | \ SPC5_MCR_PCSIS6 | \ SPC5_MCR_PCSIS7) -#define SPC5_SPI_DSPI1_DMA_PRIO 10 -#define SPC5_SPI_DSPI2_DMA_PRIO 10 #define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10 #define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10 #define SPC5_SPI_DSPI1_IRQ_PRIO 10