diff --git a/demos/STM32/NIL-STM32H755ZI-NUCLEO144/cfg/mcuconf.h b/demos/STM32/NIL-STM32H755ZI-NUCLEO144/cfg/mcuconf.h
index ac77a100d..ded4bd3a0 100644
--- a/demos/STM32/NIL-STM32H755ZI-NUCLEO144/cfg/mcuconf.h
+++ b/demos/STM32/NIL-STM32H755ZI-NUCLEO144/cfg/mcuconf.h
@@ -39,6 +39,7 @@
 #define STM32H755_MCUCONF
 #define STM32H747_MCUCONF
 #define STM32H757_MCUCONF
+#define STM32H750_MCUCONF
 
 /*
  * General settings.
@@ -491,6 +492,7 @@
  */
 #define STM32_WSPI_USE_QUADSPI1             FALSE
 #define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
+#define STM32_WSPI_SET_CR_SSHIFT            TRUE
 #define STM32_WSPI_QUADSPI1_MDMA_CHANNEL    STM32_MDMA_CHANNEL_ID_ANY
 #define STM32_WSPI_QUADSPI1_MDMA_PRIORITY   1
 #define STM32_WSPI_MDMA_ERROR_HOOK(qspip)   osalSysHalt("MDMA failure")
diff --git a/demos/STM32/RT-STM32H743ZI_REV_XY-NUCLEO144/cfg/mcuconf.h b/demos/STM32/RT-STM32H743ZI_REV_XY-NUCLEO144/cfg/mcuconf.h
index a43cbf6d7..46d75768c 100644
--- a/demos/STM32/RT-STM32H743ZI_REV_XY-NUCLEO144/cfg/mcuconf.h
+++ b/demos/STM32/RT-STM32H743ZI_REV_XY-NUCLEO144/cfg/mcuconf.h
@@ -39,6 +39,7 @@
 #define STM32H755_MCUCONF
 #define STM32H747_MCUCONF
 #define STM32H757_MCUCONF
+#define STM32H750_MCUCONF
 
 /*
  * General settings.
@@ -491,6 +492,7 @@
  */
 #define STM32_WSPI_USE_QUADSPI1             FALSE
 #define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
+#define STM32_WSPI_SET_CR_SSHIFT            TRUE
 #define STM32_WSPI_QUADSPI1_MDMA_CHANNEL    STM32_MDMA_CHANNEL_ID_ANY
 #define STM32_WSPI_QUADSPI1_MDMA_PRIORITY   1
 #define STM32_WSPI_MDMA_ERROR_HOOK(qspip)   osalSysHalt("MDMA failure")
diff --git a/demos/STM32/RT-STM32H750XB-DISCOVERY/cfg/halconf.h b/demos/STM32/RT-STM32H750XB-DISCOVERY/cfg/halconf.h
index cdbad17f1..a2ea0b094 100644
--- a/demos/STM32/RT-STM32H750XB-DISCOVERY/cfg/halconf.h
+++ b/demos/STM32/RT-STM32H750XB-DISCOVERY/cfg/halconf.h
@@ -198,7 +198,7 @@
  * @brief   Enables the WSPI subsystem.
  */
 #if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__)
-#define HAL_USE_WSPI                        FALSE
+#define HAL_USE_WSPI                        TRUE
 #endif
 
 /*===========================================================================*/
diff --git a/demos/STM32/RT-STM32H750XB-DISCOVERY/cfg/mcuconf.h b/demos/STM32/RT-STM32H750XB-DISCOVERY/cfg/mcuconf.h
index 31aae3f5e..bc2b1c7f8 100644
--- a/demos/STM32/RT-STM32H750XB-DISCOVERY/cfg/mcuconf.h
+++ b/demos/STM32/RT-STM32H750XB-DISCOVERY/cfg/mcuconf.h
@@ -39,6 +39,7 @@
 #define STM32H755_MCUCONF
 #define STM32H747_MCUCONF
 #define STM32H757_MCUCONF
+#define STM32H750_MCUCONF
 
 /*
  * General settings.
@@ -491,6 +492,7 @@
  */
 #define STM32_WSPI_USE_QUADSPI1             FALSE
 #define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
+#define STM32_WSPI_SET_CR_SSHIFT            TRUE
 #define STM32_WSPI_QUADSPI1_MDMA_CHANNEL    STM32_MDMA_CHANNEL_ID_ANY
 #define STM32_WSPI_QUADSPI1_MDMA_PRIORITY   1
 #define STM32_WSPI_MDMA_ERROR_HOOK(qspip)   osalSysHalt("MDMA failure")
diff --git a/demos/STM32/RT-STM32H755ZI-NUCLEO144/cfg/mcuconf.h b/demos/STM32/RT-STM32H755ZI-NUCLEO144/cfg/mcuconf.h
index afa70db24..54bafcb39 100644
--- a/demos/STM32/RT-STM32H755ZI-NUCLEO144/cfg/mcuconf.h
+++ b/demos/STM32/RT-STM32H755ZI-NUCLEO144/cfg/mcuconf.h
@@ -39,6 +39,7 @@
 #define STM32H755_MCUCONF
 #define STM32H747_MCUCONF
 #define STM32H757_MCUCONF
+#define STM32H750_MCUCONF
 
 /*
  * General settings.
@@ -491,6 +492,7 @@
  */
 #define STM32_WSPI_USE_QUADSPI1             FALSE
 #define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
+#define STM32_WSPI_SET_CR_SSHIFT            TRUE
 #define STM32_WSPI_QUADSPI1_MDMA_CHANNEL    STM32_MDMA_CHANNEL_ID_ANY
 #define STM32_WSPI_QUADSPI1_MDMA_PRIORITY   1
 #define STM32_WSPI_MDMA_ERROR_HOOK(qspip)   osalSysHalt("MDMA failure")
diff --git a/os/hal/ports/STM32/LLD/QUADSPIv2/hal_wspi_lld.c b/os/hal/ports/STM32/LLD/QUADSPIv2/hal_wspi_lld.c
index 9993bc9fc..5d252d97d 100644
--- a/os/hal/ports/STM32/LLD/QUADSPIv2/hal_wspi_lld.c
+++ b/os/hal/ports/STM32/LLD/QUADSPIv2/hal_wspi_lld.c
@@ -15,7 +15,7 @@
 */
 
 /**
- * @file    QUADSPIv2//hal_wspi_lld.c
+ * @file    QUADSPIv2/hal_wspi_lld.c
  * @brief   STM32 WSPI subsystem low level driver source.
  *
  * @addtogroup WSPI
@@ -73,6 +73,13 @@ static void wspi_lld_serve_mdma_interrupt(WSPIDriver *wspip, uint32_t flags) {
   (void)wspip;
   (void)flags;
 
+  if (wspip->state == WSPI_RECEIVE) {
+    /* Portable WSPI ISR code defined in the high level driver, note, it is
+     a macro.*/
+    _wspi_isr_code(wspip);
+
+    mdmaChannelDisableX(wspip->mdma);
+  }
   /* DMA errors handling.*/
 #if defined(STM32_WSPI_MDMA_ERROR_HOOK)
   if ((flags & STM32_MDMA_CISR_TEIF) != 0) {
@@ -127,8 +134,14 @@ void wspi_lld_start(WSPIDriver *wspip) {
 
   /* WSPI setup and enable.*/
   wspip->qspi->DCR = wspip->config->dcr;
+#if STM32_WSPI_SET_CR_SSHIFT
+  wspip->qspi->CR  = ((STM32_WSPI_QUADSPI1_PRESCALER_VALUE - 1U) << 24U) |
+                      QUADSPI_CR_TCIE | QUADSPI_CR_DMAEN | QUADSPI_CR_SSHIFT |
+                      QUADSPI_CR_EN;
+#else
   wspip->qspi->CR  = ((STM32_WSPI_QUADSPI1_PRESCALER_VALUE - 1U) << 24U) |
                       QUADSPI_CR_TCIE | QUADSPI_CR_DMAEN | QUADSPI_CR_EN;
+#endif
   wspip->qspi->FCR = QUADSPI_FCR_CTEF | QUADSPI_FCR_CTCF |
                      QUADSPI_FCR_CSMF | QUADSPI_FCR_CTOF;
 }
@@ -221,14 +234,14 @@ void wspi_lld_send(WSPIDriver *wspip, const wspi_command_t *cmdp,
                   STM32_MDMA_CTCR_SINC_INC;         /* Source incremented.  */
   uint32_t ccr  = STM32_MDMA_CCR_PL(STM32_WSPI_QUADSPI1_MDMA_PRIORITY) |
                   STM32_MDMA_CCR_CTCIE          |   /* On transfer complete.*/
-                  STM32_MDMA_CCR_TCIE;              /* On transfer error.   */
+                  STM32_MDMA_CCR_TEIE;              /* On transfer error.   */
 
   /* MDMA initializations.*/
   mdmaChannelSetSourceX(wspip->mdma, txbuf);
   mdmaChannelSetDestinationX(wspip->mdma, &wspip->qspi->DR);
   mdmaChannelSetTransactionSizeX(wspip->mdma, n, 0, 0);
   mdmaChannelSetModeX(wspip->mdma, ctcr, ccr);
-  mdmaChannelSetTrigModeX(wspip->mdma, MDMA_REQUEST_QUADSPI_TC);
+  mdmaChannelSetTrigModeX(wspip->mdma, MDMA_REQUEST_QUADSPI_FIFO_TH);
 
   wspip->qspi->DLR = n - 1;
   wspip->qspi->ABR = cmdp->alt;
@@ -266,15 +279,14 @@ void wspi_lld_receive(WSPIDriver *wspip, const wspi_command_t *cmdp,
                   STM32_MDMA_CTCR_SINC_FIXED;       /* Source fixed.        */
   uint32_t ccr  = STM32_MDMA_CCR_PL(STM32_WSPI_QUADSPI1_MDMA_PRIORITY) |
                   STM32_MDMA_CCR_CTCIE          |   /* On transfer complete.*/
-                  STM32_MDMA_CCR_TCIE;              /* On transfer error.   */
+                  STM32_MDMA_CCR_TEIE;              /* On transfer error.   */
 
   /* MDMA initializations.*/
   mdmaChannelSetSourceX(wspip->mdma, &wspip->qspi->DR);
   mdmaChannelSetDestinationX(wspip->mdma, rxbuf);
   mdmaChannelSetTransactionSizeX(wspip->mdma, n, 0, 0);
   mdmaChannelSetModeX(wspip->mdma, ctcr, ccr);
-
-  mdmaChannelSetTrigModeX(wspip->mdma, MDMA_REQUEST_QUADSPI_TC);
+  mdmaChannelSetTrigModeX(wspip->mdma, MDMA_REQUEST_QUADSPI_FIFO_TH);
 
   wspip->qspi->DLR = n - 1;
   wspip->qspi->ABR = cmdp->alt;
@@ -353,11 +365,13 @@ void wspi_lld_serve_interrupt(WSPIDriver *wspip) {
   wspip->qspi->FCR = QUADSPI_FCR_CTEF | QUADSPI_FCR_CTCF |
                      QUADSPI_FCR_CSMF | QUADSPI_FCR_CTOF;
 
-  /* Portable WSPI ISR code defined in the high level driver, note, it is
+  if (wspip->state == WSPI_SEND) {
+    /* Portable WSPI ISR code defined in the high level driver, note, it is
      a macro.*/
-  _wspi_isr_code(wspip);
+    _wspi_isr_code(wspip);
 
-  mdmaChannelDisableX(wspip->mdma);
+    mdmaChannelDisableX(wspip->mdma);
+  }
 }
 
 #endif /* HAL_USE_WSPI */
diff --git a/os/hal/ports/STM32/LLD/QUADSPIv2/hal_wspi_lld.h b/os/hal/ports/STM32/LLD/QUADSPIv2/hal_wspi_lld.h
index cf9720051..929b505ec 100644
--- a/os/hal/ports/STM32/LLD/QUADSPIv2/hal_wspi_lld.h
+++ b/os/hal/ports/STM32/LLD/QUADSPIv2/hal_wspi_lld.h
@@ -149,6 +149,13 @@
 #define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
 #endif
 
+/**
+ * @brief   QUADSPI1 CR_SSHIFT enforcing.
+ */
+#if !defined(STM32_WSPI_SET_CR_SSHIFT) || defined(__DOXYGEN__)
+#define STM32_WSPI_SET_CR_SSHIFT            TRUE
+#endif
+
 /**
  * @brief   QUADSPI1 MDMA priority (0..3|lowest..highest).
  */
diff --git a/testhal/STM32/multi/ADC/cfg/stm32h743zi_nucleo144/mcuconf.h b/testhal/STM32/multi/ADC/cfg/stm32h743zi_nucleo144/mcuconf.h
index 80c66c9b8..91ed76df9 100644
--- a/testhal/STM32/multi/ADC/cfg/stm32h743zi_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/ADC/cfg/stm32h743zi_nucleo144/mcuconf.h
@@ -39,6 +39,7 @@
 #define STM32H755_MCUCONF
 #define STM32H747_MCUCONF
 #define STM32H757_MCUCONF
+#define STM32H750_MCUCONF
 
 /*
  * General settings.
@@ -491,6 +492,7 @@
  */
 #define STM32_WSPI_USE_QUADSPI1             FALSE
 #define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
+#define STM32_WSPI_SET_CR_SSHIFT            TRUE
 #define STM32_WSPI_QUADSPI1_MDMA_CHANNEL    STM32_MDMA_CHANNEL_ID_ANY
 #define STM32_WSPI_QUADSPI1_MDMA_PRIORITY   1
 #define STM32_WSPI_MDMA_ERROR_HOOK(qspip)   osalSysHalt("MDMA failure")
diff --git a/testhal/STM32/multi/DAC/cfg/stm32h743_nucleo144/mcuconf.h b/testhal/STM32/multi/DAC/cfg/stm32h743_nucleo144/mcuconf.h
index 82d6689c0..767d017ff 100644
--- a/testhal/STM32/multi/DAC/cfg/stm32h743_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/DAC/cfg/stm32h743_nucleo144/mcuconf.h
@@ -39,6 +39,7 @@
 #define STM32H755_MCUCONF
 #define STM32H747_MCUCONF
 #define STM32H757_MCUCONF
+#define STM32H750_MCUCONF
 
 /*
  * General settings.
@@ -491,6 +492,7 @@
  */
 #define STM32_WSPI_USE_QUADSPI1             FALSE
 #define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
+#define STM32_WSPI_SET_CR_SSHIFT            TRUE
 #define STM32_WSPI_QUADSPI1_MDMA_CHANNEL    STM32_MDMA_CHANNEL_ID_ANY
 #define STM32_WSPI_QUADSPI1_MDMA_PRIORITY   1
 #define STM32_WSPI_MDMA_ERROR_HOOK(qspip)   osalSysHalt("MDMA failure")
diff --git a/testhal/STM32/multi/SPI/cfg/stm32h743_nucleo144/mcuconf.h b/testhal/STM32/multi/SPI/cfg/stm32h743_nucleo144/mcuconf.h
index e39568f05..6872bf196 100644
--- a/testhal/STM32/multi/SPI/cfg/stm32h743_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/SPI/cfg/stm32h743_nucleo144/mcuconf.h
@@ -39,6 +39,7 @@
 #define STM32H755_MCUCONF
 #define STM32H747_MCUCONF
 #define STM32H757_MCUCONF
+#define STM32H750_MCUCONF
 
 /*
  * General settings.
@@ -491,6 +492,7 @@
  */
 #define STM32_WSPI_USE_QUADSPI1             FALSE
 #define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
+#define STM32_WSPI_SET_CR_SSHIFT            TRUE
 #define STM32_WSPI_QUADSPI1_MDMA_CHANNEL    STM32_MDMA_CHANNEL_ID_ANY
 #define STM32_WSPI_QUADSPI1_MDMA_PRIORITY   1
 #define STM32_WSPI_MDMA_ERROR_HOOK(qspip)   osalSysHalt("MDMA failure")
diff --git a/testhal/STM32/multi/SPI/cfg/stm32h755_nucleo144/mcuconf.h b/testhal/STM32/multi/SPI/cfg/stm32h755_nucleo144/mcuconf.h
index 713dae546..a33678de2 100644
--- a/testhal/STM32/multi/SPI/cfg/stm32h755_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/SPI/cfg/stm32h755_nucleo144/mcuconf.h
@@ -39,6 +39,7 @@
 #define STM32H755_MCUCONF
 #define STM32H747_MCUCONF
 #define STM32H757_MCUCONF
+#define STM32H750_MCUCONF
 
 /*
  * General settings.
@@ -491,6 +492,7 @@
  */
 #define STM32_WSPI_USE_QUADSPI1             FALSE
 #define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
+#define STM32_WSPI_SET_CR_SSHIFT            TRUE
 #define STM32_WSPI_QUADSPI1_MDMA_CHANNEL    STM32_MDMA_CHANNEL_ID_ANY
 #define STM32_WSPI_QUADSPI1_MDMA_PRIORITY   1
 #define STM32_WSPI_MDMA_ERROR_HOOK(qspip)   osalSysHalt("MDMA failure")
diff --git a/testhal/STM32/multi/USB_CDC/cfg/stm32h743_nucleo144/mcuconf.h b/testhal/STM32/multi/USB_CDC/cfg/stm32h743_nucleo144/mcuconf.h
index 7c85d0d64..678aeabfd 100644
--- a/testhal/STM32/multi/USB_CDC/cfg/stm32h743_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/USB_CDC/cfg/stm32h743_nucleo144/mcuconf.h
@@ -39,6 +39,7 @@
 #define STM32H755_MCUCONF
 #define STM32H747_MCUCONF
 #define STM32H757_MCUCONF
+#define STM32H750_MCUCONF
 
 /*
  * General settings.
@@ -491,6 +492,7 @@
  */
 #define STM32_WSPI_USE_QUADSPI1             FALSE
 #define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
+#define STM32_WSPI_SET_CR_SSHIFT            TRUE
 #define STM32_WSPI_QUADSPI1_MDMA_CHANNEL    STM32_MDMA_CHANNEL_ID_ANY
 #define STM32_WSPI_QUADSPI1_MDMA_PRIORITY   1
 #define STM32_WSPI_MDMA_ERROR_HOOK(qspip)   osalSysHalt("MDMA failure")
diff --git a/tools/ftl/processors/conf/mcuconf_stm32h743xx/mcuconf.h.ftl b/tools/ftl/processors/conf/mcuconf_stm32h743xx/mcuconf.h.ftl
index af4874ebf..31d35a88e 100644
--- a/tools/ftl/processors/conf/mcuconf_stm32h743xx/mcuconf.h.ftl
+++ b/tools/ftl/processors/conf/mcuconf_stm32h743xx/mcuconf.h.ftl
@@ -50,6 +50,7 @@
 #define STM32H755_MCUCONF
 #define STM32H747_MCUCONF
 #define STM32H757_MCUCONF
+#define STM32H750_MCUCONF
 
 /*
  * General settings.
@@ -502,6 +503,7 @@
  */
 #define STM32_WSPI_USE_QUADSPI1             ${doc.STM32_WSPI_USE_QUADSPI1!"FALSE"}
 #define STM32_WSPI_QUADSPI1_PRESCALER_VALUE ${doc.STM32_WSPI_QUADSPI1_PRESCALER_VALUE!"1"}
+#define STM32_WSPI_SET_CR_SSHIFT            ${doc.STM32_WSPI_SET_CR_SSHIFT!"TRUE"}
 #define STM32_WSPI_QUADSPI1_MDMA_CHANNEL    ${doc.STM32_WSPI_QUADSPI1_MDMA_CHANNEL!"STM32_MDMA_CHANNEL_ID_ANY"}
 #define STM32_WSPI_QUADSPI1_MDMA_PRIORITY   ${doc.STM32_WSPI_QUADSPI1_MDMA_PRIORITY!"1"}
 #define STM32_WSPI_MDMA_ERROR_HOOK(qspip)   ${doc.STM32_WSPI_MDMA_ERROR_HOOK!"osalSysHalt(\"MDMA failure\")"}