git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3468 35acf78f-673a-0410-8e92-d51de3d6d3f4
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gdisirio
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5649691bf9
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1297070fa9
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@ -76,22 +76,22 @@
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#define STM32_LSECLK_MIN 1000
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/**
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* @brief Maximum PLL input clock frequency.
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* @brief Maximum PLLs input clock frequency.
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*/
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#define STM32_PLLIN_MAX 2000000
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/**
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* @brief Maximum PLL input clock frequency.
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* @brief Maximum PLLs input clock frequency.
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*/
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#define STM32_PLLIN_MIN 950000
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/**
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* @brief Maximum PLLCLKOUT clock frequency.
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* @brief Maximum PLLs VCO clock frequency.
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*/
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#define STM32_PLLVCO_MAX 432000000
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/**
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* @brief Maximum PLLCLKOUT clock frequency.
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* @brief Maximum PLLs VCO clock frequency.
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*/
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#define STM32_PLLVCO_MIN 192000000
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@ -114,6 +114,11 @@
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* @brief Maximum APB2 clock frequency.
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*/
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#define STM32_PCLK2_MAX 84000000
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/**
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* @brief Maximum SPI/I2S clock frequency.
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*/
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#define STM32_SPII2S_MAX 37500000
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/** @} */
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/**
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@ -458,15 +463,8 @@
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/**
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* @brief USB clock setting.
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*/
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#if !defined(STM32_USB_CLOCK_ENABLED) || defined(__DOXYGEN__)
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#define STM32_USB_CLOCK_ENABLED TRUE
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#endif
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/**
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* @brief Enables or disables the I2S clock source.
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*/
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#if !defined(STM32_I2S_CLOCK_ENABLED) || defined(__DOXYGEN__)
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#define STM32_I2S_CLOCK_ENABLED FALSE
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#if !defined(STM32_CLOCK48_REQUIRED) || defined(__DOXYGEN__)
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#define STM32_CLOCK48_REQUIRED TRUE
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#endif
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/**
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@ -600,18 +598,11 @@
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#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
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#endif
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/**
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* @brief Enables or disables the I2S clock source.
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*/
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#if !defined(STM32_I2S_CLOCK_ENABLED) || defined(__DOXYGEN__)
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#define STM32_I2S_CLOCK_ENABLED FALSE
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#endif
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/**
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* @brief I2S clock source.
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*/
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#if !defined(STM32_I2SSRC) || defined(__DOXYGEN__)
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#define STM32_I2SSRC STM32_I2CSRC_PLLI2S
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#define STM32_I2SSRC STM32_I2CSRC_CKIN
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#endif
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/**
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@ -714,10 +705,9 @@
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#error "HSI not enabled, required by STM32_MCO2SEL"
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#endif
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#if STM32_I2S_CLOCK_ENABLED && \
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(STM32_I2SSRC == STM32_I2CSRC_PLLI2S) && \
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#if (STM32_I2SSRC == STM32_I2CSRC_PLLI2S) && \
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(STM32_PLLSRC == STM32_PLLSRC_HSI)
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#error "HSI not enabled, required by STM32_I2S_CLOCK_ENABLED and STM32_I2SSRC"
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#error "HSI not enabled, required by STM32_I2SSRC"
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#endif
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#endif /* !STM32_HSI_ENABLED */
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@ -755,10 +745,9 @@
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#error "HSE not enabled, required by STM32_MCO2SEL"
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#endif
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#if STM32_I2S_CLOCK_ENABLED && \
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(STM32_I2SSRC == STM32_I2CSRC_PLLI2S) && \
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#if (STM32_I2SSRC == STM32_I2CSRC_PLLI2S) && \
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(STM32_PLLSRC == STM32_PLLSRC_HSE)
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#error "HSE not enabled, required by STM32_I2S_CLOCK_ENABLED and STM32_I2SSRC"
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#error "HSE not enabled, required by STM32_I2SSRC"
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#endif
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#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
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@ -800,10 +789,38 @@
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#endif /* !#if STM32_LSE_ENABLED */
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/*
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* PLL related checks.
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/**
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* @brief STM32_PLLM field.
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*/
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#if STM32_USB_CLOCK_ENABLED || \
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#if ((STM32_PLLM_VALUE >= 2) && (STM32_PLLM_VALUE <= 63)) || \
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defined(__DOXYGEN__)
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#define STM32_PLLM (STM32_PLLM_VALUE << 0)
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#else
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#error "invalid STM32_PLLM_VALUE value specified"
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#endif
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/**
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* @brief PLLs input clock frequency.
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*/
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#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
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#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE)
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#elif STM32_PLLSRC == STM32_PLLSRC_HSI
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#define STM32_PLLCLKIN (STM32_HSICLK / STM32_PLLM_VALUE)
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#else
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#error "invalid STM32_PLLSRC value specified"
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#endif
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/*
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* PLLs input frequency range check.
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*/
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#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
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#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
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#endif
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/*
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* PLL enable check.
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*/
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#if STM32_CLOCK48_REQUIRED || \
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(STM32_SW == STM32_SW_PLL) || \
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(STM32_MCO1SEL == STM32_MCO1SEL_PLL) || \
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(STM32_MCO2SEL == STM32_MCO2SEL_PLL) || \
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@ -816,16 +833,6 @@
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#define STM32_ACTIVATE_PLL FALSE
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#endif
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/**
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* @brief STM32_PLLM field.
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*/
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#if ((STM32_PLLM_VALUE >= 2) && (STM32_PLLM_VALUE <= 63)) || \
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defined(__DOXYGEN__)
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#define STM32_PLLM (STM32_PLLM_VALUE << 0)
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#else
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#error "invalid STM32_PLLM_VALUE value specified"
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#endif
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/**
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* @brief STM32_PLLN field.
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*/
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@ -854,39 +861,22 @@
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/**
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* @brief STM32_PLLQ field.
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*/
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#if ((STM32_PLLQ_VALUE >= 4) && (STM32_PLLQ_VALUE <= 15)) || \
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#if ((STM32_PLLQ_VALUE >= 4) && (STM32_PLLQ_VALUE <= 15)) || \
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defined(__DOXYGEN__)
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#define STM32_PLLQ (STM32_PLLQ_VALUE << 24)
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#else
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#error "invalid STM32_PLLQ_VALUE value specified"
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#endif
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/**
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* @brief PLL input clock frequency.
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*/
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#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
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#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE)
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#elif STM32_PLLSRC == STM32_PLLSRC_HSI
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#define STM32_PLLCLKIN (STM32_HSICLK / STM32_PLLM_VALUE)
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#else
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#error "invalid STM32_PLLSRC value specified"
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#endif
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/* PLL input frequency range check.*/
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#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
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#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
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#endif
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/**
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* @brief PLL VCO frequency.
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*/
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#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLN_VALUE)
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#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLN_VALUE)
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/*
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* PLL output frequency range check.
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* PLL VCO frequency range check.
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*/
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#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX)
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#error STM32_PLLVCO
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#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
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#endif
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@ -895,7 +885,9 @@
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*/
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#define STM32_PLLCLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE)
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/* PLL output frequency range check.*/
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/*
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* PLL output frequency range check.
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*/
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#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
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#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
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#endif
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@ -1000,14 +992,61 @@
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#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
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#endif
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/**
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* @brief RTC frequency.
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/*
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* PLLI2S enable check.
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*/
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#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \
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defined(__DOXYGEN__)
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#define STM32_RTCPRE (STM32_RTCPRE_VALUE << 16)
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#if (STM32_I2CSRC == STM32_I2CSRC_PLLI2S) || defined(__DOXYGEN__)
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/**
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* @brief PLL activation flag.
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*/
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#define STM32_ACTIVATE_PLLI2S TRUE
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#else
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#error "invalid STM32_RTCPRE value specified"
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#define STM32_ACTIVATE_PLLI2S FALSE
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#endif
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/**
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* @brief STM32_PLLI2SN field.
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*/
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#if ((STM32_PLLI2SN_VALUE >= 192) && (STM32_PLLI2SN_VALUE <= 432)) || \
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defined(__DOXYGEN__)
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#define STM32_PLLI2SN (STM32_PLLI2SN_VALUE << 6)
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#else
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#error "invalid STM32_PLLI2SN_VALUE value specified"
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#endif
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/**
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* @brief STM32_PLLI2SR field.
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*/
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#if ((STM32_PLLI2SR_VALUE >= 2) && (STM32_PLLI2SR_VALUE <= 7)) || \
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defined(__DOXYGEN__)
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#define STM32_PLLI2SR (STM32_PLLI2SR_VALUE << 28)
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#else
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#error "invalid STM32_PLLI2SR_VALUE value specified"
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#endif
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/**
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* @brief PLL VCO frequency.
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*/
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#define STM32_PLLI2SVCO (STM32_PLLCLKIN * STM32_PLLI2SN_VALUE)
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/*
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* PLLI2S VCO frequency range check.
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*/
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#if (STM32_PLLI2SVCO < STM32_PLLVCO_MIN) || \
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(STM32_PLLI2SVCO > STM32_PLLVCO_MAX)
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#error "STM32_PLLI2SVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
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#endif
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/**
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* @brief PLLI2S output clock frequency.
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*/
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#define STM32_PLLI2SCLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SR)
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/*
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* PLLI2S output frequency range check.
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*/
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#if STM32_PLLI2SCLKOUT > STM32_SPII2S_MAX
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#error "STM32_PLLI2SCLKOUT outside acceptable range (STM32_SPII2S_MAX)"
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#endif
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/**
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@ -1084,6 +1123,16 @@
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#error "invalid STM32_RTCPRE value specified"
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#endif
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/**
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* @brief RTC HSE divider setting.
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*/
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#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \
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defined(__DOXYGEN__)
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#define STM32_RTCPRE (STM32_RTCPRE_VALUE << 16)
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#else
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#error "invalid STM32_RTCPRE value specified"
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#endif
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/**
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* @brief RTC clock.
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*/
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@ -1100,9 +1149,13 @@
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#endif
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/**
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* @brief OTG frequency.
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* @brief 48MHz frequency.
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*/
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#define STM32_OTGFSCLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
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#if STM32_CLOCK48_REQUIRED || defined(__DOXYGEN__)
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#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
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#else
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#define STM32_PLL48CLK 0
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#endif
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/**
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* @brief Timers 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14 clock.
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@ -1156,7 +1209,7 @@
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/*===========================================================================*/
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/* STM32 DMA support code.*/
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//#include "stm32_dma.h"
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#include "stm32_dma.h"
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#ifdef __cplusplus
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extern "C" {
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