git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7347 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio
parent
0ec45cc00d
commit
130db5dfc5
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@ -0,0 +1,30 @@
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/*
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ChibiOS - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012,2013,2014 Giovanni Di Sirio.
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This file is part of ChibiOS.
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ChibiOS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* STM32F401xE memory setup.
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*/
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MEMORY
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{
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flash : org = 0x08000000, len = 512k
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ram : org = 0x20000000, len = 96k
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}
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INCLUDE rules.ld
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@ -45,29 +45,11 @@
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#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \
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RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIOFEN)
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#elif defined(STM32F2XX)
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#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \
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RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \
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RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | \
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RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \
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RCC_AHB1ENR_GPIOIEN)
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#define AHB1_LPEN_MASK AHB1_EN_MASK
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#elif defined(STM32F3XX) || defined(STM32F37X)
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#define AHB_EN_MASK STM32_GPIO_EN_MASK
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#elif defined(STM32F4XX)
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#if STM32_HAS_GPIOF && STM32_HAS_GPIOG && STM32_HAS_GPIOI
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#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \
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RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \
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RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | \
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RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \
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RCC_AHB1ENR_GPIOIEN)
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#else
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#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \
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RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \
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RCC_AHB1ENR_GPIOEEN)
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#endif /* STM32_HAS_GPIOF && STM32_HAS_GPIOG && STM32_HAS_GPIOI */
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#elif defined(STM32F2XX) || defined(STM32F4XX)
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#define AHB1_EN_MASK STM32_GPIO_EN_MASK
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#define AHB1_LPEN_MASK AHB1_EN_MASK
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#else
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@ -41,6 +41,8 @@
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#ifndef _HAL_LLD_H_
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#define _HAL_LLD_H_
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#include "stm32_registry.h"
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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@ -56,47 +58,36 @@
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*/
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#if defined(STM32F439xx) || defined(__DOXYGEN__)
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#define PLATFORM_NAME "STM32F439 High Performance with DSP and FPU"
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#define STM32F429_439xx
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#elif defined(STM32F429xx)
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#define PLATFORM_NAME "STM32F429 High Performance with DSP and FPU"
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#define STM32F429_439xx
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#elif defined(STM32F437xx)
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#define PLATFORM_NAME "STM32F437 High Performance with DSP and FPU"
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#define STM32F427_437xx
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#elif defined(STM32F427xx)
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#define PLATFORM_NAME "STM32F427 High Performance with DSP and FPU"
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#define STM32F427_437xx
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#elif defined(STM32F405xx)
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#define PLATFORM_NAME "STM32F405 High Performance with DSP and FPU"
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#define STM32F40_41xxx
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#elif defined(STM32F415xx)
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#define PLATFORM_NAME "STM32F415 High Performance with DSP and FPU"
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#define STM32F40_41xxx
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#elif defined(STM32F407xx)
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#define PLATFORM_NAME "STM32F407 High Performance with DSP and FPU"
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#define STM32F40_41xxx
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#elif defined(STM32F417xx)
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#define PLATFORM_NAME "STM32F417 High Performance with DSP and FPU"
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#define STM32F40_41xxx
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#elif defined(STM32F401xC)
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#define PLATFORM_NAME "STM32F401xC High Performance with DSP and FPU"
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#define STM32F401xx
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#elif defined(STM32F401xE)
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#define PLATFORM_NAME "STM32F401xE High Performance with DSP and FPU"
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#define STM32F401xx
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#elif defined(STM32F411xE)
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#define PLATFORM_NAME "STM32F411xE High Performance with DSP and FPU"
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#define STM32F411xx
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#elif defined(STM32F2XX)
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#define PLATFORM_NAME "STM32F2xx High Performance"
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@ -104,13 +95,6 @@
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#else
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#error "STM32F2xx/F4xx device not specified"
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#endif
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/**
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* @brief Sub-family identifier.
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*/
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#if !defined(STM32F4XX) || defined(__DOXYGEN__)
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#define STM32F4XX
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#endif
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/** @} */
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/**
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@ -1417,7 +1401,6 @@
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/* Various helpers.*/
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#include "nvic.h"
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#include "stm32_registry.h"
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#include "stm32_isr.h"
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#include "stm32_dma.h"
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#include "stm32_rcc.h"
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@ -25,6 +25,36 @@
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#ifndef _STM32_REGISTRY_H_
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#define _STM32_REGISTRY_H_
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#if defined(STM32F439xx) || defined(STM32F429xx)
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#define STM32F429_439xx
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#elif defined(STM32F437xx) || defined(STM32F427xx)
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#define STM32F427_437xx
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#elif defined(STM32F405xx) || defined(STM32F415xx) || \
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defined(STM32F407xx) || defined(STM32F417xx)
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#define STM32F40_41xxx
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#elif defined(STM32F401xC) || defined(STM32F401xE)
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#define STM32F401xx
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#elif defined(STM32F411xE)
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#define STM32F411xx
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#elif defined(STM32F2XX)
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#else
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#error "STM32F2xx/F4xx device not specified"
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#endif
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/**
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* @brief Sub-family identifier.
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*/
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#if !defined(STM32F4XX) || defined(__DOXYGEN__)
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#define STM32F4XX
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#endif
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/*===========================================================================*/
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/* Platform capabilities. */
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/*===========================================================================*/
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* @name STM32F4xx capabilities
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* @{
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*/
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/*===========================================================================*/
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/* STM32F439xx, STM32F429xx, STM32F437xx, STM32F427xx. */
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/*===========================================================================*/
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#if defined(STM32F429_439xx) || defined(STM32F427_437xx)
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
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@ -70,11 +104,7 @@
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#define STM32_HAS_DMA2 TRUE
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/* ETH attributes.*/
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#if !defined(STM32F401xx)
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#define STM32_HAS_ETH TRUE
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#else /* defined(STM32F401xx) */
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#define STM32_HAS_ETH FALSE
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#endif /* defined(STM32F401xx) */
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/* EXTI attributes.*/
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#define STM32_EXTI_NUM_CHANNELS 23
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@ -86,15 +116,18 @@
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOH TRUE
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#if !defined(STM32F401xx)
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG TRUE
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#define STM32_HAS_GPIOI TRUE
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#else /* defined(STM32F401xx) */
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#define STM32_HAS_GPIOF FALSE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOI FALSE
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#endif /* defined(STM32F401xx) */
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#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
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RCC_AHB1ENR_GPIOBEN | \
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RCC_AHB1ENR_GPIOCEN | \
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RCC_AHB1ENR_GPIODEN | \
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RCC_AHB1ENR_GPIOEEN | \
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RCC_AHB1ENR_GPIOFEN | \
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RCC_AHB1ENR_GPIOGEN | \
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RCC_AHB1ENR_GPIOHEN | \
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RCC_AHB1ENR_GPIOIEN)
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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/* RTC attributes.*/
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#define STM32_HAS_RTC TRUE
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#if defined(STM32F4XX) || defined(__DOXYGEN__)
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#define STM32_RTC_HAS_SUBSECONDS TRUE
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#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
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#define STM32_RTC_NUM_ALARMS 2
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#define STM32_RTC_HAS_INTERRUPTS FALSE
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/* SDIO attributes.*/
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#define STM32_HAS_SDIO TRUE
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#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
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STM32_DMA_STREAM_ID_MSK(2, 6))
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#define STM32_SDC_SDIO_DMA_CHN 0x04004000
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/* SPI attributes.*/
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#define STM32_HAS_SPI1 TRUE
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#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
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STM32_DMA_STREAM_ID_MSK(2, 2))
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#define STM32_SPI1_RX_DMA_CHN 0x00000303
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#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
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STM32_DMA_STREAM_ID_MSK(2, 5))
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#define STM32_SPI1_TX_DMA_CHN 0x00303000
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#define STM32_HAS_SPI2 TRUE
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#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
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#define STM32_SPI2_RX_DMA_CHN 0x00000000
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#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
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#define STM32_SPI2_TX_DMA_CHN 0x00000000
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#define STM32_HAS_SPI3 TRUE
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#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
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STM32_DMA_STREAM_ID_MSK(1, 2))
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#define STM32_SPI3_RX_DMA_CHN 0x00000000
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#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
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STM32_DMA_STREAM_ID_MSK(1, 7))
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#define STM32_SPI3_TX_DMA_CHN 0x00000000
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#define STM32_HAS_SPI4 TRUE
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#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
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STM32_DMA_STREAM_ID_MSK(2, 3))
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#define STM32_SPI4_RX_DMA_CHN 0x00005004
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#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
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STM32_DMA_STREAM_ID_MSK(2, 4))
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#define STM32_SPI4_TX_DMA_CHN 0x00050040
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#define STM32_HAS_SPI5 TRUE
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#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) | \
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STM32_DMA_STREAM_ID_MSK(2, 5))
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#define STM32_SPI5_RX_DMA_CHN 0x00702000
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#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) | \
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STM32_DMA_STREAM_ID_MSK(2, 6))
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#define STM32_SPI5_TX_DMA_CHN 0x07020000
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#define STM32_HAS_SPI6 TRUE
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#define STM32_SPI6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6))
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#define STM32_SPI6_RX_DMA_CHN 0x01000000
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#define STM32_SPI6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
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#define STM32_SPI6_TX_DMA_CHN 0x00100000
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/* TIM attributes.*/
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#define STM32_TIM_MAX_CHANNELS 4
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#define STM32_HAS_TIM1 TRUE
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#define STM32_TIM1_IS_32BITS FALSE
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#define STM32_TIM1_CHANNELS 4
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#define STM32_HAS_TIM2 TRUE
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#define STM32_TIM2_IS_32BITS TRUE
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#define STM32_TIM2_CHANNELS 4
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#define STM32_HAS_TIM3 TRUE
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#define STM32_TIM3_IS_32BITS FALSE
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#define STM32_TIM3_CHANNELS 4
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#define STM32_HAS_TIM4 TRUE
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#define STM32_TIM4_IS_32BITS FALSE
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#define STM32_TIM4_CHANNELS 4
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#define STM32_HAS_TIM5 TRUE
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#define STM32_TIM5_IS_32BITS TRUE
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#define STM32_TIM5_CHANNELS 4
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#define STM32_HAS_TIM6 TRUE
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#define STM32_TIM6_IS_32BITS FALSE
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#define STM32_TIM6_CHANNELS 0
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#define STM32_HAS_TIM7 TRUE
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#define STM32_TIM7_IS_32BITS FALSE
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#define STM32_TIM7_CHANNELS 0
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#define STM32_HAS_TIM8 TRUE
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#define STM32_TIM8_IS_32BITS FALSE
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#define STM32_TIM8_CHANNELS 6
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#define STM32_HAS_TIM9 TRUE
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#define STM32_TIM9_IS_32BITS FALSE
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#define STM32_TIM9_CHANNELS 2
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#define STM32_HAS_TIM10 TRUE
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#define STM32_TIM10_IS_32BITS FALSE
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#define STM32_TIM10_CHANNELS 2
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#define STM32_HAS_TIM11 TRUE
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#define STM32_TIM11_IS_32BITS FALSE
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#define STM32_TIM11_CHANNELS 2
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#define STM32_HAS_TIM12 TRUE
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#define STM32_TIM12_IS_32BITS FALSE
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#define STM32_TIM12_CHANNELS 2
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#define STM32_HAS_TIM13 TRUE
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#define STM32_TIM13_IS_32BITS FALSE
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#define STM32_TIM13_CHANNELS 2
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#define STM32_HAS_TIM14 TRUE
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#define STM32_TIM14_IS_32BITS FALSE
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#define STM32_TIM14_CHANNELS 2
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#define STM32_HAS_TIM15 FALSE
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#define STM32_HAS_TIM16 FALSE
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#define STM32_HAS_TIM17 FALSE
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#define STM32_HAS_TIM18 FALSE
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#define STM32_HAS_TIM19 FALSE
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/* USART attributes.*/
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#define STM32_HAS_USART1 TRUE
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#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
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STM32_DMA_STREAM_ID_MSK(2, 5))
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#define STM32_USART1_RX_DMA_CHN 0x00400400
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#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
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#define STM32_USART1_TX_DMA_CHN 0x40000000
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#define STM32_HAS_USART2 TRUE
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#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
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#define STM32_USART2_RX_DMA_CHN 0x00400000
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#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
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#define STM32_USART2_TX_DMA_CHN 0x04000000
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#define STM32_HAS_USART3 TRUE
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#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
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#define STM32_USART3_RX_DMA_CHN 0x00000040
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#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
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STM32_DMA_STREAM_ID_MSK(1, 4))
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#define STM32_USART3_TX_DMA_CHN 0x00074000
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#define STM32_HAS_UART4 TRUE
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#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
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#define STM32_UART4_RX_DMA_CHN 0x00000400
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#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
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#define STM32_UART4_TX_DMA_CHN 0x00040000
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#define STM32_HAS_UART5 TRUE
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#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 0)
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#define STM32_UART5_RX_DMA_CHN 0x00000004
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#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
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#define STM32_UART5_TX_DMA_CHN 0x40000000
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#define STM32_HAS_USART6 TRUE
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#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
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STM32_DMA_STREAM_ID_MSK(2, 2))
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#define STM32_USART6_RX_DMA_CHN 0x00000550
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#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
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STM32_DMA_STREAM_ID_MSK(2, 7))
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#define STM32_USART6_TX_DMA_CHN 0x55000000
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/* USB attributes.*/
|
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#define STM32_HAS_USB FALSE
|
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#define STM32_HAS_OTG1 TRUE
|
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#define STM32_HAS_OTG2 TRUE
|
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/* FSMC attributes.*/
|
||||
#define STM32_HAS_FSMC TRUE
|
||||
#define STM32_FSMC_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 1) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 2) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 3) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 4) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 5) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 6) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 7))
|
||||
#define STM32_FSMC_DMA_CHN 0x03010201
|
||||
#endif /* defined(STM32F429_439xx) || defined(STM32F427_437xx) */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* STM32F405xx, STM32F415xx, STM32F407xx, STM32F417xx, STM32F2XX. */
|
||||
/*===========================================================================*/
|
||||
#if defined(STM32F40_41xxx) || defined(STM32F2XX)
|
||||
/* ADC attributes.*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 4))
|
||||
#define STM32_ADC1_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_ADC2 TRUE
|
||||
#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 3))
|
||||
#define STM32_ADC2_DMA_CHN 0x00001100
|
||||
|
||||
#define STM32_HAS_ADC3 TRUE
|
||||
#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 1))
|
||||
#define STM32_ADC3_DMA_CHN 0x00000022
|
||||
|
||||
#define STM32_HAS_ADC4 FALSE
|
||||
|
||||
#define STM32_HAS_SDADC1 FALSE
|
||||
#define STM32_HAS_SDADC2 FALSE
|
||||
#define STM32_HAS_SDADC3 FALSE
|
||||
|
||||
/* CAN attributes.*/
|
||||
#define STM32_HAS_CAN1 TRUE
|
||||
#define STM32_HAS_CAN2 TRUE
|
||||
#define STM32_CAN_MAX_FILTERS 28
|
||||
|
||||
/* DAC attributes.*/
|
||||
#define STM32_HAS_DAC1 FALSE
|
||||
#define STM32_HAS_DAC2 FALSE
|
||||
|
||||
/* DMA attributes.*/
|
||||
#define STM32_ADVANCED_DMA TRUE
|
||||
#define STM32_HAS_DMA1 TRUE
|
||||
#define STM32_HAS_DMA2 TRUE
|
||||
|
||||
/* ETH attributes.*/
|
||||
#define STM32_HAS_ETH TRUE
|
||||
|
||||
/* EXTI attributes.*/
|
||||
#define STM32_EXTI_NUM_CHANNELS 23
|
||||
|
||||
/* GPIO attributes.*/
|
||||
#define STM32_HAS_GPIOA TRUE
|
||||
#define STM32_HAS_GPIOB TRUE
|
||||
#define STM32_HAS_GPIOC TRUE
|
||||
#define STM32_HAS_GPIOD TRUE
|
||||
#define STM32_HAS_GPIOE TRUE
|
||||
#define STM32_HAS_GPIOH TRUE
|
||||
#define STM32_HAS_GPIOF TRUE
|
||||
#define STM32_HAS_GPIOG TRUE
|
||||
#define STM32_HAS_GPIOI TRUE
|
||||
#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
|
||||
RCC_AHB1ENR_GPIOBEN | \
|
||||
RCC_AHB1ENR_GPIOCEN | \
|
||||
RCC_AHB1ENR_GPIODEN | \
|
||||
RCC_AHB1ENR_GPIOEEN | \
|
||||
RCC_AHB1ENR_GPIOFEN | \
|
||||
RCC_AHB1ENR_GPIOGEN | \
|
||||
RCC_AHB1ENR_GPIOHEN | \
|
||||
RCC_AHB1ENR_GPIOIEN)
|
||||
|
||||
/* I2C attributes.*/
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 5))
|
||||
#define STM32_I2C1_RX_DMA_CHN 0x00100001
|
||||
#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 6))
|
||||
#define STM32_I2C1_TX_DMA_CHN 0x11000000
|
||||
|
||||
#define STM32_HAS_I2C2 TRUE
|
||||
#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 3))
|
||||
#define STM32_I2C2_RX_DMA_CHN 0x00007700
|
||||
#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
|
||||
#define STM32_I2C2_TX_DMA_CHN 0x70000000
|
||||
|
||||
#define STM32_HAS_I2C3 TRUE
|
||||
#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
||||
#define STM32_I2C3_RX_DMA_CHN 0x00000300
|
||||
#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
||||
#define STM32_I2C3_TX_DMA_CHN 0x00030000
|
||||
|
||||
/* RTC attributes.*/
|
||||
#define STM32_HAS_RTC TRUE
|
||||
#if !defined(STM32F2XX)
|
||||
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
||||
#else
|
||||
#define STM32_RTC_HAS_SUBSECONDS FALSE
|
||||
|
|
@ -158,39 +461,9 @@
|
|||
STM32_DMA_STREAM_ID_MSK(1, 7))
|
||||
#define STM32_SPI3_TX_DMA_CHN 0x00000000
|
||||
|
||||
#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || \
|
||||
defined(STM32F401xx)
|
||||
#define STM32_HAS_SPI4 TRUE
|
||||
#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 3))
|
||||
#define STM32_SPI4_RX_DMA_CHN 0x00005004
|
||||
#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 4))
|
||||
#define STM32_SPI4_TX_DMA_CHN 0x00050040
|
||||
#else
|
||||
#define STM32_HAS_SPI4 FALSE
|
||||
#endif
|
||||
|
||||
#if defined(STM32F427_437xx) || defined(STM32F429_439xx)
|
||||
#define STM32_HAS_SPI5 TRUE
|
||||
#define STM32_SPI5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) | \
|
||||
STM32_DMA_STREAM_ID_MSK(2, 5))
|
||||
#define STM32_SPI5_RX_DMA_CHN 0x00702000
|
||||
#define STM32_SPI5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) | \
|
||||
STM32_DMA_STREAM_ID_MSK(2, 6))
|
||||
#define STM32_SPI5_TX_DMA_CHN 0x07020000
|
||||
|
||||
#define STM32_HAS_SPI6 TRUE
|
||||
#define STM32_SPI6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6))
|
||||
#define STM32_SPI6_RX_DMA_CHN 0x01000000
|
||||
#define STM32_SPI6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
|
||||
#define STM32_SPI6_TX_DMA_CHN 0x00100000
|
||||
|
||||
#else /* !(defined(STM32F427_437xx) || defined(STM32F429_439xx)) */
|
||||
#define STM32_HAS_SPI4 FALSE
|
||||
#define STM32_HAS_SPI5 FALSE
|
||||
#define STM32_HAS_SPI6 FALSE
|
||||
#endif /* !(defined(STM32F427_437xx) || defined(STM32F429_439xx)) */
|
||||
|
||||
/* TIM attributes.*/
|
||||
#define STM32_TIM_MAX_CHANNELS 4
|
||||
|
|
@ -215,7 +488,6 @@
|
|||
#define STM32_TIM5_IS_32BITS TRUE
|
||||
#define STM32_TIM5_CHANNELS 4
|
||||
|
||||
#if !defined(STM32F401xx)
|
||||
#define STM32_HAS_TIM6 TRUE
|
||||
#define STM32_TIM6_IS_32BITS FALSE
|
||||
#define STM32_TIM6_CHANNELS 0
|
||||
|
|
@ -228,12 +500,6 @@
|
|||
#define STM32_TIM8_IS_32BITS FALSE
|
||||
#define STM32_TIM8_CHANNELS 6
|
||||
|
||||
#else /* defined(STM32F401xx) */
|
||||
#define STM32_HAS_TIM6 FALSE
|
||||
#define STM32_HAS_TIM7 FALSE
|
||||
#define STM32_HAS_TIM8 FALSE
|
||||
#endif /* defined(STM32F401xx) */
|
||||
|
||||
#define STM32_HAS_TIM9 TRUE
|
||||
#define STM32_TIM9_IS_32BITS FALSE
|
||||
#define STM32_TIM9_CHANNELS 2
|
||||
|
|
@ -246,7 +512,6 @@
|
|||
#define STM32_TIM11_IS_32BITS FALSE
|
||||
#define STM32_TIM11_CHANNELS 2
|
||||
|
||||
#if !defined(STM32F401xx)
|
||||
#define STM32_HAS_TIM12 TRUE
|
||||
#define STM32_TIM12_IS_32BITS FALSE
|
||||
#define STM32_TIM12_CHANNELS 2
|
||||
|
|
@ -259,12 +524,6 @@
|
|||
#define STM32_TIM14_IS_32BITS FALSE
|
||||
#define STM32_TIM14_CHANNELS 2
|
||||
|
||||
#else /* defined(STM32F401xx) */
|
||||
#define STM32_HAS_TIM12 FALSE
|
||||
#define STM32_HAS_TIM13 FALSE
|
||||
#define STM32_HAS_TIM14 FALSE
|
||||
#endif /* defined(STM32F401xx) */
|
||||
|
||||
#define STM32_HAS_TIM15 FALSE
|
||||
#define STM32_HAS_TIM16 FALSE
|
||||
#define STM32_HAS_TIM17 FALSE
|
||||
|
|
@ -285,7 +544,6 @@
|
|||
#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
|
||||
#define STM32_USART2_TX_DMA_CHN 0x04000000
|
||||
|
||||
#if !defined(STM32F401xx)
|
||||
#define STM32_HAS_USART3 TRUE
|
||||
#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 1)
|
||||
#define STM32_USART3_RX_DMA_CHN 0x00000040
|
||||
|
|
@ -305,11 +563,227 @@
|
|||
#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
|
||||
#define STM32_UART5_TX_DMA_CHN 0x40000000
|
||||
|
||||
#else /* defined(STM32F401xx) */
|
||||
#define STM32_HAS_USART6 TRUE
|
||||
#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 2))
|
||||
#define STM32_USART6_RX_DMA_CHN 0x00000550
|
||||
#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 6) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 7))
|
||||
#define STM32_USART6_TX_DMA_CHN 0x55000000
|
||||
|
||||
/* USB attributes.*/
|
||||
#define STM32_HAS_USB FALSE
|
||||
#define STM32_HAS_OTG1 TRUE
|
||||
#define STM32_HAS_OTG2 TRUE
|
||||
|
||||
/* FSMC attributes.*/
|
||||
#define STM32_HAS_FSMC TRUE
|
||||
#define STM32_FSMC_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 1) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 2) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 3) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 4) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 5) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 6) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 7))
|
||||
#define STM32_FSMC_DMA_CHN 0x03010201
|
||||
#endif /* defined(STM32F40_41xxx) || defined(STM32F2XX) */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* STM32F401xx. */
|
||||
/*===========================================================================*/
|
||||
#if defined(STM32F401xx)
|
||||
/* ADC attributes.*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 4))
|
||||
#define STM32_ADC1_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_ADC2 TRUE
|
||||
#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 3))
|
||||
#define STM32_ADC2_DMA_CHN 0x00001100
|
||||
|
||||
#define STM32_HAS_ADC3 TRUE
|
||||
#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 1))
|
||||
#define STM32_ADC3_DMA_CHN 0x00000022
|
||||
|
||||
#define STM32_HAS_ADC4 FALSE
|
||||
|
||||
#define STM32_HAS_SDADC1 FALSE
|
||||
#define STM32_HAS_SDADC2 FALSE
|
||||
#define STM32_HAS_SDADC3 FALSE
|
||||
|
||||
/* CAN attributes.*/
|
||||
#define STM32_HAS_CAN1 TRUE
|
||||
#define STM32_HAS_CAN2 TRUE
|
||||
#define STM32_CAN_MAX_FILTERS 28
|
||||
|
||||
/* DAC attributes.*/
|
||||
#define STM32_HAS_DAC1 FALSE
|
||||
#define STM32_HAS_DAC2 FALSE
|
||||
|
||||
/* DMA attributes.*/
|
||||
#define STM32_ADVANCED_DMA TRUE
|
||||
#define STM32_HAS_DMA1 TRUE
|
||||
#define STM32_HAS_DMA2 TRUE
|
||||
|
||||
/* ETH attributes.*/
|
||||
#define STM32_HAS_ETH FALSE
|
||||
|
||||
/* EXTI attributes.*/
|
||||
#define STM32_EXTI_NUM_CHANNELS 23
|
||||
|
||||
/* GPIO attributes.*/
|
||||
#define STM32_HAS_GPIOA TRUE
|
||||
#define STM32_HAS_GPIOB TRUE
|
||||
#define STM32_HAS_GPIOC TRUE
|
||||
#define STM32_HAS_GPIOD TRUE
|
||||
#define STM32_HAS_GPIOE TRUE
|
||||
#define STM32_HAS_GPIOH TRUE
|
||||
#define STM32_HAS_GPIOF FALSE
|
||||
#define STM32_HAS_GPIOG FALSE
|
||||
#define STM32_HAS_GPIOI FALSE
|
||||
#define STM32_GPIO_EN_MASK (RCC_AHB1ENR_GPIOAEN | \
|
||||
RCC_AHB1ENR_GPIOBEN | \
|
||||
RCC_AHB1ENR_GPIOCEN | \
|
||||
RCC_AHB1ENR_GPIODEN | \
|
||||
RCC_AHB1ENR_GPIOEEN)
|
||||
|
||||
/* I2C attributes.*/
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 5))
|
||||
#define STM32_I2C1_RX_DMA_CHN 0x00100001
|
||||
#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 6))
|
||||
#define STM32_I2C1_TX_DMA_CHN 0x11000000
|
||||
|
||||
#define STM32_HAS_I2C2 TRUE
|
||||
#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 3))
|
||||
#define STM32_I2C2_RX_DMA_CHN 0x00007700
|
||||
#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7)
|
||||
#define STM32_I2C2_TX_DMA_CHN 0x70000000
|
||||
|
||||
#define STM32_HAS_I2C3 TRUE
|
||||
#define STM32_I2C3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
||||
#define STM32_I2C3_RX_DMA_CHN 0x00000300
|
||||
#define STM32_I2C3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
||||
#define STM32_I2C3_TX_DMA_CHN 0x00030000
|
||||
|
||||
/* RTC attributes.*/
|
||||
#define STM32_HAS_RTC TRUE
|
||||
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
||||
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
|
||||
#define STM32_RTC_NUM_ALARMS 2
|
||||
#define STM32_RTC_HAS_INTERRUPTS FALSE
|
||||
|
||||
/* SDIO attributes.*/
|
||||
#define STM32_HAS_SDIO TRUE
|
||||
#define STM32_SDC_SDIO_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 6))
|
||||
#define STM32_SDC_SDIO_DMA_CHN 0x04004000
|
||||
|
||||
/* SPI attributes.*/
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 2))
|
||||
#define STM32_SPI1_RX_DMA_CHN 0x00000303
|
||||
#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 5))
|
||||
#define STM32_SPI1_TX_DMA_CHN 0x00303000
|
||||
|
||||
#define STM32_HAS_SPI2 TRUE
|
||||
#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
||||
#define STM32_SPI2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
||||
#define STM32_SPI2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_SPI3 TRUE
|
||||
#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 0) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 2))
|
||||
#define STM32_SPI3_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
|
||||
STM32_DMA_STREAM_ID_MSK(1, 7))
|
||||
#define STM32_SPI3_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_SPI4 TRUE
|
||||
#define STM32_SPI4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 3))
|
||||
#define STM32_SPI4_RX_DMA_CHN 0x00005004
|
||||
#define STM32_SPI4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 4))
|
||||
#define STM32_SPI4_TX_DMA_CHN 0x00050040
|
||||
|
||||
#define STM32_HAS_SPI5 FALSE
|
||||
#define STM32_HAS_SPI6 FALSE
|
||||
|
||||
/* TIM attributes.*/
|
||||
#define STM32_TIM_MAX_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM1 TRUE
|
||||
#define STM32_TIM1_IS_32BITS FALSE
|
||||
#define STM32_TIM1_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM2 TRUE
|
||||
#define STM32_TIM2_IS_32BITS TRUE
|
||||
#define STM32_TIM2_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM3 TRUE
|
||||
#define STM32_TIM3_IS_32BITS FALSE
|
||||
#define STM32_TIM3_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM4 TRUE
|
||||
#define STM32_TIM4_IS_32BITS FALSE
|
||||
#define STM32_TIM4_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM5 TRUE
|
||||
#define STM32_TIM5_IS_32BITS TRUE
|
||||
#define STM32_TIM5_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM9 TRUE
|
||||
#define STM32_TIM9_IS_32BITS FALSE
|
||||
#define STM32_TIM9_CHANNELS 2
|
||||
|
||||
#define STM32_HAS_TIM10 TRUE
|
||||
#define STM32_TIM10_IS_32BITS FALSE
|
||||
#define STM32_TIM10_CHANNELS 2
|
||||
|
||||
#define STM32_HAS_TIM11 TRUE
|
||||
#define STM32_TIM11_IS_32BITS FALSE
|
||||
#define STM32_TIM11_CHANNELS 2
|
||||
|
||||
#define STM32_HAS_TIM6 FALSE
|
||||
#define STM32_HAS_TIM7 FALSE
|
||||
#define STM32_HAS_TIM8 FALSE
|
||||
#define STM32_HAS_TIM12 FALSE
|
||||
#define STM32_HAS_TIM13 FALSE
|
||||
#define STM32_HAS_TIM14 FALSE
|
||||
#define STM32_HAS_TIM15 FALSE
|
||||
#define STM32_HAS_TIM16 FALSE
|
||||
#define STM32_HAS_TIM17 FALSE
|
||||
#define STM32_HAS_TIM18 FALSE
|
||||
#define STM32_HAS_TIM19 FALSE
|
||||
|
||||
/* USART attributes.*/
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 5))
|
||||
#define STM32_USART1_RX_DMA_CHN 0x00400400
|
||||
#define STM32_USART1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
|
||||
#define STM32_USART1_TX_DMA_CHN 0x40000000
|
||||
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
||||
#define STM32_USART2_RX_DMA_CHN 0x00400000
|
||||
#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6)
|
||||
#define STM32_USART2_TX_DMA_CHN 0x04000000
|
||||
|
||||
#define STM32_HAS_USART3 FALSE
|
||||
#define STM32_HAS_UART4 FALSE
|
||||
#define STM32_HAS_UART5 FALSE
|
||||
#endif /* defined(STM32F401xx) */
|
||||
|
||||
#define STM32_HAS_USART6 TRUE
|
||||
#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) |\
|
||||
|
|
@ -322,23 +796,18 @@
|
|||
/* USB attributes.*/
|
||||
#define STM32_HAS_USB FALSE
|
||||
#define STM32_HAS_OTG1 TRUE
|
||||
#if !defined(STM32F401xx)
|
||||
#define STM32_HAS_OTG2 TRUE
|
||||
#else /* defined(STM32F401xx) */
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
|
||||
/* FSMC attributes.*/
|
||||
#define STM32_HAS_FSMC FALSE
|
||||
#endif /* defined(STM32F401xx) */
|
||||
|
||||
/* EMC attributes.*/
|
||||
#define STM32_HAS_FSMC TRUE
|
||||
#define STM32_FSMC_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 1) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 2) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 3) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 4) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 5) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 6) |\
|
||||
STM32_DMA_STREAM_ID_MSK(2, 7))
|
||||
#define STM32_FSMC_DMA_CHN 0x03010201
|
||||
/*===========================================================================*/
|
||||
/* STM32F411xE. */
|
||||
/*===========================================================================*/
|
||||
#if defined(STM32F411xx)
|
||||
#error "missing registry for STM32F411xx"
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
#endif /* _STM32_REGISTRY_H_ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue