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ChibiOS
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@633 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2009-01-18 09:45:57 +00:00
parent ed534c135c
commit 140c2d06cd
4 changed files with 58 additions and 36 deletions
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6
ports/ARMCM3/chcore.c
View File

@ -33,7 +33,7 @@
* @param msg pointer to the message string
*/
__attribute__((weak))
void sys_puts(char *msg) {
void port_puts(char *msg) {
}
/**
@ -42,9 +42,9 @@ void sys_puts(char *msg) {
* it in your application code.
*/
__attribute__((weak))
void sys_halt(void) {
void port_halt(void) {
sys_disable_all();
port_disable();
while (TRUE) {
}
}

83
ports/ARMCM3/chcore.h
View File

@ -150,79 +150,100 @@ typedef struct {
* IRQ prologue code, inserted at the start of all IRQ handlers enabled to
* invoke system APIs.
*/
#define SYS_IRQ_PROLOGUE()
#define PORT_IRQ_PROLOGUE()
/**
* IRQ epilogue code, inserted at the end of all IRQ handlers enabled to
* invoke system APIs.
*/
#define SYS_IRQ_EPILOGUE() { \
#define PORT_IRQ_EPILOGUE() { \
SCB_ICSR = ICSR_PENDSVSET; \
}
/**
* This port function is implemented as inlined code for performance reasons.
* IRQ handler function modifier.
*/
#define sys_disable() { \
#define PORT_IRQ_HANDLER
/**
* This function is empty in this port.
*/
#define port_init()
/**
* Raises the base priority to kernel level.
*/
#define port_lock() { \
register uint32_t tmp asm ("r3") = BASEPRI_KERNEL; \
asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \
}
/**
* This port function is implemented as inlined code for performance reasons.
* Lowers the base priority to user level.
*/
#define sys_enable() { \
#define port_unlock() { \
register uint32_t tmp asm ("r3") = BASEPRI_USER; \
asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \
}
/**
* This port function is implemented as inlined code for performance reasons.
* Same as @p port_lock() in this port.
*/
#define sys_disable_from_isr() sys_disable()
#define port_lock_from_isr() port_lock()
/**
* Same as @p port_unlock() in this port.
*/
#define port_unlock_from_isr() port_unlock()
/**
* Disables all the interrupt sources by raising the priority mask to level 0.
*/
#define port_disable() asm volatile ("cpsid i")
/**
* Raises/lowers the base priority to kernel level.
*/
#define port_suspend() { \
register uint32_t tmp asm ("r3") = BASEPRI_KERNEL; \
asm volatile ("msr BASEPRI, %0 \n\t" \
"cpsie i" : : "r" (tmp)); \
}
/**
* Lowers the base priority to user level.
*/
#define port_enable() { \
register uint32_t tmp asm ("r3") = BASEPRI_USER; \
asm volatile ("msr BASEPRI, %0 \n\t" \
"cpsie i" : : "r" (tmp)); \
}
/**
* This port function is implemented as inlined code for performance reasons.
*/
#define sys_enable_from_isr() sys_enable()
/**
* Disables all the interrupt sources, even those having a priority higher
* to the kernel.
* In the Cortex-M3 it raises the priority mask to level 0.
*/
#define sys_disable_all() asm volatile ("cpsid i")
#if ENABLE_WFI_IDLE != 0
/**
* This port function is implemented as inlined code for performance reasons.
*/
#define sys_wait_for_interrupt() { \
#if (ENABLE_WFI_IDLE != 0) || defined(__DOXYGEN__)
#define port_wait_for_interrupt() { \
asm volatile ("wfi"); \
}
#else
#define sys_wait_for_interrupt()
#define port_wait_for_interrupt()
#endif
/**
* This port function is implemented as inlined code for performance reasons.
*/
#define sys_switch(otp, ntp) { \
#define port_switch(otp, ntp) { \
register Thread *_otp asm ("r0") = (otp); \
register Thread *_ntp asm ("r1") = (ntp); \
asm volatile ("svc #0" : : "r" (_otp), "r" (_ntp)); \
}
/**
* IRQ handler function modifier.
*/
#define SYS_IRQ_HANDLER
#ifdef __cplusplus
extern "C" {
#endif
void sys_puts(char *msg);
void sys_halt(void);
void port_puts(char *msg);
void port_halt(void);
void threadstart(void);
#ifdef __cplusplus
}

2
ports/ARMCM3/crt0.s
View File

@ -95,7 +95,7 @@ bloop:
movs r0, #0
mov r1, r0
bl main
bl sys_halt
bl port_halt
/*
* Default early initialization code. It is declared weak in order to be

3
readme.txt
View File

@ -77,7 +77,7 @@ Win32-MinGW - ChibiOS/RT simulator and demo into a WIN32 process,
*** 1.1.0unstable ***
- NEW: Better separation between the port code and the system APIs, now an
architecture-specific "driver" contains all the port related code.
Port functions are no more directly exposed as APIs to the user code.
Port functions/macros are no more directly exposed as APIs to the user code.
- NEW: Added a configuration option to enable nested system locks/unlocks.
- NEW: Improved the interrupt handlers related code. Now interrupts are
handled in a very similar way in every architecture.
@ -87,6 +87,7 @@ Win32-MinGW - ChibiOS/RT simulator and demo into a WIN32 process,
CH_IRQ_HANDLER that should be used when declaring an interrupt handler.
- Introduced the concept of interrupt classes, see the documentation.
- Introduced the concept of system state, see the documentation.
- Huge improvements to the ports documentation.
*** 1.0.0rc2 ***
- FIX: Removed unused variable "retaddr" from the Cortex-M3 port.