andreika-git
/
ChibiOS
mirror of https://github.com/andreika-git/ChibiOS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

H7 ADC demo working, not fully tested. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12496 110e8d01-0319-4d1e-a829-52ad28d1bb01
This commit is contained in:
Giovanni Di Sirio 2018-12-30 13:29:58 +00:00
parent afec43446f
commit 15fca87673
2 changed files with 37 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
os/hal/ports/common/ARMCMx/cache.h
View File

@ -29,6 +29,15 @@
/* Driver constants. */
/*===========================================================================*/
#if defined(__DCACHE_PRESENT) || defined(__DOXYGEN__)
/**
* @brief Data cache line size, zero if there is no data cache.
*/
#define CACHE_LINE_SIZE 32U
#else
#define CACHE_LINE_SIZE 0U
#endif
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@ -47,6 +56,17 @@
#if defined(__DCACHE_PRESENT) || defined(__DOXYGEN__)
#if (__DCACHE_PRESENT != 0) || defined(__DOXYGEN__)
/**
* @brief Aligns the specified size to a multiple of cache line size.
* @note This macros assumes that the size of the type @p t is a power of
* two and not greater than @p CACHE_LINE_SIZE.
*
* @param[in] t type of the buffer element
* @param[in] n number of buffer elements
*/
#define CACHE_SIZE_ALIGN(t, n) \
((((((n) * sizeof (t)) - 1U) | (CACHE_LINE_SIZE - 1U)) + 1U) / sizeof (t))
/**
* @brief Invalidates the data cache lines overlapping a memory buffer.
* @details This function is meant to make sure that data written in
@ -67,7 +87,7 @@
__DSB(); \
while (start < end) { \
SCB->DCIMVAC = (uint32_t)start; \
start += 32U; \
start += CACHE_LINE_SIZE; \
} \
__DSB(); \
__ISB(); \
@ -93,7 +113,7 @@
__DSB(); \
while (start < end) { \
SCB->DCCIMVAC = (uint32_t)start; \
start += 32U; \
start += CACHE_LINE_SIZE; \
} \
__DSB(); \
__ISB(); \
@ -111,6 +131,8 @@
#endif
#else /* !defined(__DCACHE_PRESENT) */
#define CACHE_SIZE_ALIGN(t, n) (n)
#define cacheBufferInvalidate(addr, size) { \
(void)(addr); \
(void)(size); \

15
testhal/STM32/multi/ADC/main.c
View File

@ -16,6 +16,7 @@
#include "ch.h"
#include "hal.h"
#include "ccportab.h"
#include "portab.h"
@ -26,8 +27,17 @@
#define ADC_GRP1_BUF_DEPTH 1
#define ADC_GRP2_BUF_DEPTH 64
adcsample_t samples1[ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH];
adcsample_t samples2[ADC_GRP2_NUM_CHANNELS * ADC_GRP2_BUF_DEPTH];
/* Buffers are allocated with size and address aligned to the cache
line size.*/
#if CACHE_LINE_SIZE > 0
CC_ALIGN(CACHE_LINE_SIZE)
#endif
adcsample_t samples1[CACHE_SIZE_ALIGN(adcsample_t, ADC_GRP1_NUM_CHANNELS * ADC_GRP1_BUF_DEPTH)];
#if CACHE_LINE_SIZE > 0
CC_ALIGN(CACHE_LINE_SIZE)
#endif
adcsample_t samples2[CACHE_SIZE_ALIGN(adcsample_t, ADC_GRP2_NUM_CHANNELS * ADC_GRP2_BUF_DEPTH)];
/*
* ADC streaming callback.
@ -110,6 +120,7 @@ int main(void) {
/* Performing a one-shot conversion on two channels.*/
adcConvert(&PORTAB_ADC1, &portab_adcgrpcfg1, samples1, ADC_GRP1_BUF_DEPTH);
cacheBufferInvalidate(samples1, sizeof (samples1) / sizeof (adcsample_t));
/*
* Normal main() thread activity, if the button is pressed then the