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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1769 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2010-03-22 12:29:20 +00:00
parent 51d47eb079
commit 167f5bc878
12 changed files with 203 additions and 107 deletions
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4
demos/ARMCM3-STM32F103-GCC/Makefile
View File

@ -60,7 +60,7 @@ CHIBIOS = ../..
include $(CHIBIOS)/boards/OLIMEX_STM32_P103/board.mk
include $(CHIBIOS)/os/hal/platforms/STM32/platform.mk
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCM3/port.mk
include $(CHIBIOS)/os/ports/GCC/ARMCM3/STM32F103/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
include $(CHIBIOS)/test/test.mk
@ -153,7 +153,7 @@ CPPWARN = -Wall -Wextra
#
# List all default C defines here, like -D_DEBUG=1
DDEFS =
DDEFS = -DSTM32F10X_MD
# List all default ASM defines here, like -D_DEBUG=1
DADEFS =

35
demos/ARMCM3-STM32F103-GCC/mcuconf.h
View File

@ -25,10 +25,11 @@
* is enabled in halconf.h.
*
* IRQ priorities:
* 0xF0 Lowest, priority level reserved for PENDSV.
* 0xE0...0x40 Normal IRQs priority levels (0x80 used by SYSTICK).
* 0x30 Used by SVCALL, do not share.
* 0x20...0x00 Fast interrupts, can preempt the kernel but cannot use it.
* 15 Lowest, priority level reserved for PENDSV.
* 14...4 Normal IRQs priority levels (0x80 used by SYSTICK).
* 3 Used by SVCALL, do not share.
* 2...0 Fast interrupts, can preempt the kernel but cannot use it
* directly.
*
* DMA priorities:
* 0...3 Lowest...Highest.
@ -44,14 +45,14 @@
*/
#define USE_STM32_ADC1 TRUE
#define STM32_ADC1_DMA_PRIORITY 3
#define STM32_ADC1_IRQ_PRIORITY 0x50
#define STM32_ADC1_IRQ_PRIORITY CORTEX_PRIORITY(5)
#define STM32_ADC1_DMA_ERROR_HOOK() chSysHalt()
/*
* CAN driver system settings.
*/
#define USE_STM32_CAN1 TRUE
#define STM32_CAN1_IRQ_PRIORITY 0xB0
#define STM32_CAN1_IRQ_PRIORITY CORTEX_PRIORITY(11)
/*
* PWM driver system settings.
@ -60,10 +61,10 @@
#define USE_STM32_PWM2 FALSE
#define USE_STM32_PWM3 FALSE
#define USE_STM32_PWM4 FALSE
#define STM32_PWM1_IRQ_PRIORITY 0x70
#define STM32_PWM2_IRQ_PRIORITY 0x70
#define STM32_PWM3_IRQ_PRIORITY 0x70
#define STM32_PWM4_IRQ_PRIORITY 0x70
#define STM32_PWM1_IRQ_PRIORITY CORTEX_PRIORITY(7)
#define STM32_PWM2_IRQ_PRIORITY CORTEX_PRIORITY(7)
#define STM32_PWM3_IRQ_PRIORITY CORTEX_PRIORITY(7)
#define STM32_PWM4_IRQ_PRIORITY CORTEX_PRIORITY(7)
/*
* SERIAL driver system settings.
@ -75,12 +76,12 @@
#define USE_STM32_UART4 FALSE
#define USE_STM32_UART5 FALSE
#endif
#define STM32_USART1_PRIORITY 0xC0
#define STM32_USART2_PRIORITY 0xC0
#define STM32_USART3_PRIORITY 0xC0
#define STM32_USART1_PRIORITY CORTEX_PRIORITY(12)
#define STM32_USART2_PRIORITY CORTEX_PRIORITY(12)
#define STM32_USART3_PRIORITY CORTEX_PRIORITY(12)
#if defined(STM32F10X_HD) || defined(STM32F10X_CL)
#define STM32_UART4_PRIORITY 0xC0
#define STM32_UART5_PRIORITY 0xC0
#define STM32_UART4_PRIORITY CORTEX_PRIORITY(12)
#define STM32_UART5_PRIORITY CORTEX_PRIORITY(12)
#endif
/*
@ -90,6 +91,6 @@
#define USE_STM32_SPI2 TRUE
#define STM32_SPI1_DMA_PRIORITY 2
#define STM32_SPI2_DMA_PRIORITY 2
#define STM32_SPI1_IRQ_PRIORITY 0xA0
#define STM32_SPI2_IRQ_PRIORITY 0xA0
#define STM32_SPI1_IRQ_PRIORITY CORTEX_PRIORITY(10)
#define STM32_SPI2_IRQ_PRIORITY CORTEX_PRIORITY(10)
#define STM32_SPI1_DMA_ERROR_HOOK() chSysHalt()

5
os/hal/platforms/STM32/adc_lld.h
View File

@ -77,10 +77,11 @@
/**
* @brief ADC1 interrupt priority level setting.
* @note @p BASEPRI_KERNEL >= @p STM32_ADC1_IRQ_PRIORITY > @p PRIORITY_PENDSV.
* @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_ADC1_IRQ_PRIORITY >
* @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ADC1_IRQ_PRIORITY 0x50
#define STM32_ADC1_IRQ_PRIORITY CORTEX_PRIORITY(5)
#endif
/**

5
os/hal/platforms/STM32/can_lld.h
View File

@ -83,10 +83,11 @@
/**
* @brief CAN1 interrupt priority level setting.
* @note @p BASEPRI_KERNEL >= @p STM32_SPI1_IRQ_PRIORITY > @p PRIORITY_PENDSV.
* @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_SPI1_IRQ_PRIORITY >
* @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_CAN1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_CAN1_IRQ_PRIORITY 0xB0
#define STM32_CAN1_IRQ_PRIORITY CORTEX_PRIORITY(11)
#endif
/*===========================================================================*/

6
os/hal/platforms/STM32/hal_lld.c
View File

@ -75,9 +75,9 @@ void hal_lld_init(void) {
/* Note: PRIGROUP 4:0 (4:4).*/
SCB->AIRCR = AIRCR_VECTKEY | SCB_AIRCR_PRIGROUP_0 | SCB_AIRCR_PRIGROUP_1;
NVICSetSystemHandlerPriority(HANDLER_SVCALL, PRIORITY_SVCALL);
NVICSetSystemHandlerPriority(HANDLER_SYSTICK, PRIORITY_SYSTICK);
NVICSetSystemHandlerPriority(HANDLER_PENDSV, PRIORITY_PENDSV);
NVICSetSystemHandlerPriority(HANDLER_SVCALL, CORTEX_PRIORITY_SVCALL);
NVICSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK);
NVICSetSystemHandlerPriority(HANDLER_PENDSV, CORTEX_PRIORITY_PENDSV);
/* Systick initialization.*/
SysTick->LOAD = SYSCLK / (8000000 / CH_FREQUENCY) - 1;

20
os/hal/platforms/STM32/pwm_lld.h
View File

@ -80,34 +80,38 @@
/**
* @brief PWM1 interrupt priority level setting.
* @note @p BASEPRI_KERNEL >= @p STM32_PWM1_IRQ_PRIORITY > @p PRIORITY_PENDSV.
* @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_PWM1_IRQ_PRIORITY >
* @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_PWM1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_PWM1_IRQ_PRIORITY 0x70
#define STM32_PWM1_IRQ_PRIORITY CORTEX_PRIORITY(7)
#endif
/**
* @brief PWM2 interrupt priority level setting.
* @note @p BASEPRI_KERNEL >= @p STM32_PWM2_IRQ_PRIORITY > @p PRIORITY_PENDSV.
* @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_PWM2_IRQ_PRIORITY >
* @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_PWM2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_PWM2_IRQ_PRIORITY 0x70
#define STM32_PWM2_IRQ_PRIORITY CORTEX_PRIORITY(7)
#endif
/**
* @brief PWM3 interrupt priority level setting.
* @note @p BASEPRI_KERNEL >= @p STM32_PWM3_IRQ_PRIORITY > @p PRIORITY_PENDSV.
* @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_PWM3_IRQ_PRIORITY >
* @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_PWM3_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_PWM3_IRQ_PRIORITY 0x70
#define STM32_PWM3_IRQ_PRIORITY CORTEX_PRIORITY(7)
#endif
/**
* @brief PWM4 interrupt priority level setting.
* @note @p BASEPRI_KERNEL >= @p STM32_PWM4_IRQ_PRIORITY > @p PRIORITY_PENDSV.
* @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_PWM4_IRQ_PRIORITY >
* @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_PWM4_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_PWM4_IRQ_PRIORITY 0x80
#define STM32_PWM4_IRQ_PRIORITY CORTEX_PRIORITY(7)
#endif
/*===========================================================================*/

30
os/hal/platforms/STM32/serial_lld.h
View File

@ -72,7 +72,7 @@
* @note The default is @p FALSE.
*/
#if !defined(USE_STM32_UART4) || defined(__DOXYGEN__)
#define USE_STM32_UART4 TRUE
#define USE_STM32_UART4 TRUE
#endif
/**
@ -81,51 +81,57 @@
* @note The default is @p FALSE.
*/
#if !defined(USE_STM32_USART3) || defined(__DOXYGEN__)
#define USE_STM32_UART5 TRUE
#define USE_STM32_UART5 TRUE
#endif
#endif
/**
* @brief USART1 interrupt priority level setting.
* @note @p BASEPRI_KERNEL >= @p STM32_USART1_PRIORITY > @p PRIORITY_PENDSV.
* @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_USART1_PRIORITY >
* @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_USART1_PRIORITY) || defined(__DOXYGEN__)
#define STM32_USART1_PRIORITY 0xC0
#define STM32_USART1_PRIORITY CORTEX_PRIORITY(12)
#endif
/**
* @brief USART2 interrupt priority level setting.
* @note @p BASEPRI_KERNEL >= @p STM32_USART2_PRIORITY > @p PRIORITY_PENDSV.
* @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_USART2_PRIORITY >
* @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_USART2_PRIORITY) || defined(__DOXYGEN__)
#define STM32_USART2_PRIORITY 0xC0
#define STM32_USART2_PRIORITY CORTEX_PRIORITY(12)
#endif
/**
* @brief USART3 interrupt priority level setting.
* @note @p BASEPRI_KERNEL >= @p STM32_USART3_PRIORITY > @p PRIORITY_PENDSV.
* @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_USART3_PRIORITY >
* @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_USART3_PRIORITY) || defined(__DOXYGEN__)
#define STM32_USART3_PRIORITY 0xC0
#define STM32_USART3_PRIORITY CORTEX_PRIORITY(12)
#endif
#if defined(STM32F10X_HD) || defined(STM32F10X_CL) || defined(__DOXYGEN__)
/**
* @brief UART4 interrupt priority level setting.
* @note @p BASEPRI_KERNEL >= @p STM32_USART2_PRIORITY > @p PRIORITY_PENDSV.
* @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_USART2_PRIORITY >
* @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_UART4_PRIORITY) || defined(__DOXYGEN__)
#define STM32_UART4_PRIORITY 0xC0
#define STM32_UART4_PRIORITY CORTEX_PRIORITY(12)
#endif
/**
* @brief UART5 interrupt priority level setting.
* @note @p BASEPRI_KERNEL >= @p STM32_USART2_PRIORITY > @p PRIORITY_PENDSV.
* @note @p CORTEX_BASEPRI_KERNEL >= @p STM32_USART2_PRIORITY >
* @p CORTEX_PRIORITY_PENDSV.
*/
#if !defined(STM32_UART5_PRIORITY) || defined(__DOXYGEN__)
#define STM32_UART5_PRIORITY 0xC0
#define STM32_UART5_PRIORITY CORTEX_PRIORITY(12)
#endif
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/

4
os/hal/platforms/STM32/spi_lld.h
View File

@ -80,7 +80,7 @@
* @note @p BASEPRI_KERNEL >= @p STM32_SPI1_IRQ_PRIORITY > @p PRIORITY_PENDSV.
*/
#if !defined(STM32_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SPI1_IRQ_PRIORITY 0xA0
#define STM32_SPI1_IRQ_PRIORITY CORTEX_PRIORITY(10)
#endif
/**
@ -88,7 +88,7 @@
* @note @p BASEPRI_KERNEL >= @p STM32_SPI2_IRQ_PRIORITY > @p PRIORITY_PENDSV.
*/
#if !defined(STM32_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_SPI2_IRQ_PRIORITY 0xA0
#define STM32_SPI2_IRQ_PRIORITY CORTEX_PRIORITY(10)
#endif
/**

115
os/ports/GCC/ARMCM3/STM32F103/cmparams.h Normal file
View File

@ -0,0 +1,115 @@
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @file ARMCM3/STM32F103/cmparams.h
* @brief ARM Cortex-M3 STM32 specific parameters.
*
* @addtogroup ARMCM3_STM32F103
* @{
*/
#ifndef _CMPARAMS_H_
#define _CMPARAMS_H_
/*===========================================================================*/
/* Constants parameters. */
/*===========================================================================*/
/**
* @brief Cortex core model.
*/
#define CORTEX_MODEL CORTEX_M3
/**
* @brief Systick unit presence.
*/
#define CORTEX_HAS_ST TRUE
/**
* @brief Memory Protection unit presence.
*/
#define CORTEX_HAS_MPU FALSE
/**
* @brief Number of bits in priority masks.
* @details The available number of priority levels is equal to
* (1 << @p CORTEX_PRIORITY_BITS).
*/
#define CORTEX_PRIORITY_BITS 4
/**
* @brief Priority to priority mask conversion macro.
*/
#define CORTEX_PRIORITY(n) ((n) << (8 - CORTEX_PRIORITY_BITS))
/*===========================================================================*/
/* Configurable parameters. */
/*===========================================================================*/
/**
* @brief BASEPRI user level, 0 = disabled.
*/
#ifndef CORTEX_BASEPRI_USER
#define CORTEX_BASEPRI_USER CORTEX_PRIORITY(0)
#endif
/**
* @brief BASEPRI level within kernel lock.
* @details Priority levels higher than this one (lower values) are unaffected
* by the OS activity and can be classified as fast interrupt sources,
* see @ref interrupt_classes.
*/
#ifndef CORTEX_BASEPRI_KERNEL
#define CORTEX_BASEPRI_KERNEL CORTEX_PRIORITY(4)
#endif
/**
* @brief SVCALL handler priority.
* @note This priority must always be one level above the @p BASEPRI_KERNEL
* value.
* @note It is recommended, but not mandatory, to leave this priority level
* for this handler alone.
*/
#ifndef CORTEX_PRIORITY_SVCALL
#define CORTEX_PRIORITY_SVCALL CORTEX_PRIORITY(3)
#endif
/**
* @brief SYSTICK handler priority.
*/
#ifndef CORTEX_PRIORITY_SYSTICK
#define CORTEX_PRIORITY_SYSTICK CORTEX_PRIORITY(8)
#endif
/**
* @brief PENDSV handler priority.
* @note It is recommended to leave this priority level for this handler
* alone.
* @note This is a reserved handler and its priority must always be the
* lowest priority in the system in order to be always executed last
* in the interrupt servicing chain.
*/
#ifndef CORTEX_PRIORITY_PENDSV
#define CORTEX_PRIORITY_PENDSV CORTEX_PRIORITY(15)
#endif
#endif /* _CMPARAMS_H_ */
/** @} */

1
os/ports/GCC/ARMCM3/port.mk → os/ports/GCC/ARMCM3/STM32F103/port.mk
View File

@ -6,4 +6,5 @@ PORTSRC = ${CHIBIOS}/os/ports/GCC/ARMCM3/chcore.c \
PORTASM = ${CHIBIOS}/os/ports/GCC/ARMCM3/crt0.s
PORTINC = ${CHIBIOS}/os/ports/GCC/ARMCM3 \
${CHIBIOS}/os/ports/GCC/ARMCM3/STM32F103 \
${CHIBIOS}/os/ports/GCC/ARMCM3/cmsis

4
os/ports/GCC/ARMCM3/chcore.c
View File

@ -109,7 +109,7 @@ void SVCallVector(Thread *ntp, Thread *otp) {
#ifdef CH_CURRP_REGISTER_CACHE
#define PUSH_CONTEXT(sp) { \
register uint32_t tmp asm ("r3") = BASEPRI_USER; \
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_USER; \
asm volatile ("mrs %0, PSP \n\t" \
"stmdb %0!, {r3-r6,r8-r11, lr}" : \
"=r" (sp) : "r" (sp), "r" (tmp)); \
@ -123,7 +123,7 @@ void SVCallVector(Thread *ntp, Thread *otp) {
}
#else
#define PUSH_CONTEXT(sp) { \
register uint32_t tmp asm ("r3") = BASEPRI_USER; \
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_USER; \
asm volatile ("mrs %0, PSP \n\t" \
"stmdb %0!, {r3-r11,lr}" : \
"=r" (sp) : "r" (sp), "r" (tmp)); \

81
os/ports/GCC/ARMCM3/chcore.h
View File

@ -39,67 +39,34 @@
#define ENABLE_WFI_IDLE 0
#endif
/**
* @brief BASEPRI user level, 0 = disabled.
*/
#ifndef BASEPRI_USER
#define BASEPRI_USER 0
#endif
/**
* @brief BASEPRI level within kernel lock.
* @details Priority levels higher than this one (lower values) are unaffected
* by the OS activity and can be classified as fast interrupt sources,
* see @ref interrupt_classes.
*/
#ifndef BASEPRI_KERNEL
#define BASEPRI_KERNEL 0x40
#endif
/**
* @brief SVCALL handler priority.
* @note This priority must always be one level above the @p BASEPRI_KERNEL
* value.
* @note It is recommended, but not mandatory, to leave this priority level
* for this handler alone.
*/
#ifndef PRIORITY_SVCALL
#define PRIORITY_SVCALL (BASEPRI_KERNEL - 0x10)
#endif
/**
* @brief SYSTICK handler priority.
*/
#ifndef PRIORITY_SYSTICK
#define PRIORITY_SYSTICK 0x80
#endif
/**
* @brief PENDSV handler priority.
* @note It is recommended to leave this priority level for this handler
* alone.
* @note This is a reserved handler and its priority must always be the
* lowest priority in the system in order to be always executed last
* in the interrupt servicing chain.
*/
#ifndef PRIORITY_PENDSV
#define PRIORITY_PENDSV 0xF0
#endif
/**
* @brief Macro defining the ARM Cortex-M3 architecture.
*/
#define CH_ARCHITECTURE_ARMCM3
#define CORTEX_M0 0 /**< @brief Cortex-M0 variant. */
#define CORTEX_M3 3 /**< @brief Cortex-M3 variant. */
/**
* @brief Name of the implemented architecture.
*/
#define CH_ARCHITECTURE_NAME "ARM"
/* Inclusion of the Cortex-Mx implementation specific parameters.*/
#include "cmparams.h"
/* Generating model-dependent info.*/
#if (CORTEX_MODEL == CORTEX_M3) || defined(__DOXYGEN__)
/**
* @brief Macro defining the ARM Cortex-M3 architecture.
*/
#define CH_ARCHITECTURE_ARMCM3
/**
* @brief Name of the architecture variant (optional).
*/
#define CH_CORE_VARIANT_NAME "Cortex-M3"
#define CH_CORE_VARIANT_NAME "Cortex-M3"
#elif (CORTEX_MODEL == CORTEX_M0)
#define CH_ARCHITECTURE_ARMCM0
#define CH_CORE_VARIANT_NAME "Cortex-M0"
#else
#error "unknown or unsupported Cortex-M model"
#endif
/**
* @brief 32 bits stack and memory alignment enforcement.
@ -170,7 +137,7 @@ struct context {
tp->p_ctx.r13 = (struct intctx *)((uint8_t *)workspace + \
wsize - \
sizeof(struct intctx)); \
tp->p_ctx.r13->basepri = BASEPRI_USER; \
tp->p_ctx.r13->basepri = CORTEX_BASEPRI_USER; \
tp->p_ctx.r13->lr_exc = (regarm_t)0xFFFFFFFD; \
tp->p_ctx.r13->r0 = arg; \
tp->p_ctx.r13->lr_thd = chThdExit; \
@ -263,7 +230,7 @@ struct context {
*/
#if CH_OPTIMIZE_SPEED
#define port_lock() { \
register uint32_t tmp asm ("r3") = BASEPRI_KERNEL; \
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \
asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \
}
#else
@ -280,7 +247,7 @@ struct context {
*/
#if CH_OPTIMIZE_SPEED
#define port_unlock() { \
register uint32_t tmp asm ("r3") = BASEPRI_USER; \
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_USER; \
asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \
}
#else
@ -321,7 +288,7 @@ struct context {
* @note In this port it raises/lowers the base priority to kernel level.
*/
#define port_suspend() { \
register uint32_t tmp asm ("r3") = BASEPRI_KERNEL; \
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \
asm volatile ("msr BASEPRI, %0 \n\t" \
"cpsie i" : : "r" (tmp)); \
}
@ -331,7 +298,7 @@ struct context {
* @note In this port it lowers the base priority to user level.
*/
#define port_enable() { \
register uint32_t tmp asm ("r3") = BASEPRI_USER; \
register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_USER; \
asm volatile ("msr BASEPRI, %0 \n\t" \
"cpsie i" : : "r" (tmp)); \
}