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STM32F1xx devices clock configuration updated to make it similar to the newer STM32 devices. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3764 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio 2012-01-08 13:41:31 +00:00
parent 040c4026cc
commit 169a4bbc7e
3 changed files with 247 additions and 54 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
docs/reports/STM32F100-24-GCC.txt
View File

@ -5,11 +5,13 @@ Settings: SYSCLK=24, ACR=0x10 (no wait states)
*** ChibiOS/RT test suite
***
*** Kernel: 2.1.7unstable
*** GCC Version: 4.5.1
*** Kernel: 2.3.5unstable
*** Compiled: Jan 8 2012 - 14:14:07
*** Compiler: GCC 4.6.2
*** Architecture: ARMv7-M
*** Core Variant: Cortex-M3
*** Platform: STM32 Value Line Medium Density
*** Port Info: Advanced kernel mode
*** Platform: STM32F1 Value Line Medium Density
*** Test Board: ST STM32VL-Discovery
----------------------------------------------------------------------------
@ -98,56 +100,56 @@ Settings: SYSCLK=24, ACR=0x10 (no wait states)
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.1 (Benchmark, messages #1)
--- Score : 103348 msgs/S, 206696 ctxswc/S
--- Score : 107466 msgs/S, 214932 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.2 (Benchmark, messages #2)
--- Score : 84666 msgs/S, 169332 ctxswc/S
--- Score : 88361 msgs/S, 176722 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.3 (Benchmark, messages #3)
--- Score : 84666 msgs/S, 169332 ctxswc/S
--- Score : 88361 msgs/S, 176722 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.4 (Benchmark, context switch)
--- Score : 341704 ctxswc/S
--- Score : 364984 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.5 (Benchmark, threads, full cycle)
--- Score : 64356 threads/S
--- Score : 64312 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.6 (Benchmark, threads, create only)
--- Score : 94372 threads/S
--- Score : 91069 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads)
--- Score : 26091 reschedules/S, 156546 ctxswc/S
--- Score : 27423 reschedules/S, 164538 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.8 (Benchmark, round robin context switching)
--- Score : 199360 ctxswc/S
--- Score : 194360 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.9 (Benchmark, I/O Queues throughput)
--- Score : 203236 bytes/S
--- Score : 262192 bytes/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.10 (Benchmark, virtual timers set/reset)
--- Score : 327148 timers/S
--- Score : 305910 timers/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.11 (Benchmark, semaphores wait/signal)
--- Score : 382084 wait+signal/S
--- Score : 381748 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.12 (Benchmark, mutexes lock/unlock)
--- Score : 284288 lock+unlock/S
--- Score : 268084 lock+unlock/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.13 (Benchmark, RAM footprint)
--- System: 360 bytes
--- Thread: 68 bytes
--- System: 376 bytes
--- Thread: 72 bytes
--- Timer : 20 bytes
--- Semaph: 12 bytes
--- EventS: 4 bytes

6
os/hal/platforms/STM32F1xx/hal_lld.c
View File

@ -140,9 +140,15 @@ void stm32_clock_init(void) {
#endif
/* Clock settings.*/
#if STM32_HAS_USB
RCC->CFGR = STM32_MCOSEL | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE |
STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 |
STM32_HPRE;
#else
RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLXTPRE |
STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 |
STM32_HPRE;
#endif
/* Flash setup and final clock selection. */
FLASH->ACR = STM32_FLASHBITS;

259
os/hal/platforms/STM32F1xx/hal_lld_f100.h
View File

@ -58,11 +58,68 @@
/** @} */
/**
* @name Internal clock sources
* @name Absolute Maximum Ratings
* @{
*/
#define STM32_HSICLK 8000000 /**< High speed internal clock. */
#define STM32_LSICLK 40000 /**< Low speed internal clock. */
/**
* @brief Maximum system clock frequency.
*/
#define STM32_SYSCLK_MAX 24000000
/**
* @brief Maximum HSE clock frequency.
*/
#define STM32_HSECLK_MAX 24000000
/**
* @brief Minimum HSE clock frequency.
*/
#define STM32_HSECLK_MIN 1000000
/**
* @brief Maximum LSE clock frequency.
*/
#define STM32_LSECLK_MAX 1000000
/**
* @brief Minimum LSE clock frequency.
*/
#define STM32_LSECLK_MIN 32768
/**
* @brief Maximum PLLs input clock frequency.
*/
#define STM32_PLLIN_MAX 24000000
/**
* @brief Maximum PLLs input clock frequency.
*/
#define STM32_PLLIN_MIN 1000000
/**
* @brief Maximum PLL output clock frequency.
*/
#define STM32_PLLOUT_MAX 24000000
/**
* @brief Maximum PLL output clock frequency.
*/
#define STM32_PLLOUT_MIN 16000000
/**
* @brief Maximum APB1 clock frequency.
*/
#define STM32_PCLK1_MAX 24000000
/**
* @brief Maximum APB2 clock frequency.
*/
#define STM32_PCLK2_MAX 24000000
/**
* @brief Maximum ADC clock frequency.
*/
#define STM32_ADCCLK_MAX 12000000
/** @} */
/**
@ -106,16 +163,16 @@
#define STM32_PLLXTPRE_DIV1 (0 << 17) /**< HSE divided by 1. */
#define STM32_PLLXTPRE_DIV2 (1 << 17) /**< HSE divided by 2. */
#define STM32_MCO_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
#define STM32_MCO_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */
#define STM32_MCO_HSI (5 << 24) /**< HSI clock on MCO pin. */
#define STM32_MCO_HSE (6 << 24) /**< HSE clock on MCO pin. */
#define STM32_MCO_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
#define STM32_MCOSEL_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */
#define STM32_MCOSEL_HSI (5 << 24) /**< HSI clock on MCO pin. */
#define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */
#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
#define STM32_RTC_NOCLOCK (0 << 8) /**< No clock. */
#define STM32_RTC_LSE (1 << 8) /**< LSE used as RTC clock. */
#define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock. */
#define STM32_RTC_HSE (3 << 8) /**< HSE divided by 128 used as
#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No clock. */
#define STM32_RTCSEL_LSE (1 << 8) /**< LSE used as RTC clock. */
#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */
#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as
RTC clock. */
/** @} */
@ -182,7 +239,7 @@
#define STM32_SPI3_TX_DMA_CHN 0x00000000
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
#define STM32_RTCSEL_HAS_SUBSECONDS TRUE
/* SDIO attributes.*/
#define STM32_HAS_SDIO FALSE
@ -373,11 +430,40 @@
/* USART attributes.*/
#define STM32_HAS_USART1 TRUE
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
#define STM32_USART1_RX_DMA_CHN 0x00000000
#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
#define STM32_USART1_TX_DMA_CHN 0x00000000
#define STM32_HAS_USART2 TRUE
#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
#define STM32_I2C2_RX_DMA_CHN 0x00000000
#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
#define STM32_I2C2_TX_DMA_CHN 0x00000000
#define STM32_HAS_USART3 TRUE
#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
#define STM32_USART3_RX_DMA_CHN 0x00000000
#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
#define STM32_USART3_TX_DMA_CHN 0x00000000
#define STM32_HAS_UART4 FALSE
#define STM32_UART4_RX_DMA_MSK 0
#define STM32_UART4_RX_DMA_CHN 0x00000000
#define STM32_UART4_TX_DMA_MSK 0
#define STM32_UART4_TX_DMA_CHN 0x00000000
#define STM32_HAS_UART5 FALSE
#define STM32_UART5_RX_DMA_MSK 0
#define STM32_UART5_RX_DMA_CHN 0x00000000
#define STM32_UART5_TX_DMA_MSK 0
#define STM32_UART5_TX_DMA_CHN 0x00000000
#define STM32_HAS_USART6 FALSE
#define STM32_USART6_RX_DMA_MSK 0
#define STM32_USART6_RX_DMA_CHN 0x00000000
#define STM32_USART6_TX_DMA_MSK 0
#define STM32_USART6_TX_DMA_CHN 0x00000000
/* USB attributes.*/
#define STM32_HAS_USB FALSE
@ -492,16 +578,16 @@
/**
* @brief PLL multiplier value.
* @note The allowed range is 2...16.
* @note The default value is calculated for a 72MHz system clock from
* @note The default value is calculated for a 24MHz system clock from
* a 8MHz crystal using the PLL.
*/
#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
#define STM32_PLLMUL_VALUE 9
#define STM32_PLLMUL_VALUE 3
#endif
/**
* @brief AHB prescaler value.
* @note The default value is calculated for a 72MHz system clock from
* @note The default value is calculated for a 24MHz system clock from
* a 8MHz crystal using the PLL.
*/
#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
@ -512,35 +598,35 @@
* @brief APB1 prescaler value.
*/
#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
#define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PPRE1 STM32_PPRE1_DIV1
#endif
/**
* @brief APB2 prescaler value.
*/
#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_PPRE2 STM32_PPRE2_DIV1
#endif
/**
* @brief ADC prescaler value.
*/
#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
#define STM32_ADCPRE STM32_ADCPRE_DIV4
#define STM32_ADCPRE STM32_ADCPRE_DIV2
#endif
/**
* @brief MCO pin setting.
*/
#if !defined(STM32_MCO) || defined(__DOXYGEN__)
#define STM32_MCO STM32_MCO_NOCLOCK
#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
#endif
/**
* @brief Clock source selecting. LSI by default.
*/
#if !defined(STM32_RTC) || defined(__DOXYGEN__)
#define STM32_RTC STM32_RTC_LSI
#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
#define STM32_RTCSEL STM32_RTCSEL_LSI
#endif
/** @} */
@ -548,11 +634,110 @@
/* Derived constants and error checks. */
/*===========================================================================*/
/*
* HSI related checks.
*/
#if STM32_HSI_ENABLED
#else /* !STM32_HSI_ENABLED */
#if STM32_SW == STM32_SW_HSI
#error "HSI not enabled, required by STM32_SW"
#endif
#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
#endif
#if (STM32_MCOSEL == STM32_MCOSEL_HSI) || \
((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) && (STM32_PLLSRC == STM32_PLLSRC_HSI))
#error "HSI not enabled, required by STM32_MCOSEL"
#endif
#endif /* !STM32_HSI_ENABLED */
/*
* HSE related checks.
*/
#if STM32_HSE_ENABLED
#if STM32_HSECLK == 0
#error "HSE frequency not defined"
#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
#endif
#else /* !STM32_HSE_ENABLED */
#if STM32_SW == STM32_SW_HSE
#error "HSE not enabled, required by STM32_SW"
#endif
#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
#endif
#if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
((STM32_MCOSEL == STM32_MCOSEL_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE))
#error "HSE not enabled, required by STM32_MCOSEL"
#endif
#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
#error "HSE not enabled, required by STM32_RTCSELSEL"
#endif
#endif /* !STM32_HSE_ENABLED */
/*
* LSI related checks.
*/
#if STM32_LSI_ENABLED
#else /* !STM32_LSI_ENABLED */
#if STM32_RTCSEL == STM32_RTCSEL_LSI
#error "LSI not enabled, required by STM32_RTCSEL"
#endif
#endif /* !STM32_LSI_ENABLED */
/*
* LSE related checks.
*/
#if STM32_LSE_ENABLED
#if (STM32_LSECLK == 0)
#error "LSE frequency not defined"
#endif
#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
#endif
#else /* !STM32_LSE_ENABLED */
#if STM32_RTCSEL == STM32_RTCSEL_LSE
#error "LSE not enabled, required by STM32_RTCSEL"
#endif
#endif /* !STM32_LSE_ENABLED */
/* PLL activation conditions.*/
#if (STM32_SW == STM32_SW_PLL) || \
(STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) || \
defined(__DOXYGEN__)
/**
* @brief PLL activation flag.
*/
#define STM32_ACTIVATE_PLL TRUE
#else
#define STM32_ACTIVATE_PLL FALSE
#endif
/* HSE prescaler setting check.*/
#if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) && \
(STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2)
#error "invalid STM32_PLLXTPRE value specified"
#endif
/**
* @brief PLLMUL field.
*/
@ -579,8 +764,8 @@
#endif
/* PLL input frequency range check.*/
#if (STM32_PLLCLKIN < 1000000) || (STM32_PLLCLKIN > 24000000)
#error "STM32_PLLCLKIN outside acceptable range (1...24MHz)"
#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
#endif
/**
@ -589,8 +774,8 @@
#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
/* PLL output frequency range check.*/
#if (STM32_PLLCLKOUT < 16000000) || (STM32_PLLCLKOUT > 24000000)
#error "STM32_PLLCLKOUT outside acceptable range (16...24MHz)"
#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
#endif
/**
@ -607,8 +792,8 @@
#endif
/* Check on the system clock.*/
#if STM32_SYSCLK > 24000000
#error "STM32_SYSCLK above maximum rated frequency (24MHz)"
#if STM32_SYSCLK > STM32_SYSCLK_MAX
#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
#endif
/**
@ -637,8 +822,8 @@
#endif
/* AHB frequency check.*/
#if STM32_HCLK > 24000000
#error "STM32_HCLK exceeding maximum frequency (24MHz)"
#if STM32_HCLK > STM32_SYSCLK_MAX
#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
#endif
/**
@ -659,8 +844,8 @@
#endif
/* APB1 frequency check.*/
#if STM32_PCLK1 > 24000000
#error "STM32_PCLK1 exceeding maximum frequency (24MHz)"
#if STM32_PCLK1 > STM32_PCLK1_MAX
#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
#endif
/**
@ -681,8 +866,8 @@
#endif
/* APB2 frequency check.*/
#if STM32_PCLK2 > 24000000
#error "STM32_PCLK2 exceeding maximum frequency (24MHz)"
#if STM32_PCLK2 > STM32_PCLK2_MAX
#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
#endif
/**
@ -701,8 +886,8 @@
#endif
/* ADC frequency check.*/
#if STM32_ADCCLK > 12000000
#error "STM32_ADCCLK exceeding maximum frequency (12MHz)"
#if STM32_ADCCLK > STM32_ADCCLK_MAX
#error "STM32_ADCCLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
#endif
/**