diff --git a/os/hal/platforms/STM32/stm32_dma.c b/os/hal/platforms/STM32/stm32_dma.c
index 621659a0b..2232df448 100644
--- a/os/hal/platforms/STM32/stm32_dma.c
+++ b/os/hal/platforms/STM32/stm32_dma.c
@@ -251,6 +251,7 @@ CH_IRQ_HANDLER(DMA2_Ch3_IRQHandler) {
   CH_IRQ_EPILOGUE();
 }
 
+#if defined(STM32F10X_CL) || defined(__DOXYGEN__)
 /**
  * @brief   DMA2 channel 4 shared interrupt handler.
  *
@@ -286,6 +287,39 @@ CH_IRQ_HANDLER(DMA2_Ch5_IRQHandler) {
 
   CH_IRQ_EPILOGUE();
 }
+
+#else /* !STM32F10X_CL */
+/**
+ * @brief   DMA2 channels 4 and 5 shared interrupt handler.
+ * @note    This IRQ is shared between DMA2 channels 4 and 5 so it is a
+ *          bit less efficient because an extra check.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(DMA2_Ch4_5_IRQHandler) {
+  uint32_t isr;
+
+  CH_IRQ_PROLOGUE();
+
+  /* Check on channel 4.*/
+  isr = STM32_DMA2->ISR >> (STM32_DMA_CHANNEL_5 * 4);
+  if (isr & DMA_ISR_GIF1) {
+    dmaClearChannel(STM32_DMA2, STM32_DMA_CHANNEL_5);
+    if (dma2[3].dmaisrfunc)
+      dma2[3].dmaisrfunc(dma2[3].dmaisrparam, isr);
+  }
+
+  /* Check on channel 5.*/
+  isr = STM32_DMA2->ISR >> (STM32_DMA_CHANNEL_4 * 4);
+  if (isr & DMA_ISR_GIF1) {
+    dmaClearChannel(STM32_DMA2, STM32_DMA_CHANNEL_5);
+    if (dma2[4].dmaisrfunc)
+      dma2[4].dmaisrfunc(dma2[4].dmaisrparam, isr);
+  }
+
+  CH_IRQ_EPILOGUE();
+}
+#endif /* !STM32F10X_CL */
 #endif /* STM32_HAS_DMA2 */
 
 /*===========================================================================*/
diff --git a/os/hal/platforms/STM8S/spi_lld.c b/os/hal/platforms/STM8S/spi_lld.c
index f9af72cde..57e459d80 100644
--- a/os/hal/platforms/STM8S/spi_lld.c
+++ b/os/hal/platforms/STM8S/spi_lld.c
@@ -130,8 +130,10 @@ void spi_lld_start(SPIDriver *spip) {
   CLK->PCKENR1 |= CLK_PCKENR1_SPI;              /* PCKEN11, clock source.   */
 
   /* Configuration.*/
-  SPI->CR2 = 0;
-  SPI->CR1 = spip->config->cr1 | SPI_CR1_MSTR | SPI_CR1_SPE;
+  SPI->CR1  = 0;
+  SPI->CR1  = spip->config->cr1 | SPI_CR1_MSTR;
+  SPI->CR2  = SPI_CR2_SSI | SPI_CR2_SSM;
+  SPI->CR1 |= SPI_CR1_SPE;
 }
 
 /**
diff --git a/readme.txt b/readme.txt
index bedf49b1f..956fe764e 100644
--- a/readme.txt
+++ b/readme.txt
@@ -79,6 +79,9 @@
   to 2.2.4).
 - FIX: Fixed wrong macro check for STM32 XL devices (bug 3291898)(backported
   to 2.2.4).
+- FIX: Fixed SPI driver restart in STM32 SPI driver implementation, also
+  applied the same fix to the STM8S SPI driver (bug 3288758)(backported to
+  2.2.4).
 - FIX: Fixed missing state transition in ADC driver (bug 3288149)(backported
   to 2.2.4).
 - FIX: Fixed missing state transition in SPI driver (bug 3288112)(backported