From 1780910ebcd2c59d9c22d1f46317a8e1a55d9aad Mon Sep 17 00:00:00 2001
From: Giovanni Di Sirio <gdisirio@gmail.com>
Date: Sat, 18 Nov 2017 16:19:37 +0000
Subject: [PATCH] git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11030
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/lib/complex/mfs/mfs.h        |  2 +-
 testhal/STM32/multi/QSPI-MFS/main.c | 29 +++++++++++++++--------------
 2 files changed, 16 insertions(+), 15 deletions(-)

diff --git a/os/hal/lib/complex/mfs/mfs.h b/os/hal/lib/complex/mfs/mfs.h
index 0cae31f90..ec9cf4cda 100644
--- a/os/hal/lib/complex/mfs/mfs.h
+++ b/os/hal/lib/complex/mfs/mfs.h
@@ -319,7 +319,7 @@ typedef struct {
   flash_offset_t            used_space;
   /**
    * @brief   Offsets of the most recent instance of the records.
-   * @note    Zero means that ther is not a record with that id.
+   * @note    Zero means that there is not a record with that id.
    */
   mfs_record_descriptor_t   descriptors[MFS_CFG_MAX_RECORDS];
   /**
diff --git a/testhal/STM32/multi/QSPI-MFS/main.c b/testhal/STM32/multi/QSPI-MFS/main.c
index e468c39f3..0be2a81e6 100644
--- a/testhal/STM32/multi/QSPI-MFS/main.c
+++ b/testhal/STM32/multi/QSPI-MFS/main.c
@@ -28,26 +28,27 @@
 
 /* 16MB device, 2 cycles delay after NCS.*/
 const QSPIConfig qspicfg1 = {
-  NULL,
-  STM32_DCR_FSIZE(24) | STM32_DCR_CSHT(1)
+  .end_cb           = NULL,
+  .dcr              = STM32_DCR_FSIZE(24) | STM32_DCR_CSHT(1)
+};
+
+const M25QConfig m25qcfg1 = {
+  .busp             = &QSPID1,
+  .buscfg           = &qspicfg1
 };
 
 M25QDriver m25q;
 
-const M25QConfig m25qcfg1 = {
-  &QSPID1,
-  &qspicfg1
+const MFSConfig mfscfg1 = {
+  .flashp           = (BaseFlash *)&m25q,
+  .erased           = 0xFFFFFFFFU,
+  .bank_size        = 4096U,
+  .bank0_start      = 0U,
+  .bank0_sectors    = 1U,
+  .bank1_start      = 1U,
+  .bank1_sectors    = 1U
 };
 
-const MFSConfig mfscfg1 = {
-  (BaseFlash *)&m25q,
-  0xFFFFFFFFU,
-  4096U,
-  0,
-  2,
-  2,
-  2
-};
 /*
  * LED blinker thread, times are in milliseconds.
  */