Fixed bug 3598720.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4982 35acf78f-673a-0410-8e92-d51de3d6d3f4
2012-12-28 10:41:04 +00:00 · 2012-12-28 10:41:04 +00:00 · 17d265e3ba
parent d38b79b7b2
commit 17d265e3ba
22 changed files with 242 additions and 19 deletions
--- a/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/mcuconf.h
+++ b/demos/ARMCM4-STM32F407-DISCOVERY-MEMS/mcuconf.h
@ -163,6 +163,17 @@
 #define STM32_ICU_TIM5_IRQ_PRIORITY         7
 #define STM32_ICU_TIM8_IRQ_PRIORITY         7

+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS          2
+#define STM32_MAC_RECEIVE_BUFFERS           4
+#define STM32_MAC_BUFFERS_SIZE              1522
+#define STM32_MAC_PHY_TIMEOUT               100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY         13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
+
 /*
 * PWM driver system settings.
 */
--- a/demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h
+++ b/demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h
@ -163,6 +163,17 @@
 #define STM32_ICU_TIM5_IRQ_PRIORITY         7
 #define STM32_ICU_TIM8_IRQ_PRIORITY         7

+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS          2
+#define STM32_MAC_RECEIVE_BUFFERS           4
+#define STM32_MAC_BUFFERS_SIZE              1522
+#define STM32_MAC_PHY_TIMEOUT               100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY         13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
+
 /*
 * PWM driver system settings.
 */
--- a/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/mcuconf.h
+++ b/demos/ARMCM4-STM32F407-LWIP-FATFS-USB/mcuconf.h
@ -163,6 +163,28 @@
 #define STM32_ICU_TIM5_IRQ_PRIORITY         7
 #define STM32_ICU_TIM8_IRQ_PRIORITY         7

+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS          2
+#define STM32_MAC_RECEIVE_BUFFERS           4
+#define STM32_MAC_BUFFERS_SIZE              1522
+#define STM32_MAC_PHY_TIMEOUT               100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY         13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
+
+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS          2
+#define STM32_MAC_RECEIVE_BUFFERS           4
+#define STM32_MAC_BUFFERS_SIZE              1522
+#define STM32_MAC_PHY_TIMEOUT               100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY         13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
+
 /*
 * PWM driver system settings.
 */
--- a/demos/ARMCM4-STM32F407-LWIP/mcuconf.h
+++ b/demos/ARMCM4-STM32F407-LWIP/mcuconf.h
@ -163,6 +163,17 @@
 #define STM32_ICU_TIM5_IRQ_PRIORITY         7
 #define STM32_ICU_TIM8_IRQ_PRIORITY         7

+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS          2
+#define STM32_MAC_RECEIVE_BUFFERS           4
+#define STM32_MAC_BUFFERS_SIZE              1522
+#define STM32_MAC_PHY_TIMEOUT               100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY         13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
+
 /*
 * PWM driver system settings.
 */
--- a/os/hal/platforms/STM32/mac_lld.c
+++ b/os/hal/platforms/STM32/mac_lld.c
@ -272,7 +272,7 @@ void mac_lld_init(void) {
    ;
 #endif

-#if STM32_ETH1_CHANGE_PHY_STATE
+#if STM32_MAC_ETH1_CHANGE_PHY_STATE
  /* PHY in power down mode until the driver will be started.*/
  mii_write(&ETHD1, MII_BMCR, mii_read(&ETHD1, MII_BMCR) | BMCR_PDOWN);
 #endif
@ -306,9 +306,10 @@ void mac_lld_start(MACDriver *macp) {
    ;

  /* ISR vector enabled.*/
-  nvicEnableVector(ETH_IRQn, CORTEX_PRIORITY_MASK(STM32_ETH1_IRQ_PRIORITY));
+  nvicEnableVector(ETH_IRQn,
+                   CORTEX_PRIORITY_MASK(STM32_MAC_ETH1_IRQ_PRIORITY));

-#if STM32_ETH1_CHANGE_PHY_STATE
+#if STM32_MAC_ETH1_CHANGE_PHY_STATE
  /* PHY in power up mode.*/
  mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) & ~BMCR_PDOWN);
 #endif
@ -327,7 +328,7 @@ void mac_lld_start(MACDriver *macp) {
  /* Transmitter and receiver enabled.
     Note that the complete setup of the MAC is performed when the link
     status is detected.*/
-#if STM32_IP_CHECKSUM_OFFLOAD
+#if STM32_MAC_IP_CHECKSUM_OFFLOAD
  ETH->MACCR = ETH_MACCR_IPCO | ETH_MACCR_RE | ETH_MACCR_TE;
 #else
  ETH->MACCR =                  ETH_MACCR_RE | ETH_MACCR_TE;
@ -365,7 +366,7 @@ void mac_lld_start(MACDriver *macp) {
 void mac_lld_stop(MACDriver *macp) {

  if (macp->state != MAC_STOP) {
-#if STM32_ETH1_CHANGE_PHY_STATE
+#if STM32_MAC_ETH1_CHANGE_PHY_STATE
    /* PHY in power down mode until the driver will be restarted.*/
    mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) | BMCR_PDOWN);
 #endif
@ -482,7 +483,7 @@ void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) {

  /* Unlocks the descriptor and returns it to the DMA engine.*/
  tdp->physdesc->tdes1 = tdp->offset;
-  tdp->physdesc->tdes0 = STM32_TDES0_CIC(STM32_IP_CHECKSUM_OFFLOAD) |
+  tdp->physdesc->tdes0 = STM32_TDES0_CIC(STM32_MAC_IP_CHECKSUM_OFFLOAD) |
                         STM32_TDES0_IC | STM32_TDES0_LS | STM32_TDES0_FS |
                         STM32_TDES0_TCH | STM32_TDES0_OWN;

@ -519,9 +520,9 @@ msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
     frames are discarded.*/
  while (!(rdes->rdes0 & STM32_RDES0_OWN)) {
    if (!(rdes->rdes0 & (STM32_RDES0_AFM | STM32_RDES0_ES))
-#if STM32_IP_CHECKSUM_OFFLOAD
-        && !(rdes->rdes0 & STM32_RDES0_FT & (STM32_RDES0_IPHCE |
-                                             STM32_RDES0_PCE))
+#if STM32_MAC_IP_CHECKSUM_OFFLOAD
+        && (rdes->rdes0 & STM32_RDES0_FT)
+        && !(rdes->rdes0 & (STM32_RDES0_IPHCE | STM32_RDES0_PCE))
 #endif
        && (rdes->rdes0 & STM32_RDES0_FS) && (rdes->rdes0 & STM32_RDES0_LS)) {
      /* Found a valid one.*/
--- a/os/hal/platforms/STM32/mac_lld.h
+++ b/os/hal/platforms/STM32/mac_lld.h
@ -124,21 +124,21 @@
 * @brief   Number of available transmit buffers.
 */
 #if !defined(STM32_MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__)
-#define STM32_MAC_TRANSMIT_BUFFERS  2
+#define STM32_MAC_TRANSMIT_BUFFERS          2
 #endif

 /**
 * @brief   Number of available receive buffers.
 */
 #if !defined(STM32_MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__)
-#define STM32_MAC_RECEIVE_BUFFERS   4
+#define STM32_MAC_RECEIVE_BUFFERS           4
 #endif

 /**
 * @brief   Maximum supported frame size.
 */
 #if !defined(STM32_MAC_BUFFERS_SIZE) || defined(__DOXYGEN__)
-#define STM32_MAC_BUFFERS_SIZE      1522
+#define STM32_MAC_BUFFERS_SIZE              1522
 #endif

 /**
@ -151,21 +151,21 @@
 *          single search path is performed.
 */
 #if !defined(STM32_MAC_PHY_TIMEOUT) || defined(__DOXYGEN__)
-#define STM32_MAC_PHY_TIMEOUT       100
+#define STM32_MAC_PHY_TIMEOUT               100
 #endif

 /**
 * @brief   Change the PHY power state inside the driver.
 */
-#if !defined(STM32_ETH1_CHANGE_PHY_STATE) || defined(__DOXYGEN__)
-#define STM32_ETH1_CHANGE_PHY_STATE TRUE
+#if !defined(STM32_MAC_ETH1_CHANGE_PHY_STATE) || defined(__DOXYGEN__)
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
 #endif

 /**
 * @brief   ETHD1 interrupt priority level setting.
 */
-#if !defined(STM32_ETH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ETH1_IRQ_PRIORITY     13
+#if !defined(STM32_MAC_ETH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_MAC_ETH1_IRQ_PRIORITY         13
 #endif

 /**
@ -181,8 +181,8 @@
 *              calculated in hardware.
 *          .
 */
-#if !defined(STM32_IP_CHECKSUM_OFFLOAD) || defined(__DOXYGEN__)
-#define STM32_IP_CHECKSUM_OFFLOAD   0
+#if !defined(STM32_MAC_IP_CHECKSUM_OFFLOAD) || defined(__DOXYGEN__)
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
 #endif
 /** @} */

--- a/readme.txt
+++ b/readme.txt
@ -82,6 +82,8 @@
 *****************************************************************************

 *** 2.5.2 ***
+- FIX: Fixed wrong condition in checksum offload of STM32 MAC driver (bug
+  3598720)(backported to 2.4.4).
 - FIX: Fixed error in STM32 MAC driver degrades performance (bug 3598719)
  (backported to 2.4.4).
 - FIX: Fixed warning in STM32 ICU driver using IAR compiler (bug 3598177)
--- a/testhal/STM32F4xx/ADC/mcuconf.h
+++ b/testhal/STM32F4xx/ADC/mcuconf.h
@ -163,6 +163,17 @@
 #define STM32_ICU_TIM5_IRQ_PRIORITY         7
 #define STM32_ICU_TIM8_IRQ_PRIORITY         7

+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS          2
+#define STM32_MAC_RECEIVE_BUFFERS           4
+#define STM32_MAC_BUFFERS_SIZE              1522
+#define STM32_MAC_PHY_TIMEOUT               100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY         13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
+
 /*
 * PWM driver system settings.
 */
--- a/testhal/STM32F4xx/CAN/mcuconf.h
+++ b/testhal/STM32F4xx/CAN/mcuconf.h
@ -163,6 +163,17 @@
 #define STM32_ICU_TIM5_IRQ_PRIORITY         7
 #define STM32_ICU_TIM8_IRQ_PRIORITY         7

+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS          2
+#define STM32_MAC_RECEIVE_BUFFERS           4
+#define STM32_MAC_BUFFERS_SIZE              1522
+#define STM32_MAC_PHY_TIMEOUT               100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY         13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
+
 /*
 * PWM driver system settings.
 */
--- a/testhal/STM32F4xx/DMA_STORM/mcuconf.h
+++ b/testhal/STM32F4xx/DMA_STORM/mcuconf.h
@ -163,6 +163,17 @@
 #define STM32_ICU_TIM5_IRQ_PRIORITY         7
 #define STM32_ICU_TIM8_IRQ_PRIORITY         7

+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS          2
+#define STM32_MAC_RECEIVE_BUFFERS           4
+#define STM32_MAC_BUFFERS_SIZE              1522
+#define STM32_MAC_PHY_TIMEOUT               100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY         13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
+
 /*
 * PWM driver system settings.
 */
--- a/testhal/STM32F4xx/EXT/mcuconf.h
+++ b/testhal/STM32F4xx/EXT/mcuconf.h
@ -163,6 +163,17 @@
 #define STM32_ICU_TIM5_IRQ_PRIORITY         7
 #define STM32_ICU_TIM8_IRQ_PRIORITY         7

+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS          2
+#define STM32_MAC_RECEIVE_BUFFERS           4
+#define STM32_MAC_BUFFERS_SIZE              1522
+#define STM32_MAC_PHY_TIMEOUT               100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY         13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
+
 /*
 * PWM driver system settings.
 */
--- a/testhal/STM32F4xx/GPT/mcuconf.h
+++ b/testhal/STM32F4xx/GPT/mcuconf.h
@ -163,6 +163,17 @@
 #define STM32_ICU_TIM5_IRQ_PRIORITY         7
 #define STM32_ICU_TIM8_IRQ_PRIORITY         7

+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS          2
+#define STM32_MAC_RECEIVE_BUFFERS           4
+#define STM32_MAC_BUFFERS_SIZE              1522
+#define STM32_MAC_PHY_TIMEOUT               100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY         13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
+
 /*
 * PWM driver system settings.
 */
--- a/testhal/STM32F4xx/I2C/mcuconf.h
+++ b/testhal/STM32F4xx/I2C/mcuconf.h
@ -163,6 +163,17 @@
 #define STM32_ICU_TIM5_IRQ_PRIORITY         7
 #define STM32_ICU_TIM8_IRQ_PRIORITY         7

+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS          2
+#define STM32_MAC_RECEIVE_BUFFERS           4
+#define STM32_MAC_BUFFERS_SIZE              1522
+#define STM32_MAC_PHY_TIMEOUT               100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY         13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
+
 /*
 * PWM driver system settings.
 */
--- a/testhal/STM32F4xx/IRQ_STORM/mcuconf.h
+++ b/testhal/STM32F4xx/IRQ_STORM/mcuconf.h
@ -163,6 +163,17 @@
 #define STM32_ICU_TIM5_IRQ_PRIORITY         7
 #define STM32_ICU_TIM8_IRQ_PRIORITY         7

+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS          2
+#define STM32_MAC_RECEIVE_BUFFERS           4
+#define STM32_MAC_BUFFERS_SIZE              1522
+#define STM32_MAC_PHY_TIMEOUT               100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY         13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
+
 /*
 * PWM driver system settings.
 */
--- a/testhal/STM32F4xx/IRQ_STORM_FPU/mcuconf.h
+++ b/testhal/STM32F4xx/IRQ_STORM_FPU/mcuconf.h
@ -163,6 +163,17 @@
 #define STM32_ICU_TIM5_IRQ_PRIORITY         7
 #define STM32_ICU_TIM8_IRQ_PRIORITY         7

+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS          2
+#define STM32_MAC_RECEIVE_BUFFERS           4
+#define STM32_MAC_BUFFERS_SIZE              1522
+#define STM32_MAC_PHY_TIMEOUT               100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY         13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
+
 /*
 * PWM driver system settings.
 */
--- a/testhal/STM32F4xx/PWM-ICU/mcuconf.h
+++ b/testhal/STM32F4xx/PWM-ICU/mcuconf.h
@ -163,6 +163,17 @@
 #define STM32_ICU_TIM5_IRQ_PRIORITY         7
 #define STM32_ICU_TIM8_IRQ_PRIORITY         7

+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS          2
+#define STM32_MAC_RECEIVE_BUFFERS           4
+#define STM32_MAC_BUFFERS_SIZE              1522
+#define STM32_MAC_PHY_TIMEOUT               100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY         13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
+
 /*
 * PWM driver system settings.
 */
--- a/testhal/STM32F4xx/RTC/mcuconf.h
+++ b/testhal/STM32F4xx/RTC/mcuconf.h
@ -163,6 +163,17 @@
 #define STM32_ICU_TIM5_IRQ_PRIORITY         7
 #define STM32_ICU_TIM8_IRQ_PRIORITY         7

+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS          2
+#define STM32_MAC_RECEIVE_BUFFERS           4
+#define STM32_MAC_BUFFERS_SIZE              1522
+#define STM32_MAC_PHY_TIMEOUT               100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY         13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
+
 /*
 * PWM driver system settings.
 */
--- a/testhal/STM32F4xx/RTC_FATTIME/mcuconf.h
+++ b/testhal/STM32F4xx/RTC_FATTIME/mcuconf.h
@ -163,6 +163,17 @@
 #define STM32_ICU_TIM5_IRQ_PRIORITY         7
 #define STM32_ICU_TIM8_IRQ_PRIORITY         7

+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS          2
+#define STM32_MAC_RECEIVE_BUFFERS           4
+#define STM32_MAC_BUFFERS_SIZE              1522
+#define STM32_MAC_PHY_TIMEOUT               100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY         13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
+
 /*
 * PWM driver system settings.
 */
--- a/testhal/STM32F4xx/SDC/mcuconf.h
+++ b/testhal/STM32F4xx/SDC/mcuconf.h
@ -163,6 +163,17 @@
 #define STM32_ICU_TIM5_IRQ_PRIORITY         7
 #define STM32_ICU_TIM8_IRQ_PRIORITY         7

+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS          2
+#define STM32_MAC_RECEIVE_BUFFERS           4
+#define STM32_MAC_BUFFERS_SIZE              1522
+#define STM32_MAC_PHY_TIMEOUT               100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY         13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
+
 /*
 * PWM driver system settings.
 */
--- a/testhal/STM32F4xx/SPI/mcuconf.h
+++ b/testhal/STM32F4xx/SPI/mcuconf.h
@ -163,6 +163,17 @@
 #define STM32_ICU_TIM5_IRQ_PRIORITY         7
 #define STM32_ICU_TIM8_IRQ_PRIORITY         7

+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS          2
+#define STM32_MAC_RECEIVE_BUFFERS           4
+#define STM32_MAC_BUFFERS_SIZE              1522
+#define STM32_MAC_PHY_TIMEOUT               100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY         13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
+
 /*
 * PWM driver system settings.
 */
--- a/testhal/STM32F4xx/UART/mcuconf.h
+++ b/testhal/STM32F4xx/UART/mcuconf.h
@ -163,6 +163,17 @@
 #define STM32_ICU_TIM5_IRQ_PRIORITY         7
 #define STM32_ICU_TIM8_IRQ_PRIORITY         7

+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS          2
+#define STM32_MAC_RECEIVE_BUFFERS           4
+#define STM32_MAC_BUFFERS_SIZE              1522
+#define STM32_MAC_PHY_TIMEOUT               100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY         13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
+
 /*
 * PWM driver system settings.
 */
--- a/testhal/STM32F4xx/USB_CDC/mcuconf.h
+++ b/testhal/STM32F4xx/USB_CDC/mcuconf.h
@ -163,6 +163,17 @@
 #define STM32_ICU_TIM5_IRQ_PRIORITY         7
 #define STM32_ICU_TIM8_IRQ_PRIORITY         7

+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS          2
+#define STM32_MAC_RECEIVE_BUFFERS           4
+#define STM32_MAC_BUFFERS_SIZE              1522
+#define STM32_MAC_PHY_TIMEOUT               100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY         13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
+
 /*
 * PWM driver system settings.
 */