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ChibiOS
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3810 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2012-01-14 13:30:33 +00:00
parent a41f12ad8a
commit 17f9264b09
4 changed files with 33 additions and 26 deletions
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1
os/hal/platforms/STM32F1xx/hal_lld.c
View File

@ -53,6 +53,7 @@ static void hal_lld_backup_domain_init(void) {
/* Reset BKP domain if different clock source selected.*/ /* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MSK) != STM32_RTCSEL){ if ((RCC->BDCR & STM32_RTCSEL_MSK) != STM32_RTCSEL){
/* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST; RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0; RCC->BDCR = 0;
} }

18
os/hal/platforms/STM32F2xx/hal_lld.c
View File

@ -47,18 +47,20 @@
static void hal_lld_backup_domain_init(void) { static void hal_lld_backup_domain_init(void) {
/* Backup domain access enabled and left open.*/ /* Backup domain access enabled and left open.*/
PWR->CR = PWR_CR_DBP; PWR->CR |= PWR_CR_DBP;
/* If enabled then the LSE is started.*/ /* Reset BKP domain if different clock source selected.*/
#if STM32_LSE_ENABLED if ((RCC->BDCR & STM32_RTCSEL_MSK) != STM32_RTCSEL){
if ((RCC->BDCR & RCC_BDCR_LSEON) == 0) {
/* Backup domain reset.*/ /* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST; RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0; RCC->BDCR = 0;
RCC->BDCR = RCC_BDCR_LSEON;
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Waits until LSE is stable. */
} }
/* If enabled then the LSE is started.*/
#if STM32_LSE_ENABLED
RCC->BDCR |= RCC_BDCR_LSEON;
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Waits until LSE is stable. */
#endif #endif
#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK #if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
@ -66,7 +68,7 @@ static void hal_lld_backup_domain_init(void) {
initialization.*/ initialization.*/
if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) { if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
/* Selects clock source.*/ /* Selects clock source.*/
RCC->BDCR = (RCC->BDCR & ~RCC_BDCR_RTCSEL) | STM32_RTCSEL; RCC->BDCR |= STM32_RTCSEL;
/* RTC clock enabled.*/ /* RTC clock enabled.*/
RCC->BDCR |= RCC_BDCR_RTCEN; RCC->BDCR |= RCC_BDCR_RTCEN;

18
os/hal/platforms/STM32F4xx/hal_lld.c
View File

@ -47,18 +47,20 @@
static void hal_lld_backup_domain_init(void) { static void hal_lld_backup_domain_init(void) {
/* Backup domain access enabled and left open.*/ /* Backup domain access enabled and left open.*/
PWR->CR = PWR_CR_DBP; PWR->CR |= PWR_CR_DBP;
/* If enabled then the LSE is started.*/ /* Reset BKP domain if different clock source selected.*/
#if STM32_LSE_ENABLED if ((RCC->BDCR & STM32_RTCSEL_MSK) != STM32_RTCSEL){
if ((RCC->BDCR & RCC_BDCR_LSEON) == 0) {
/* Backup domain reset.*/ /* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST; RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0; RCC->BDCR = 0;
RCC->BDCR = RCC_BDCR_LSEON;
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Waits until LSE is stable. */
} }
/* If enabled then the LSE is started.*/
#if STM32_LSE_ENABLED
RCC->BDCR |= RCC_BDCR_LSEON;
while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
; /* Waits until LSE is stable. */
#endif #endif
#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK #if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
@ -66,7 +68,7 @@ static void hal_lld_backup_domain_init(void) {
initialization.*/ initialization.*/
if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) { if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
/* Selects clock source.*/ /* Selects clock source.*/
RCC->BDCR = (RCC->BDCR & ~RCC_BDCR_RTCSEL) | STM32_RTCSEL; RCC->BDCR |= STM32_RTCSEL;
/* RTC clock enabled.*/ /* RTC clock enabled.*/
RCC->BDCR |= RCC_BDCR_RTCEN; RCC->BDCR |= RCC_BDCR_RTCEN;

22
os/hal/platforms/STM32L1xx/hal_lld.c
View File

@ -47,18 +47,20 @@
static void hal_lld_backup_domain_init(void) { static void hal_lld_backup_domain_init(void) {
/* Backup domain access enabled and left open.*/ /* Backup domain access enabled and left open.*/
PWR->CR = PWR_CR_DBP; PWR->CR |= PWR_CR_DBP;
/* If enabled then the LSE is started.*/ /* Reset BKP domain if different clock source selected.*/
#if STM32_LSE_ENABLED if ((RCC->CSR & STM32_RTCSEL_MSK) != STM32_RTCSEL){
if ((RCC->CSR & RCC_CSR_LSEON) == 0) {
/* Backup domain reset.*/ /* Backup domain reset.*/
RCC->CSR |= RCC_CSR_RTCRST; RCC->CSR |= RCC_CSR_RTCRST;
RCC->CSR &= ~RCC_CSR_RTCRST; RCC->CSR &= ~RCC_CSR_RTCRST;
RCC->CSR |= RCC_CSR_LSEON;
while ((RCC->CSR & RCC_CSR_LSERDY) == 0)
; /* Waits until LSE is stable. */
} }
/* If enabled then the LSE is started.*/
#if STM32_LSE_ENABLED
RCC->CSR |= RCC_CSR_LSEON;
while ((RCC->CSR & RCC_CSR_LSERDY) == 0)
; /* Waits until LSE is stable. */
#endif #endif
#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK #if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
@ -66,7 +68,7 @@ static void hal_lld_backup_domain_init(void) {
initialization.*/ initialization.*/
if ((RCC->CSR & RCC_CSR_RTCEN) == 0) { if ((RCC->CSR & RCC_CSR_RTCEN) == 0) {
/* Selects clock source.*/ /* Selects clock source.*/
RCC->CSR = (RCC->CSR & ~RCC_CSR_RTCSEL) | STM32_RTCSEL; RCC->CSR |= STM32_RTCSEL;
/* RTC clock enabled.*/ /* RTC clock enabled.*/
RCC->CSR |= RCC_CSR_RTCEN; RCC->CSR |= RCC_CSR_RTCEN;
@ -200,7 +202,7 @@ void stm32_clock_init(void) {
STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE; STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
RCC->CSR |= STM32_RTCSEL; RCC->CSR |= STM32_RTCSEL;
/* Flash setup and final clock selection. */ /* Flash setup and final clock selection.*/
#if defined(STM32_FLASHBITS1) #if defined(STM32_FLASHBITS1)
FLASH->ACR = STM32_FLASHBITS1; FLASH->ACR = STM32_FLASHBITS1;
#endif #endif
@ -210,7 +212,7 @@ void stm32_clock_init(void) {
/* Switching to the configured clock source if it is different from MSI.*/ /* Switching to the configured clock source if it is different from MSI.*/
#if (STM32_SW != STM32_SW_MSI) #if (STM32_SW != STM32_SW_MSI)
RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
; ;
#endif #endif