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ChibiOS
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More H5 code, clock tree almost complete. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@16371 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2023-08-11 11:07:43 +00:00
parent c7b3abea41
commit 1825e08571
12 changed files with 591 additions and 386 deletions
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14
demos/STM32/RT-STM32H563ZI-NUCLEO144/Makefile
View File

@ -99,13 +99,13 @@ include $(CHIBIOS)/os/license/license.mk
# Startup files.
include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32h5xx.mk
# HAL-OSAL files (optional).
#include $(CHIBIOS)/os/hal/hal.mk
#include $(CHIBIOS)/os/hal/ports/STM32/STM32L5xx/platform.mk
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/hal/ports/STM32/STM32H5xx/platform.mk
#include $(CHIBIOS)/os/hal/boards/ST_NUCLEO144_H563ZI/board.mk
#include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk
include $(CHIBIOS)/os/hal/osal/rt-nil/osal.mk
# RTOS files (optional).
#include $(CHIBIOS)/os/rt/rt.mk
#include $(CHIBIOS)/os/common/ports/ARMv8-M-ML/compilers/GCC/mk/port.mk
include $(CHIBIOS)/os/rt/rt.mk
include $(CHIBIOS)/os/common/ports/ARMv8-M-ML/compilers/GCC/mk/port.mk
# Auto-build files in ./source recursively.
include $(CHIBIOS)/tools/mk/autobuild.mk
# Other files (optional).
@ -150,10 +150,10 @@ CPPWARN = -Wall -Wextra -Wundef
#
# List all user C define here, like -D_DEBUG=1
UDEFS = -DSTM32H563xx
UDEFS =
# Define ASM defines here
UADEFS = -DSTM32H563xx
UADEFS =
# List all user directories here
UINCDIR =

2
demos/STM32/RT-STM32H563ZI-NUCLEO144/cfg/halconf.h
View File

@ -142,7 +142,7 @@
* @brief Enables the SERIAL subsystem.
*/
#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL TRUE
#define HAL_USE_SERIAL FALSE
#endif
/**

44
demos/STM32/RT-STM32H563ZI-NUCLEO144/cfg/mcuconf.h
View File

@ -40,12 +40,12 @@
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_CLOCK_DYNAMIC TRUE
#define STM32_CLOCK_DYNAMIC FALSE
/*
* PWR settings.
*/
#define STM32_PWR_VOSCR STM32_VOS_RANGE3
#define STM32_PWR_VOSCR STM32_VOS_RANGE0
#define STM32_PWR_BDCR (0U)
#define STM32_PWR_UCPDR (0U)
#define STM32_PWR_SCCR (0U)
@ -66,24 +66,24 @@
#define STM32_HSE_ENABLED FALSE
#define STM32_LSI_ENABLED FALSE
#define STM32_LSE_ENABLED FALSE
#define STM32_SW STM32_SW_PLL1PCLK
#define STM32_SW STM32_SW_PLL1P
#define STM32_PLL1SRC STM32_PLL1SRC_HSI
#define STM32_PLL1M_VALUE 4
#define STM32_PLL1N_VALUE 84
#define STM32_PLL1P_VALUE 7
#define STM32_PLL1Q_VALUE 8
#define STM32_PLL1M_VALUE 16
#define STM32_PLL1N_VALUE 250
#define STM32_PLL1P_VALUE 2
#define STM32_PLL1Q_VALUE 2
#define STM32_PLL1R_VALUE 2
#define STM32_PLL2SRC STM32_PLL2SRC_HSI
#define STM32_PLL2M_VALUE 4
#define STM32_PLL2N_VALUE 84
#define STM32_PLL2P_VALUE 7
#define STM32_PLL2Q_VALUE 8
#define STM32_PLL2M_VALUE 16
#define STM32_PLL2N_VALUE 250
#define STM32_PLL2P_VALUE 2
#define STM32_PLL2Q_VALUE 2
#define STM32_PLL2R_VALUE 2
#define STM32_PLL3SRC STM32_PLL3SRC_HSI
#define STM32_PLL3M_VALUE 4
#define STM32_PLL3N_VALUE 84
#define STM32_PLL3P_VALUE 7
#define STM32_PLL3Q_VALUE 8
#define STM32_PLL3M_VALUE 16
#define STM32_PLL3N_VALUE 250
#define STM32_PLL3P_VALUE 2
#define STM32_PLL3Q_VALUE 2
#define STM32_PLL3R_VALUE 2
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV1
@ -94,7 +94,7 @@
#define STM32_RTCPRE_VALUE STM32_RTCPRE_NOCLOCK
#define STM32_MCO1SEL STM32_MCO1SEL_HSI
#define STM32_MCO1PRE_VALUE STM32_MCO1PRE_NOCLOCK
#define STM32_MCO2SEL STM32_MCO2SEL_CSI
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE_VALUE STM32_MCO2PRE_NOCLOCK
#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
@ -113,10 +113,10 @@
#define STM32_USART10SEL STM32_USART10SEL_PCLK1
#define STM32_USART11SEL STM32_USART11SEL_PCLK1
#define STM32_UART12SEL STM32_UART12SEL_PCLK1
#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK3
#define STM32_TIMICSEL STM32_TIMICSEL_NOCLK
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK3
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK3
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#define STM32_LPTIM3SEL STM32_LPTIM3SEL_PCLK3
#define STM32_LPTIM4SEL STM32_LPTIM4SEL_PCLK3
#define STM32_LPTIM5SEL STM32_LPTIM5SEL_PCLK3
@ -138,10 +138,10 @@
#define STM32_I2C4SEL STM32_I2C4SEL_PCLK3
#define STM32_I3C1SEL STM32_I3C1SEL_PCLK1
#define STM32_ADCDACSEL STM32_ADCDACSEL_HCLK
#define STM32_DACSEL STM32_DACSEL_LSI
#define STM32_RNGSEL STM32_RNGSEL_HSI48
#define STM32_CECSEL STM32_CECSEL_LSE
#define STM32_FDCANSEL STM32_FDCANSEL_HSE
#define STM32_DACSEL STM32_DACSEL_IGNORE
#define STM32_RNGSEL STM32_RNGSEL_IGNORE
#define STM32_CECSEL STM32_CECSEL_IGNORE
#define STM32_FDCANSEL STM32_FDCANSEL_IGNORE
#define STM32_SAI1SEL STM32_SAI1SEL_PLL1Q
#define STM32_SAI2SEL STM32_SAI2SEL_PLL1Q
#define STM32_CKPERSEL STM32_CKPERSEL_HSI

7
os/hal/ports/STM32/LLD/RCCv1/stm32_ahb.inc
View File

@ -30,8 +30,15 @@
* @name HPRE field bits definitions
* @{
*/
#if defined(RCC_CFGR_HPRE_Pos)
#define STM32_HPRE_MASK (15U << RCC_CFGR_HPRE_Pos)
#define STM32_HPRE_FIELD(n) ((n) << RCC_CFGR_HPRE_Pos)
#elif defined(RCC_CFGR2_HPRE_Pos)
#define STM32_HPRE_MASK (15U << RCC_CFGR2_HPRE_Pos)
#define STM32_HPRE_FIELD(n) ((n) << RCC_CFGR2_HPRE_Pos)
#else
#error "unknown register name"
#endif
#define STM32_HPRE_DIV1 STM32_HPRE_FIELD(0U)
#define STM32_HPRE_DIV2 STM32_HPRE_FIELD(8U)
#define STM32_HPRE_DIV4 STM32_HPRE_FIELD(9U)

6
os/hal/ports/STM32/LLD/RCCv1/stm32_bd.inc
View File

@ -76,7 +76,13 @@ __STATIC_INLINE void bd_reset(void) {
/* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/
#if defined(RCC_BDCR_BDRST)
RCC->BDCR = RCC_BDCR_BDRST;
#elif defined(RCC_BDCR_VSWRST)
RCC->BDCR = RCC_BDCR_VSWRST;
#else
#error "unknown bit name"
#endif
RCC->BDCR = 0U;
}
}

37
os/hal/ports/STM32/LLD/RCCv1/stm32_pll1.inc
View File

@ -29,6 +29,8 @@
/**
* @name PLL helpers
*/
#define STM32_PLL1VCOSEL_WIDE (0U << RCC_PLL1CFGR_PLL1VCOSEL_Pos)
#define STM32_PLL1VCOSEL_MEDIUM (1U << RCC_PLL1CFGR_PLL1VCOSEL_Pos)
#define STM32_PLL1RGE_0 (0U << RCC_PLL1CFGR_PLL1RGE_Pos)
#define STM32_PLL1RGE_1 (1U << RCC_PLL1CFGR_PLL1RGE_Pos)
#define STM32_PLL1RGE_2 (2U << RCC_PLL1CFGR_PLL1RGE_Pos)
@ -223,21 +225,35 @@
*/
#define STM32_PLL1CLKIN (STM32_PLL1IN / STM32_PLL1M_VALUE)
/**
* @brief PLL comparator input frequency.
*/
#if STM32_PLL1CLKIN < STM32_PLLIN_MIN
#error "STM32_PLL1CLKIN below acceptable range"
#elif STM32_PLL1CLKIN > STM32_PLLIN_MAX
#error "STM32_PLL1CLKIN above acceptable range"
#elif (STM32_PLL1CLKIN < STM32_PLLIN_THRESHOLD1) || defined(__DOXYGEN__)
#define STM32_PLL1RGE STM32_PLL1RGE_0
#define STM32_PLL1VCOSEL STM32_PLL1VCOSEL_MEDIUM
#define STM32_PLL1VCO_MIN STM32_PLLVCO_MEDIUM_MIN
#define STM32_PLL1VCO_MAX STM32_PLLVCO_MEDIUM_MAX
#elif STM32_PLL1CLKIN < STM32_PLLIN_THRESHOLD2
#define STM32_PLL1RGE STM32_PLL1RGE_1
#define STM32_PLL1VCOSEL STM32_PLL1VCOSEL_WIDE
#define STM32_PLL1VCO_MIN STM32_PLLVCO_WIDE_MIN
#define STM32_PLL1VCO_MAX STM32_PLLVCO_WIDE_MAX
#elif STM32_PLL1CLKIN < STM32_PLLIN_THRESHOLD3
#define STM32_PLL1RGE STM32_PLL1RGE_2
#define STM32_PLL1VCOSEL STM32_PLL1VCOSEL_WIDE
#define STM32_PLL1VCO_MIN STM32_PLLVCO_WIDE_MIN
#define STM32_PLL1VCO_MAX STM32_PLLVCO_WIDE_MAX
#else
#define STM32_PLL1RGE STM32_PLL1RGE_3
#define STM32_PLL1VCOSEL STM32_PLL1VCOSEL_WIDE
#define STM32_PLL1VCO_MIN STM32_PLLVCO_WIDE_MIN
#define STM32_PLL1VCO_MAX STM32_PLLVCO_WIDE_MAX
#endif
/**
@ -255,13 +271,13 @@
/**
* @brief PLL1 VCO frequency.
*/
#define STM32_PLL1VCO (STM32_PLL1IN * STM32_PLL1N_VALUE)
#define STM32_PLL1VCO (STM32_PLL1CLKIN * STM32_PLL1N_VALUE)
/*
* PLL1 VCO frequency range check.
*/
#if STM32_ACTIVATE_PLL1 && \
((STM32_PLL1VCO < STM32_PLLVCO_MIN) || (STM32_PLL1VCO > STM32_PLLVCO_MAX))
((STM32_PLL1VCO < STM32_PLL1VCO_MIN) || (STM32_PLL1VCO > STM32_PLL1VCO_MAX))
#error "STM32_PLL1VCO outside acceptable range (STM32_PLL1VCO_MIN...STM32_PLL1VCO_MAX)"
#endif
@ -410,11 +426,12 @@ __STATIC_INLINE void pll1_init(void) {
#if STM32_RCC_HAS_PLL1
#if STM32_ACTIVATE_PLL1
/* PLL1 activation.*/
RCC->PLL1CFGR = STM32_PLL1REN | STM32_PLL1QEN |
STM32_PLL1PEN | STM32_PLL1M |
STM32_PLL1RGE | STM32_PLL1SRC; /* TODO PLL1VCOSEL, PLL1FRACEN */
RCC->PLL1DIVR = STM32_PLL1R | STM32_PLL1Q |
STM32_PLL1P | STM32_PLL1N;
RCC->PLL1CFGR = STM32_PLL1REN | STM32_PLL1QEN |
STM32_PLL1PEN | STM32_PLL1M |
STM32_PLL1RGE | STM32_PLL1VCOSEL |
STM32_PLL1SRC; /* TODO PLL1FRACEN */
RCC->PLL1DIVR = STM32_PLL1R | STM32_PLL1Q |
STM32_PLL1P | STM32_PLL1N;
RCC->CR |= RCC_CR_PLL1ON;
pll1_wait_lock();

303
os/hal/ports/STM32/LLD/RCCv1/stm32_pll2.inc
View File

@ -26,6 +26,17 @@
/* Driver local definitions. */
/*===========================================================================*/
/**
* @name PLL helpers
*/
#define STM32_PLL2VCOSEL_WIDE (0U << RCC_PLL2CFGR_PLL2VCOSEL_Pos)
#define STM32_PLL2VCOSEL_MEDIUM (1U << RCC_PLL2CFGR_PLL2VCOSEL_Pos)
#define STM32_PLL2RGE_0 (0U << RCC_PLL2CFGR_PLL2RGE_Pos)
#define STM32_PLL2RGE_1 (1U << RCC_PLL2CFGR_PLL2RGE_Pos)
#define STM32_PLL2RGE_2 (2U << RCC_PLL2CFGR_PLL2RGE_Pos)
#define STM32_PLL2RGE_3 (3U << RCC_PLL2CFGR_PLL2RGE_Pos)
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
@ -74,48 +85,109 @@
#error "STM32_PLL2R_VALUE not defined in mcuconf.h"
#endif
/* Check on valid values.*/
#if !defined(STM32_PLL2M_VALUE_MAX)
#error "STM32_PLL2M_VALUE_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL2M_VALUE_MIN)
#error "STM32_PLL2M_VALUE_MIN not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL2N_ODDVALID)
#error "STM32_PLL2N_ODDVALID not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL2N_VALUE_MAX)
#error "STM32_PLL2N_VALUE_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL2N_VALUE_MIN)
#error "STM32_PLL2N_VALUE_MIN not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL2P_ODDVALID)
#error "STM32_PLL2P_ODDVALID not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL2P_VALUE_MAX)
#error "STM32_PLL2P_VALUE_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL2P_VALUE_MIN)
#error "STM32_PLL2P_VALUE_MIN not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL2Q_ODDVALID)
#error "STM32_PLL2Q_ODDVALID not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL2Q_VALUE_MAX)
#error "STM32_PLL2Q_VALUE_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL2Q_VALUE_MIN)
#error "STM32_PLL2Q_VALUE_MIN not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL2R_ODDVALID)
#error "STM32_PLL2R_ODDVALID not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL2R_VALUE_MAX)
#error "STM32_PLL2R_VALUE_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL2R_VALUE_MIN)
#error "STM32_PLL2R_VALUE_MIN not defined in hal_lld.h"
#endif
/* Check on limits.*/
#if !defined(STM32_PLL2IN_MAX)
#error "STM32_PLL2IN_MAX not defined in hal_lld.h"
#if !defined(STM32_PLLIN_MAX)
#error "STM32_PLLIN_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL2IN_MIN)
#error "STM32_PLL2IN_MIN not defined in hal_lld.h"
#if !defined(STM32_PLLIN_MIN)
#error "STM32_PLLIN_MIN not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL2VCO_MAX)
#error "STM32_PLL2VCO_MAX not defined in hal_lld.h"
#if !defined(STM32_PLLVCO_MAX)
#error "STM32_PLLVCO_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL2VCO_MIN)
#error "STM32_PLL2VCO_MIN not defined in hal_lld.h"
#if !defined(STM32_PLLVCO_MIN)
#error "STM32_PLLVCO_MIN not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL2P_MAX)
#error "STM32_PLL2P_MAX not defined in hal_lld.h"
#if !defined(STM32_PLLP_MAX)
#error "STM32_PLLP_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL2P_MIN)
#error "STM32_PLL2P_MIN not defined in hal_lld.h"
#if !defined(STM32_PLLP_MIN)
#error "STM32_PLLP_MIN not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL2Q_MAX)
#error "STM32_PLL2Q_MAX not defined in hal_lld.h"
#if !defined(STM32_PLLQ_MAX)
#error "STM32_PLLQ_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL2Q_MIN)
#error "STM32_PLL2Q_MIN not defined in hal_lld.h"
#if !defined(STM32_PLLQ_MIN)
#error "STM32_PLLQ_MIN not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL2R_MAX)
#error "STM32_PLL2R_MAX not defined in hal_lld.h"
#if !defined(STM32_PLLR_MAX)
#error "STM32_PLLR_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL2R_MIN)
#error "STM32_PLL2R_MIN not defined in hal_lld.h"
#if !defined(STM32_PLLR_MIN)
#error "STM32_PLLR_MIN not defined in hal_lld.h"
#endif
/* Input checks.*/
#if !defined(STM32_PLL2IN)
#error "STM32_PLL2IN not defined in hal_lld.h"
#endif
#if !defined(STM32_ACTIVATE_PLL2)
#error "STM32_ACTIVATE_PLL2 not defined in hal_lld.h"
#endif
@ -132,19 +204,15 @@
#error "STM32_PLL2REN not defined in hal_lld.h"
#endif
#if STM32_ACTIVATE_PLL2 && (STM32_PLL2CLKIN == 0)
#if STM32_ACTIVATE_PLL2 && (STM32_PLL2IN == 0)
#error "PLL2 activation required but no PLL2 clock selected"
#endif
#if (STM32_PLL2CLKIN != 0) && \
((STM32_PLL2CLKIN < STM32_PLL2IN_MIN) || (STM32_PLL2CLKIN > STM32_PLL2IN_MAX))
#error "STM32_PLL2CLKIN outside acceptable range (STM32_PLL2IN_MIN...STM32_PLL2IN_MAX)"
#endif
/**
* @brief STM32_PLL2M field.
*/
#if ((STM32_PLL2M_VALUE >= 1) && (STM32_PLL2M_VALUE <= 16)) || \
#if ((STM32_PLL2M_VALUE >= STM32_PLL2M_VALUE_MIN) && \
(STM32_PLL2M_VALUE <= STM32_PLL2M_VALUE_MAX)) || \
defined(__DOXYGEN__)
#define STM32_PLL2M ((STM32_PLL2M_VALUE - 1U) << RCC_PLL2CFGR_PLL2M_Pos)
@ -152,12 +220,49 @@
#error "invalid STM32_PLL2M_VALUE value specified"
#endif
/**
* @brief PLL comparator input frequency.
*/
#define STM32_PLL2CLKIN (STM32_PLL2IN / STM32_PLL2M_VALUE)
#if STM32_PLL2CLKIN < STM32_PLLIN_MIN
#error "STM32_PLL2CLKIN below acceptable range"
#elif STM32_PLL2CLKIN > STM32_PLLIN_MAX
#error "STM32_PLL2CLKIN above acceptable range"
#elif (STM32_PLL2CLKIN < STM32_PLLIN_THRESHOLD1) || defined(__DOXYGEN__)
#define STM32_PLL2RGE STM32_PLL2RGE_0
#define STM32_PLL2VCOSEL STM32_PLL2VCOSEL_MEDIUM
#define STM32_PLL2VCO_MIN STM32_PLLVCO_MEDIUM_MIN
#define STM32_PLL2VCO_MAX STM32_PLLVCO_MEDIUM_MAX
#elif STM32_PLL2CLKIN < STM32_PLLIN_THRESHOLD2
#define STM32_PLL2RGE STM32_PLL2RGE_1
#define STM32_PLL2VCOSEL STM32_PLL2VCOSEL_WIDE
#define STM32_PLL2VCO_MIN STM32_PLLVCO_WIDE_MIN
#define STM32_PLL2VCO_MAX STM32_PLLVCO_WIDE_MAX
#elif STM32_PLL2CLKIN < STM32_PLLIN_THRESHOLD3
#define STM32_PLL2RGE STM32_PLL2RGE_2
#define STM32_PLL2VCOSEL STM32_PLL2VCOSEL_WIDE
#define STM32_PLL2VCO_MIN STM32_PLLVCO_WIDE_MIN
#define STM32_PLL2VCO_MAX STM32_PLLVCO_WIDE_MAX
#else
#define STM32_PLL2RGE STM32_PLL2RGE_3
#define STM32_PLL2VCOSEL STM32_PLL2VCOSEL_WIDE
#define STM32_PLL2VCO_MIN STM32_PLLVCO_WIDE_MIN
#define STM32_PLL2VCO_MAX STM32_PLLVCO_WIDE_MAX
#endif
/**
* @brief STM32_PLL2N field.
*/
#if ((STM32_PLL2N_VALUE >= 8) && (STM32_PLL2N_VALUE <= 127)) || \
#if ((STM32_PLL2N_VALUE >= STM32_PLL2N_VALUE_MIN) && \
(STM32_PLL2N_VALUE <= STM32_PLL2N_VALUE_MAX)) || \
defined(__DOXYGEN__)
#define STM32_PLL2N (STM32_PLL2N_VALUE << RCC_PLL2CFGR_PLL2N_Pos)
#define STM32_PLL2N (STM32_PLL2N_VALUE << RCC_PLL2DIVR_PLL2N_Pos)
#else
#error "invalid STM32_PLL2N_VALUE value specified"
@ -180,137 +285,114 @@
/* P output, if present. */
/*---------------------------------------------------------------------------*/
#if STM32_RCC_PLL2_HAS_P || defined(__DOXYGEN__)
#if !STM32_PLL2P_ODDVALID && ((STM32_PLL2P_VALUE & 1) != 0)
#error "odd STM32_PLL2P_VALUE value specified"
#endif
/**
* @brief STM32_PLL2P field.
*/
#if (STM32_PLL2P_VALUE == 7) || defined(__DOXYGEN__)
#define STM32_PLL2P (0U << RCC_PLL2CFGR_PLL2P_Pos)
#elif STM32_PLL2P_VALUE == 17
#define STM32_PLL2P (1U << RCC_PLL2CFGR_PLL2P_Pos)
#else
#error "invalid STM32_PLL2P_VALUE value specified"
#endif
/* PDIV is not present on all devices.*/
#if defined(RCC_PLL2CFGR_PLL2PDIV_Pos) || defined(__DOXYGEN__)
/**
* @brief STM32_PLL2PDIV field.
*/
#if (STM32_PLL2PDIV_VALUE == 0) || \
((STM32_PLL2PDIV_VALUE >= 2) && (STM32_PLL2PDIV_VALUE <= 31)) || \
#if ((STM32_PLL2P_VALUE >= STM32_PLL2P_VALUE_MIN) && \
(STM32_PLL2P_VALUE <= STM32_PLL2P_VALUE_MAX)) || \
defined(__DOXYGEN__)
#define STM32_PLL2PDIV (STM32_PLL2PDIV_VALUE << RCC_PLL2CFGR_PLL2PDIV_Pos)
#define STM32_PLL2P ((STM32_PLL2P_VALUE - 1) << RCC_PLL2DIVR_PLL2P_Pos)
#else
#error "invalid STM32_PLL2PDIV_VALUE value specified"
#error "out of range STM32_PLL2P_VALUE value specified"
#endif
/**
* @brief PLL2 P output clock frequency.
* @brief PLL2P output clock frequency.
*/
#if (STM32_PLL2PDIV_VALUE == 0) || defined(__DOXYGEN__)
#define STM32_PLL2_P_CLKOUT (STM32_PLL2VCO / STM32_PLL2P_VALUE)
#else
#define STM32_PLL2_P_CLKOUT (STM32_PLL2VCO / STM32_PLL2PDIV_VALUE)
#endif
#else
#define STM32_PLL2_P_CLKOUT (STM32_PLL2VCO / STM32_PLL2P_VALUE)
#define STM32_PLL2PDIV 0U
#endif
/*
* PLL2-P output frequency range check.
* PLL2P output frequency range check.
*/
#if STM32_ACTIVATE_PLL2 && \
((STM32_PLL2_P_CLKOUT < STM32_PLL2P_MIN) || (STM32_PLL2_P_CLKOUT > STM32_PLL2P_MAX))
#error "STM32_PLL2_P_CLKOUT outside acceptable range (STM32_PLL2P_MIN...STM32_PLL2P_MAX)"
((STM32_PLL2_P_CLKOUT < STM32_PLLP_MIN) || \
(STM32_PLL2_P_CLKOUT > STM32_PLLP_MAX))
#error "STM32_PLL2_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)"
#endif
#else /* !STM32_RCC_PLL2_HAS_P */
#define STM32_PLL2P 0U
#define STM32_PLL2PDIV 0U
#define STM32_PLL2P 0
#endif /* !STM32_RCC_PLL2_HAS_P */
/*---------------------------------------------------------------------------*/
/* Q output, if present. */
/*---------------------------------------------------------------------------*/
#if STM32_RCC_PLL2_HAS_Q || defined(__DOXYGEN__)
/**
* @brief STM32_PLL2Q field.
*/
#if (STM32_PLL2Q_VALUE == 2) || defined(__DOXYGEN__)
#define STM32_PLL2Q (0U << RCC_PLL2CFGR_PLL2Q_Pos)
#elif STM32_PLL2Q_VALUE == 4
#define STM32_PLL2Q (1U << RCC_PLL2CFGR_PLL2Q_Pos)
#elif STM32_PLL2Q_VALUE == 6
#define STM32_PLL2Q (2U << RCC_PLL2CFGR_PLL2Q_Pos)
#elif STM32_PLL2Q_VALUE == 8
#define STM32_PLL2Q (3U << RCC_PLL2CFGR_PLL2Q_Pos)
#else
#error "invalid STM32_PLL2Q_VALUE value specified"
#if !STM32_PLL2Q_ODDVALID && ((STM32_PLL2Q_VALUE & 1) != 0)
#error "odd STM32_PLL2Q_VALUE value specified"
#endif
/**
* @brief PLL2 Q output clock frequency.
* @brief STM32_PLL2Q field.
*/
#if ((STM32_PLL2Q_VALUE >= STM32_PLL2Q_VALUE_MIN) && \
(STM32_PLL2Q_VALUE <= STM32_PLL2Q_VALUE_MAX)) || \
defined(__DOXYGEN__)
#define STM32_PLL2Q ((STM32_PLL2Q_VALUE - 1) << RCC_PLL2DIVR_PLL2Q_Pos)
#else
#error "out of range STM32_PLL2Q_VALUE value specified"
#endif
/**
* @brief PLL2Q output clock frequency.
*/
#define STM32_PLL2_Q_CLKOUT (STM32_PLL2VCO / STM32_PLL2Q_VALUE)
/*
* PLL2-Q output frequency range check.
* PLL2P output frequency range check.
*/
#if STM32_ACTIVATE_PLL2 && \
((STM32_PLL2_Q_CLKOUT < STM32_PLL2Q_MIN) || (STM32_PLL2_Q_CLKOUT > STM32_PLL2Q_MAX))
#error "STM32_PLL2_Q_CLKOUT outside acceptable range (STM32_PLL2Q_MIN...STM32_PLL2Q_MAX)"
((STM32_PLL2_Q_CLKOUT < STM32_PLLQ_MIN) || \
(STM32_PLL2_Q_CLKOUT > STM32_PLLQ_MAX))
#error "STM32_PLL2_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)"
#endif
#else /* !STM32_RCC_PLL2_HAS_Q */
#define STM32_PLL2Q 0U
#define STM32_PLL2Q 0
#endif /* !STM32_RCC_PLL2_HAS_Q */
/*---------------------------------------------------------------------------*/
/* R output, if present. */
/*---------------------------------------------------------------------------*/
#if STM32_RCC_PLL2_HAS_R || defined(__DOXYGEN__)
/**
* @brief STM32_PLL2R field.
*/
#if (STM32_PLL2R_VALUE == 2) || defined(__DOXYGEN__)
#define STM32_PLL2R (0U << RCC_PLL2CFGR_PLL2R_Pos)
#elif STM32_PLL2R_VALUE == 4
#define STM32_PLL2R (1U << RCC_PLL2CFGR_PLL2R_Pos)
#elif STM32_PLL2R_VALUE == 6
#define STM32_PLL2R (2U << RCC_PLL2CFGR_PLL2R_Pos)
#elif STM32_PLL2R_VALUE == 8
#define STM32_PLL2R (3U << RCC_PLL2CFGR_PLL2R_Pos)
#else
#error "invalid STM32_PLL2R_VALUE value specified"
#if !STM32_PLL2R_ODDVALID && ((STM32_PLL2R_VALUE & 1) != 0)
#error "odd STM32_PLL2R_VALUE value specified"
#endif
/**
* @brief PLL2 R output clock frequency.
* @brief STM32_PLL2R field.
*/
#if ((STM32_PLL2R_VALUE >= STM32_PLL2R_VALUE_MIN) && \
(STM32_PLL2R_VALUE <= STM32_PLL2R_VALUE_MAX)) || \
defined(__DOXYGEN__)
#define STM32_PLL2R ((STM32_PLL2R_VALUE - 1) << RCC_PLL2DIVR_PLL2R_Pos)
#else
#error "out of range STM32_PLL2R_VALUE value specified"
#endif
/**
* @brief PLL2R output clock frequency.
*/
#define STM32_PLL2_R_CLKOUT (STM32_PLL2VCO / STM32_PLL2R_VALUE)
/*
* PLL2-R output frequency range check.
* PLL2R output frequency range check.
*/
#if STM32_ACTIVATE_PLL2 && \
((STM32_PLL2_R_CLKOUT < STM32_PLL2R_MIN) || (STM32_PLL2_R_CLKOUT > STM32_PLL2R_MAX))
#error "STM32_PLL2_R_CLKOUT outside acceptable range (STM32_PLL2R_MIN...STM32_PLL2R_MAX)"
((STM32_PLL2_R_CLKOUT < STM32_PLLR_MIN) || \
(STM32_PLL2_R_CLKOUT > STM32_PLLR_MAX))
#error "STM32_PLL2_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)"
#endif
#else /* !STM32_RCC_PLL2_HAS_R */
#define STM32_PLL2R 0U
#define STM32_PLL2R 0
#endif /* !STM32_RCC_PLL2_HAS_R */
/*===========================================================================*/
@ -344,11 +426,12 @@ __STATIC_INLINE void pll2_init(void) {
#if STM32_RCC_HAS_PLL2
#if STM32_ACTIVATE_PLL2
/* PLL2 activation.*/
RCC->PLL2CFGR = STM32_PLL2PDIV | STM32_PLL2R |
STM32_PLL2REN | STM32_PLL2Q |
STM32_PLL2QEN | STM32_PLL2P |
STM32_PLL2PEN | STM32_PLL2N |
STM32_PLL2M | STM32_PLL2SRC;
RCC->PLL2CFGR = STM32_PLL2REN | STM32_PLL2QEN |
STM32_PLL2PEN | STM32_PLL2M |
STM32_PLL2RGE | STM32_PLL2VCOSEL |
STM32_PLL2SRC; /* TODO PLL2FRACEN */
RCC->PLL2DIVR = STM32_PLL2R | STM32_PLL2Q |
STM32_PLL2P | STM32_PLL2N;
RCC->CR |= RCC_CR_PLL2ON;
pll2_wait_lock();

303
os/hal/ports/STM32/LLD/RCCv1/stm32_pll3.inc
View File

@ -26,6 +26,17 @@
/* Driver local definitions. */
/*===========================================================================*/
/**
* @name PLL helpers
*/
#define STM32_PLL3VCOSEL_WIDE (0U << RCC_PLL3CFGR_PLL3VCOSEL_Pos)
#define STM32_PLL3VCOSEL_MEDIUM (1U << RCC_PLL3CFGR_PLL3VCOSEL_Pos)
#define STM32_PLL3RGE_0 (0U << RCC_PLL3CFGR_PLL3RGE_Pos)
#define STM32_PLL3RGE_1 (1U << RCC_PLL3CFGR_PLL3RGE_Pos)
#define STM32_PLL3RGE_2 (2U << RCC_PLL3CFGR_PLL3RGE_Pos)
#define STM32_PLL3RGE_3 (3U << RCC_PLL3CFGR_PLL3RGE_Pos)
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
@ -74,48 +85,109 @@
#error "STM32_PLL3R_VALUE not defined in mcuconf.h"
#endif
/* Check on valid values.*/
#if !defined(STM32_PLL3M_VALUE_MAX)
#error "STM32_PLL3M_VALUE_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL3M_VALUE_MIN)
#error "STM32_PLL3M_VALUE_MIN not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL3N_ODDVALID)
#error "STM32_PLL3N_ODDVALID not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL3N_VALUE_MAX)
#error "STM32_PLL3N_VALUE_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL3N_VALUE_MIN)
#error "STM32_PLL3N_VALUE_MIN not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL3P_ODDVALID)
#error "STM32_PLL3P_ODDVALID not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL3P_VALUE_MAX)
#error "STM32_PLL3P_VALUE_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL3P_VALUE_MIN)
#error "STM32_PLL3P_VALUE_MIN not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL3Q_ODDVALID)
#error "STM32_PLL3Q_ODDVALID not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL3Q_VALUE_MAX)
#error "STM32_PLL3Q_VALUE_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL3Q_VALUE_MIN)
#error "STM32_PLL3Q_VALUE_MIN not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL3R_ODDVALID)
#error "STM32_PLL3R_ODDVALID not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL3R_VALUE_MAX)
#error "STM32_PLL3R_VALUE_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL3R_VALUE_MIN)
#error "STM32_PLL3R_VALUE_MIN not defined in hal_lld.h"
#endif
/* Check on limits.*/
#if !defined(STM32_PLL3IN_MAX)
#error "STM32_PLL3IN_MAX not defined in hal_lld.h"
#if !defined(STM32_PLLIN_MAX)
#error "STM32_PLLIN_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL3IN_MIN)
#error "STM32_PLL3IN_MIN not defined in hal_lld.h"
#if !defined(STM32_PLLIN_MIN)
#error "STM32_PLLIN_MIN not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL3VCO_MAX)
#error "STM32_PLL3VCO_MAX not defined in hal_lld.h"
#if !defined(STM32_PLLVCO_MAX)
#error "STM32_PLLVCO_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL3VCO_MIN)
#error "STM32_PLL3VCO_MIN not defined in hal_lld.h"
#if !defined(STM32_PLLVCO_MIN)
#error "STM32_PLLVCO_MIN not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL3P_MAX)
#error "STM32_PLL3P_MAX not defined in hal_lld.h"
#if !defined(STM32_PLLP_MAX)
#error "STM32_PLLP_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL3P_MIN)
#error "STM32_PLL3P_MIN not defined in hal_lld.h"
#if !defined(STM32_PLLP_MIN)
#error "STM32_PLLP_MIN not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL3Q_MAX)
#error "STM32_PLL3Q_MAX not defined in hal_lld.h"
#if !defined(STM32_PLLQ_MAX)
#error "STM32_PLLQ_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL3Q_MIN)
#error "STM32_PLL3Q_MIN not defined in hal_lld.h"
#if !defined(STM32_PLLQ_MIN)
#error "STM32_PLLQ_MIN not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL3R_MAX)
#error "STM32_PLL3R_MAX not defined in hal_lld.h"
#if !defined(STM32_PLLR_MAX)
#error "STM32_PLLR_MAX not defined in hal_lld.h"
#endif
#if !defined(STM32_PLL3R_MIN)
#error "STM32_PLL3R_MIN not defined in hal_lld.h"
#if !defined(STM32_PLLR_MIN)
#error "STM32_PLLR_MIN not defined in hal_lld.h"
#endif
/* Input checks.*/
#if !defined(STM32_PLL3IN)
#error "STM32_PLL3IN not defined in hal_lld.h"
#endif
#if !defined(STM32_ACTIVATE_PLL3)
#error "STM32_ACTIVATE_PLL3 not defined in hal_lld.h"
#endif
@ -132,19 +204,15 @@
#error "STM32_PLL3REN not defined in hal_lld.h"
#endif
#if STM32_ACTIVATE_PLL3 && (STM32_PLL3CLKIN == 0)
#if STM32_ACTIVATE_PLL3 && (STM32_PLL3IN == 0)
#error "PLL3 activation required but no PLL3 clock selected"
#endif
#if (STM32_PLL3CLKIN != 0) && \
((STM32_PLL3CLKIN < STM32_PLL3IN_MIN) || (STM32_PLL3CLKIN > STM32_PLL3IN_MAX))
#error "STM32_PLL3CLKIN outside acceptable range (STM32_PLL3IN_MIN...STM32_PLL3IN_MAX)"
#endif
/**
* @brief STM32_PLL3M field.
*/
#if ((STM32_PLL3M_VALUE >= 1) && (STM32_PLL3M_VALUE <= 16)) || \
#if ((STM32_PLL3M_VALUE >= STM32_PLL3M_VALUE_MIN) && \
(STM32_PLL3M_VALUE <= STM32_PLL3M_VALUE_MAX)) || \
defined(__DOXYGEN__)
#define STM32_PLL3M ((STM32_PLL3M_VALUE - 1U) << RCC_PLL3CFGR_PLL3M_Pos)
@ -152,12 +220,49 @@
#error "invalid STM32_PLL3M_VALUE value specified"
#endif
/**
* @brief PLL comparator input frequency.
*/
#define STM32_PLL3CLKIN (STM32_PLL3IN / STM32_PLL3M_VALUE)
#if STM32_PLL3CLKIN < STM32_PLLIN_MIN
#error "STM32_PLL3CLKIN below acceptable range"
#elif STM32_PLL3CLKIN > STM32_PLLIN_MAX
#error "STM32_PLL3CLKIN above acceptable range"
#elif (STM32_PLL3CLKIN < STM32_PLLIN_THRESHOLD1) || defined(__DOXYGEN__)
#define STM32_PLL3RGE STM32_PLL3RGE_0
#define STM32_PLL3VCOSEL STM32_PLL3VCOSEL_MEDIUM
#define STM32_PLL3VCO_MIN STM32_PLLVCO_MEDIUM_MIN
#define STM32_PLL3VCO_MAX STM32_PLLVCO_MEDIUM_MAX
#elif STM32_PLL3CLKIN < STM32_PLLIN_THRESHOLD2
#define STM32_PLL3RGE STM32_PLL3RGE_1
#define STM32_PLL3VCOSEL STM32_PLL3VCOSEL_WIDE
#define STM32_PLL3VCO_MIN STM32_PLLVCO_WIDE_MIN
#define STM32_PLL3VCO_MAX STM32_PLLVCO_WIDE_MAX
#elif STM32_PLL3CLKIN < STM32_PLLIN_THRESHOLD3
#define STM32_PLL3RGE STM32_PLL3RGE_2
#define STM32_PLL3VCOSEL STM32_PLL3VCOSEL_WIDE
#define STM32_PLL3VCO_MIN STM32_PLLVCO_WIDE_MIN
#define STM32_PLL3VCO_MAX STM32_PLLVCO_WIDE_MAX
#else
#define STM32_PLL3RGE STM32_PLL3RGE_3
#define STM32_PLL3VCOSEL STM32_PLL3VCOSEL_WIDE
#define STM32_PLL3VCO_MIN STM32_PLLVCO_WIDE_MIN
#define STM32_PLL3VCO_MAX STM32_PLLVCO_WIDE_MAX
#endif
/**
* @brief STM32_PLL3N field.
*/
#if ((STM32_PLL3N_VALUE >= 8) && (STM32_PLL3N_VALUE <= 127)) || \
#if ((STM32_PLL3N_VALUE >= STM32_PLL3N_VALUE_MIN) && \
(STM32_PLL3N_VALUE <= STM32_PLL3N_VALUE_MAX)) || \
defined(__DOXYGEN__)
#define STM32_PLL3N (STM32_PLL3N_VALUE << RCC_PLL3CFGR_PLL3N_Pos)
#define STM32_PLL3N (STM32_PLL3N_VALUE << RCC_PLL3DIVR_PLL3N_Pos)
#else
#error "invalid STM32_PLL3N_VALUE value specified"
@ -180,137 +285,114 @@
/* P output, if present. */
/*---------------------------------------------------------------------------*/
#if STM32_RCC_PLL3_HAS_P || defined(__DOXYGEN__)
#if !STM32_PLL3P_ODDVALID && ((STM32_PLL3P_VALUE & 1) != 0)
#error "odd STM32_PLL3P_VALUE value specified"
#endif
/**
* @brief STM32_PLL3P field.
*/
#if (STM32_PLL3P_VALUE == 7) || defined(__DOXYGEN__)
#define STM32_PLL3P (0U << RCC_PLL3CFGR_PLL3P_Pos)
#elif STM32_PLL3P_VALUE == 17
#define STM32_PLL3P (1U << RCC_PLL3CFGR_PLL3P_Pos)
#else
#error "invalid STM32_PLL3P_VALUE value specified"
#endif
/* PDIV is not present on all devices.*/
#if defined(RCC_PLL3CFGR_PLL3PDIV_Pos) || defined(__DOXYGEN__)
/**
* @brief STM32_PLL3PDIV field.
*/
#if (STM32_PLL3PDIV_VALUE == 0) || \
((STM32_PLL3PDIV_VALUE >= 2) && (STM32_PLL3PDIV_VALUE <= 31)) || \
#if ((STM32_PLL3P_VALUE >= STM32_PLL3P_VALUE_MIN) && \
(STM32_PLL3P_VALUE <= STM32_PLL3P_VALUE_MAX)) || \
defined(__DOXYGEN__)
#define STM32_PLL3PDIV (STM32_PLL3PDIV_VALUE << RCC_PLL3CFGR_PLL3PDIV_Pos)
#define STM32_PLL3P ((STM32_PLL3P_VALUE - 1) << RCC_PLL3DIVR_PLL3P_Pos)
#else
#error "invalid STM32_PLL3PDIV_VALUE value specified"
#error "out of range STM32_PLL3P_VALUE value specified"
#endif
/**
* @brief PLL3 P output clock frequency.
* @brief PLL3P output clock frequency.
*/
#if (STM32_PLL3PDIV_VALUE == 0) || defined(__DOXYGEN__)
#define STM32_PLL3_P_CLKOUT (STM32_PLL3VCO / STM32_PLL3P_VALUE)
#else
#define STM32_PLL3_P_CLKOUT (STM32_PLL3VCO / STM32_PLL3PDIV_VALUE)
#endif
#else
#define STM32_PLL3_P_CLKOUT (STM32_PLL3VCO / STM32_PLL3P_VALUE)
#define STM32_PLL3PDIV 0U
#endif
/*
* PLL3-P output frequency range check.
* PLL3P output frequency range check.
*/
#if STM32_ACTIVATE_PLL3 && \
((STM32_PLL3_P_CLKOUT < STM32_PLL3P_MIN) || (STM32_PLL3_P_CLKOUT > STM32_PLL3P_MAX))
#error "STM32_PLL3_P_CLKOUT outside acceptable range (STM32_PLL3P_MIN...STM32_PLL3P_MAX)"
((STM32_PLL3_P_CLKOUT < STM32_PLLP_MIN) || \
(STM32_PLL3_P_CLKOUT > STM32_PLLP_MAX))
#error "STM32_PLL3_P_CLKOUT outside acceptable range (STM32_PLLP_MIN...STM32_PLLP_MAX)"
#endif
#else /* !STM32_RCC_PLL3_HAS_P */
#define STM32_PLL3P 0U
#define STM32_PLL3PDIV 0U
#define STM32_PLL3P 0
#endif /* !STM32_RCC_PLL3_HAS_P */
/*---------------------------------------------------------------------------*/
/* Q output, if present. */
/*---------------------------------------------------------------------------*/
#if STM32_RCC_PLL3_HAS_Q || defined(__DOXYGEN__)
/**
* @brief STM32_PLL3Q field.
*/
#if (STM32_PLL3Q_VALUE == 2) || defined(__DOXYGEN__)
#define STM32_PLL3Q (0U << RCC_PLL3CFGR_PLL3Q_Pos)
#elif STM32_PLL3Q_VALUE == 4
#define STM32_PLL3Q (1U << RCC_PLL3CFGR_PLL3Q_Pos)
#elif STM32_PLL3Q_VALUE == 6
#define STM32_PLL3Q (2U << RCC_PLL3CFGR_PLL3Q_Pos)
#elif STM32_PLL3Q_VALUE == 8
#define STM32_PLL3Q (3U << RCC_PLL3CFGR_PLL3Q_Pos)
#else
#error "invalid STM32_PLL3Q_VALUE value specified"
#if !STM32_PLL3Q_ODDVALID && ((STM32_PLL3Q_VALUE & 1) != 0)
#error "odd STM32_PLL3Q_VALUE value specified"
#endif
/**
* @brief PLL3 Q output clock frequency.
* @brief STM32_PLL3Q field.
*/
#if ((STM32_PLL3Q_VALUE >= STM32_PLL3Q_VALUE_MIN) && \
(STM32_PLL3Q_VALUE <= STM32_PLL3Q_VALUE_MAX)) || \
defined(__DOXYGEN__)
#define STM32_PLL3Q ((STM32_PLL3Q_VALUE - 1) << RCC_PLL3DIVR_PLL3Q_Pos)
#else
#error "out of range STM32_PLL3Q_VALUE value specified"
#endif
/**
* @brief PLL3Q output clock frequency.
*/
#define STM32_PLL3_Q_CLKOUT (STM32_PLL3VCO / STM32_PLL3Q_VALUE)
/*
* PLL3-Q output frequency range check.
* PLL3P output frequency range check.
*/
#if STM32_ACTIVATE_PLL3 && \
((STM32_PLL3_Q_CLKOUT < STM32_PLL3Q_MIN) || (STM32_PLL3_Q_CLKOUT > STM32_PLL3Q_MAX))
#error "STM32_PLL3_Q_CLKOUT outside acceptable range (STM32_PLL3Q_MIN...STM32_PLL3Q_MAX)"
((STM32_PLL3_Q_CLKOUT < STM32_PLLQ_MIN) || \
(STM32_PLL3_Q_CLKOUT > STM32_PLLQ_MAX))
#error "STM32_PLL3_Q_CLKOUT outside acceptable range (STM32_PLLQ_MIN...STM32_PLLQ_MAX)"
#endif
#else /* !STM32_RCC_PLL3_HAS_Q */
#define STM32_PLL3Q 0U
#define STM32_PLL3Q 0
#endif /* !STM32_RCC_PLL3_HAS_Q */
/*---------------------------------------------------------------------------*/
/* R output, if present. */
/*---------------------------------------------------------------------------*/
#if STM32_RCC_PLL3_HAS_R || defined(__DOXYGEN__)
/**
* @brief STM32_PLL3R field.
*/
#if (STM32_PLL3R_VALUE == 2) || defined(__DOXYGEN__)
#define STM32_PLL3R (0U << RCC_PLL3CFGR_PLL3R_Pos)
#elif STM32_PLL3R_VALUE == 4
#define STM32_PLL3R (1U << RCC_PLL3CFGR_PLL3R_Pos)
#elif STM32_PLL3R_VALUE == 6
#define STM32_PLL3R (2U << RCC_PLL3CFGR_PLL3R_Pos)
#elif STM32_PLL3R_VALUE == 8
#define STM32_PLL3R (3U << RCC_PLL3CFGR_PLL3R_Pos)
#else
#error "invalid STM32_PLL3R_VALUE value specified"
#if !STM32_PLL3R_ODDVALID && ((STM32_PLL3R_VALUE & 1) != 0)
#error "odd STM32_PLL3R_VALUE value specified"
#endif
/**
* @brief PLL3 R output clock frequency.
* @brief STM32_PLL3R field.
*/
#if ((STM32_PLL3R_VALUE >= STM32_PLL3R_VALUE_MIN) && \
(STM32_PLL3R_VALUE <= STM32_PLL3R_VALUE_MAX)) || \
defined(__DOXYGEN__)
#define STM32_PLL3R ((STM32_PLL3R_VALUE - 1) << RCC_PLL3DIVR_PLL3R_Pos)
#else
#error "out of range STM32_PLL3R_VALUE value specified"
#endif
/**
* @brief PLL3R output clock frequency.
*/
#define STM32_PLL3_R_CLKOUT (STM32_PLL3VCO / STM32_PLL3R_VALUE)
/*
* PLL3-R output frequency range check.
* PLL3R output frequency range check.
*/
#if STM32_ACTIVATE_PLL3 && \
((STM32_PLL3_R_CLKOUT < STM32_PLL3R_MIN) || (STM32_PLL3_R_CLKOUT > STM32_PLL3R_MAX))
#error "STM32_PLL3_R_CLKOUT outside acceptable range (STM32_PLL3R_MIN...STM32_PLL3R_MAX)"
((STM32_PLL3_R_CLKOUT < STM32_PLLR_MIN) || \
(STM32_PLL3_R_CLKOUT > STM32_PLLR_MAX))
#error "STM32_PLL3_R_CLKOUT outside acceptable range (STM32_PLLR_MIN...STM32_PLLR_MAX)"
#endif
#else /* !STM32_RCC_PLL3_HAS_R */
#define STM32_PLL3R 0U
#define STM32_PLL3R 0
#endif /* !STM32_RCC_PLL3_HAS_R */
/*===========================================================================*/
@ -344,11 +426,12 @@ __STATIC_INLINE void pll3_init(void) {
#if STM32_RCC_HAS_PLL3
#if STM32_ACTIVATE_PLL3
/* PLL3 activation.*/
RCC->PLL3CFGR = STM32_PLL3PDIV | STM32_PLL3R |
STM32_PLL3REN | STM32_PLL3Q |
STM32_PLL3QEN | STM32_PLL3P |
STM32_PLL3PEN | STM32_PLL3N |
STM32_PLL3M | STM32_PLL3SRC;
RCC->PLL3CFGR = STM32_PLL3REN | STM32_PLL3QEN |
STM32_PLL3PEN | STM32_PLL3M |
STM32_PLL3RGE | STM32_PLL3VCOSEL |
STM32_PLL3SRC; /* TODO PLL3FRACEN */
RCC->PLL3DIVR = STM32_PLL3R | STM32_PLL3Q |
STM32_PLL3P | STM32_PLL3N;
RCC->CR |= RCC_CR_PLL3ON;
pll3_wait_lock();

24
os/hal/ports/STM32/LLD/SYSTICKv1/hal_st_lld.c
View File

@ -65,6 +65,8 @@
#define ST_ENABLE_STOP() DBG->APBFZ2 |= DBG_APB_FZ2_DBG_TIM1_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM1
#elif defined(STM32H5XX)
#define ST_ENABLE_STOP() DBGMCU->APB2FZR |= DBGMCU_APB2FZR_DBG_TIM1_STOP
#else
#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM1_STOP
#endif
@ -92,6 +94,8 @@
#define ST_ENABLE_STOP() DBG->APBFZ1 |= DBG_APB_FZ1_DBG_TIM2_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM2
#elif defined(STM32H5XX)
#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM2_STOP
#else
#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM2_STOP
#endif
@ -119,6 +123,8 @@
#define ST_ENABLE_STOP() DBG->APBFZ1 |= DBG_APB_FZ1_DBG_TIM3_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM3
#elif defined(STM32H5XX)
#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM3_STOP
#else
#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM3_STOP
#endif
@ -144,6 +150,8 @@
#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM4_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM4
#elif defined(STM32H5XX)
#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM4_STOP
#else
#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM4_STOP
#endif
@ -169,6 +177,8 @@
#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM5_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM5
#elif defined(STM32H5XX)
#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM5_STOP
#else
#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM5_STOP
#endif
@ -196,6 +206,8 @@
#define ST_ENABLE_STOP() DBG->APBFZ1 |= DBG_APB_FZ1_DBG_TIM8_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM8
#elif defined(STM32H5XX)
#define ST_ENABLE_STOP() DBGMCU->APB2FZR |= DBGMCU_APB2FZR_DBG_TIM8_STOP
#else
#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM8_STOP
#endif
@ -296,6 +308,8 @@
#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM12_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM12
#elif defined(STM32H5XX)
#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM12_STOP
#else
#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM12_STOP
#endif
@ -321,6 +335,8 @@
#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM13_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM13
#elif defined(STM32H5XX)
#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM23_STOP
#else
#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM13_STOP
#endif
@ -348,6 +364,8 @@
#define ST_ENABLE_STOP() DBG->APBFZ2 |= DBG_APB_FZ2_DBG_TIM14_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM14
#elif defined(STM32H5XX)
#define ST_ENABLE_STOP() DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM14_STOP
#else
#define ST_ENABLE_STOP() DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM14_STOP
#endif
@ -373,6 +391,8 @@
#define ST_ENABLE_STOP() DBGMCU->APB2FZ |= DBGMCU_APB2FZ_DBG_TIM15_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB2FZ1 |= DBGMCU_APB2FZ1_DBG_TIM15
#elif defined(STM32H5XX)
#define ST_ENABLE_STOP() DBGMCU->APB2FZR |= DBGMCU_APB2FZR_DBG_TIM15_STOP
#else
#define ST_ENABLE_STOP() DBGMCU->APB2FZ |= DBGMCU_APB2_FZ_DBG_TIM15_STOP
#endif
@ -402,6 +422,8 @@
#define ST_ENABLE_STOP() DBGMCU->APB2FZR |= DBGMCU_APB2FZR_DBG_TIM16_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB2FZ1 |= DBGMCU_APB2FZ1_DBG_TIM16
#elif defined(STM32H5XX)
#define ST_ENABLE_STOP() DBGMCU->APB2FZR |= DBGMCU_APB2FZR_DBG_TIM16_STOP
#else
#define ST_ENABLE_STOP() DBGMCU->APB2FZ |= DBGMCU_APB2_FZ_DBG_TIM16_STOP
#endif
@ -431,6 +453,8 @@
#define ST_ENABLE_STOP() DBGMCU->APB2FZR |= DBGMCU_APB2FZR_DBG_TIM17_STOP
#elif defined(STM32H7XX)
#define ST_ENABLE_STOP() DBGMCU->APB2FZ1 |= DBGMCU_APB2FZ1_DBG_TIM17
#elif defined(STM32H5XX)
#define ST_ENABLE_STOP() DBGMCU->APB2FZR |= DBGMCU_APB2FZR_DBG_TIM17_STOP
#else
#define ST_ENABLE_STOP() DBGMCU->APB2FZ |= DBGMCU_APB2_FZ_DBG_TIM17_STOP
#endif

187
os/hal/ports/STM32/STM32H5xx/hal_lld.h
View File

@ -53,23 +53,23 @@
* @{
*/
#if defined(STM32H503xx) || defined(__DOXYGEN__)
#define PLATFORM_NAME "STM32H5 High-performance"
#define PLATFORM_NAME "STM32H5 High-performance"
#elif defined(STM32H562xx) || defined(STM32H563xx)
#define PLATFORM_NAME "STM32H5 High-performance"
#define PLATFORM_NAME "STM32H5 High-performance"
#elif defined(STM32H573xx)
#define PLATFORM_NAME "STM32H5 High-performance with security"
#define PLATFORM_NAME "STM32H5 High-performance with security"
#else
#error "STM32H5 device not specified"
#error "STM32H5 device not specified"
#endif
/**
* @brief Sub-family identifier.
*/
#if !defined(STM32H5XX) || defined(__DOXYGEN__)
#define STM32H5XX
#define STM32H5XX
#endif
/** @} */
@ -536,49 +536,53 @@
#define STM32_DACSEL_MASK (1U << 3)
#define STM32_DACSEL_FIELD(n) ((n) << 3)
#define STM32_DACSEL_LSI STM32_DACSEL_FIELD(0U)
#define STM32_DACSEL_LSE STM32_DACSEL_FIELD(1U)
#define STM32_DACSEL_IGNORE 0xFFFFFFFFU
#define STM32_DACSEL_LSE STM32_DACSEL_FIELD(0U)
#define STM32_DACSEL_LSI STM32_DACSEL_FIELD(1U)
#define STM32_RNGSEL_MASK (3U << 4)
#define STM32_RNGSEL_FIELD(n) ((n) << 4)
#define STM32_RNGSEL_HSI48 STM32_RNGSEL_FIELD(0U)
#define STM32_RNGSEL_PLL1Q STM32_RNGSEL_FIELD(1U)
#define STM32_RNGSEL_LSE STM32_RNGSEL_FIELD(2U)
#define STM32_RNGSEL_LSI STM32_RNGSEL_FIELD(3U)
#define STM32_RNGSEL_MASK (3U << 4)
#define STM32_RNGSEL_FIELD(n) ((n) << 4)
#define STM32_RNGSEL_IGNORE 0xFFFFFFFFU
#define STM32_RNGSEL_HSI48 STM32_RNGSEL_FIELD(0U)
#define STM32_RNGSEL_PLL1Q STM32_RNGSEL_FIELD(1U)
#define STM32_RNGSEL_LSE STM32_RNGSEL_FIELD(2U)
#define STM32_RNGSEL_LSI STM32_RNGSEL_FIELD(3U)
#define STM32_CECSEL_MASK (3U << 6)
#define STM32_CECSEL_FIELD(n) ((n) << 6)
#define STM32_CECSEL_LSE STM32_CECSEL_FIELD(0U)
#define STM32_CECSEL_LSI STM32_CECSEL_FIELD(1U)
#define STM32_CECSEL_CSIDIV128 STM32_CECSEL_FIELD(2U)
#define STM32_CECSEL_MASK (3U << 6)
#define STM32_CECSEL_FIELD(n) ((n) << 6)
#define STM32_CECSEL_IGNORE 0xFFFFFFFFU
#define STM32_CECSEL_LSE STM32_CECSEL_FIELD(0U)
#define STM32_CECSEL_LSI STM32_CECSEL_FIELD(1U)
#define STM32_CECSEL_CSIDIV128 STM32_CECSEL_FIELD(2U)
#define STM32_FDCANSEL_MASK (3U << 8)
#define STM32_FDCANSEL_MASK (3U << 8)
#define STM32_FDCANSEL_FIELD(n) ((n) << 8)
#define STM32_FDCANSEL_HSE STM32_FDCANSEL_FIELD(0U)
#define STM32_FDCANSEL_PLL1Q STM32_FDCANSEL_FIELD(1U)
#define STM32_FDCANSEL_PLL2Q STM32_FDCANSEL_FIELD(2U)
#define STM32_FDCANSEL_IGNORE 0xFFFFFFFFU
#define STM32_FDCANSEL_HSE STM32_FDCANSEL_FIELD(0U)
#define STM32_FDCANSEL_PLL1Q STM32_FDCANSEL_FIELD(1U)
#define STM32_FDCANSEL_PLL2Q STM32_FDCANSEL_FIELD(2U)
#define STM32_SAI1SEL_MASK (7U << 16)
#define STM32_SAI1SEL_FIELD(n) ((n) << 16)
#define STM32_SAI1SEL_PLL1Q STM32_SAI1SEL_FIELD(0U)
#define STM32_SAI1SEL_PLL2P STM32_SAI1SEL_FIELD(1U)
#define STM32_SAI1SEL_PLL3P STM32_SAI1SEL_FIELD(2U)
#define STM32_SAI1SEL_AUDIOCLK STM32_SAI1SEL_FIELD(3U)
#define STM32_SAI1SEL_PER STM32_SAI1SEL_FIELD(4U)
#define STM32_SAI1SEL_MASK (7U << 16)
#define STM32_SAI1SEL_FIELD(n) ((n) << 16)
#define STM32_SAI1SEL_PLL1Q STM32_SAI1SEL_FIELD(0U)
#define STM32_SAI1SEL_PLL2P STM32_SAI1SEL_FIELD(1U)
#define STM32_SAI1SEL_PLL3P STM32_SAI1SEL_FIELD(2U)
#define STM32_SAI1SEL_AUDIOCLK STM32_SAI1SEL_FIELD(3U)
#define STM32_SAI1SEL_PER STM32_SAI1SEL_FIELD(4U)
#define STM32_SAI2SEL_MASK (7U << 19)
#define STM32_SAI2SEL_FIELD(n) ((n) << 19)
#define STM32_SAI2SEL_PLL1Q STM32_SAI2SEL_FIELD(0U)
#define STM32_SAI2SEL_PLL2P STM32_SAI2SEL_FIELD(1U)
#define STM32_SAI2SEL_PLL3P STM32_SAI2SEL_FIELD(2U)
#define STM32_SAI2SEL_AUDIOCLK STM32_SAI2SEL_FIELD(3U)
#define STM32_SAI2SEL_PER STM32_SAI2SEL_FIELD(4U)
#define STM32_SAI2SEL_MASK (7U << 19)
#define STM32_SAI2SEL_FIELD(n) ((n) << 19)
#define STM32_SAI2SEL_PLL1Q STM32_SAI2SEL_FIELD(0U)
#define STM32_SAI2SEL_PLL2P STM32_SAI2SEL_FIELD(1U)
#define STM32_SAI2SEL_PLL3P STM32_SAI2SEL_FIELD(2U)
#define STM32_SAI2SEL_AUDIOCLK STM32_SAI2SEL_FIELD(3U)
#define STM32_SAI2SEL_PER STM32_SAI2SEL_FIELD(4U)
#define STM32_CKPERSEL_MASK (3U << 30)
#define STM32_CKPERSEL_FIELD(n) ((n) << 30)
#define STM32_CKPERSEL_HSI STM32_CKPERSEL_FIELD(0U)
#define STM32_CKPERSEL_CSI STM32_CKPERSEL_FIELD(1U)
#define STM32_CKPERSEL_HSE STM32_CKPERSEL_FIELD(2U)
#define STM32_CKPERSEL_MASK (3U << 30)
#define STM32_CKPERSEL_FIELD(n) ((n) << 30)
#define STM32_CKPERSEL_HSI STM32_CKPERSEL_FIELD(0U)
#define STM32_CKPERSEL_CSI STM32_CKPERSEL_FIELD(1U)
#define STM32_CKPERSEL_HSE STM32_CKPERSEL_FIELD(2U)
/** @} */
/**
@ -625,7 +629,7 @@
* @brief PWR VOSCR register initialization value.
*/
#if !defined(STM32_PWR_VOSCR) || defined(__DOXYGEN__)
#define STM32_PWR_VOSCR STM32_VOS_RANGE3
#define STM32_PWR_VOSCR STM32_VOS_RANGE0
#endif
/**
@ -761,7 +765,7 @@
* @brief PLL1M divider value.
* @note The allowed values are 1..63.
*/
#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
#if !defined(STM32_PLL1M_VALUE) || defined(__DOXYGEN__)
#define STM32_PLL1M_VALUE 4
#endif
@ -808,7 +812,7 @@
* @brief PLL2M divider value.
* @note The allowed values are 1..63.
*/
#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
#if !defined(STM32_PLL2M_VALUE) || defined(__DOXYGEN__)
#define STM32_PLL2M_VALUE 4
#endif
@ -855,7 +859,7 @@
* @brief PLL3M divider value.
* @note The allowed values are 1..63.
*/
#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__)
#if !defined(STM32_PLL3M_VALUE) || defined(__DOXYGEN__)
#define STM32_PLL3M_VALUE 4
#endif
@ -965,7 +969,7 @@
* @brief MCO2 clock source.
*/
#if !defined(STM32_MCO2SEL) || defined(__DOXYGEN__)
#define STM32_MCO2SEL STM32_MCO2SEL_CSI
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#endif
/**
@ -985,7 +989,7 @@
/**
* @brief TIMICSEL clock source.
*/
#if !defined(STM32_LSCOSEL) || defined(__DOXYGEN__)
#if !defined(STM32_TIMICSEL) || defined(__DOXYGEN__)
#define STM32_TIMICSEL STM32_TIMICSEL_NOCLK
#endif
@ -1077,7 +1081,7 @@
* @brief LPUART1 clock source.
*/
#if !defined(STM32_LPUART1SEL) || defined(__DOXYGEN__)
#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK3
#endif
/**
@ -1091,7 +1095,7 @@
* @brief LPTIM2 clock source.
*/
#if !defined(STM32_LPTIM2SEL) || defined(__DOXYGEN__)
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK3
#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
#endif
/**
@ -1245,7 +1249,7 @@
* @brief DACSEL clock source.
*/
#if !defined(STM32_DACSEL) || defined(__DOXYGEN__)
#define STM32_DACSEL STM32_DACSEL_LSI
#define STM32_DACSEL STM32_DACSEL_LSE
#endif
/**
@ -1524,13 +1528,13 @@
#if STM32_CSI_ENABLED
#else /* !STM32_CSI_ENABLED */
#if STM32_ACTIVATE_PLL1 && (STM32_PLL1SRC == STM32_PLL1SRC_CSI))
#if STM32_ACTIVATE_PLL1 && (STM32_PLL1SRC == STM32_PLL1SRC_CSI)
#error "CSI not enabled, required by STM32_PLL1SRC"
#endif
#if STM32_ACTIVATE_PLL2 && (STM32_PLL1SRC == STM32_PLL2SRC_CSI))
#if STM32_ACTIVATE_PLL2 && (STM32_PLL1SRC == STM32_PLL2SRC_CSI)
#error "CSI not enabled, required by STM32_PLL2SRC"
#endif
#if STM32_ACTIVATE_PLL3 && (STM32_PLL1SRC == STM32_PLL3SRC_CSI))
#if STM32_ACTIVATE_PLL3 && (STM32_PLL1SRC == STM32_PLL3SRC_CSI)
#error "CSI not enabled, required by STM32_PLL3SRC"
#endif
@ -1613,7 +1617,7 @@
#error "CSI not enabled, required by STM32_CECSEL"
#endif
#if STM32_PERSEL == STM32_PERSEL_CSI
#if STM32_CKPERSEL == STM32_CKPERSEL_CSI
#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PER)
#error "CSI not enabled, required by STM32_LPTIM1SEL"
#endif
@ -1912,13 +1916,13 @@
#if STM32_HSE_ENABLED
#else /* !STM32_HSE_ENABLED */
#if STM32_ACTIVATE_PLL1 && (STM32_PLL1SRC == STM32_PLL1SRC_HSE))
#if STM32_ACTIVATE_PLL1 && (STM32_PLL1SRC == STM32_PLL1SRC_HSE)
#error "HSE not enabled, required by STM32_PLL1SRC"
#endif
#if STM32_ACTIVATE_PLL2 && (STM32_PLL1SRC == STM32_PLL2SRC_HSE))
#if STM32_ACTIVATE_PLL2 && (STM32_PLL1SRC == STM32_PLL2SRC_HSE)
#error "HSE not enabled, required by STM32_PLL2SRC"
#endif
#if STM32_ACTIVATE_PLL3 && (STM32_PLL1SRC == STM32_PLL3SRC_HSE))
#if STM32_ACTIVATE_PLL3 && (STM32_PLL1SRC == STM32_PLL3SRC_HSE)
#error "HSE not enabled, required by STM32_PLL3SRC"
#endif
@ -2100,7 +2104,7 @@
/**
* @brief STM32_PLL2PEN field.
*/
#if (STM32_SW == STM32_SW_PLL2P) || \
#if (STM32_SW == STM32_SW_PLL1P) || \
(STM32_MCO2SEL == STM32_MCO2SEL_PLL1P) || \
(STM32_LPTIM1SEL == STM32_LPTIM1SEL_PLL2P) || \
(STM32_LPTIM2SEL == STM32_LPTIM2SEL_PLL2P) || \
@ -2206,12 +2210,12 @@
/**
* @brief STM32_PLL3REN field.
*/
#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PLL3P) || \
(STM32_LPTIM2SEL == STM32_LPTIM2SEL_PLL3P) || \
(STM32_LPTIM3SEL == STM32_LPTIM3SEL_PLL3P) || \
(STM32_LPTIM4SEL == STM32_LPTIM4SEL_PLL3P) || \
(STM32_LPTIM5SEL == STM32_LPTIM5SEL_PLL3P) || \
(STM32_LPTIM6SEL == STM32_LPTIM6SEL_PLL3P) || \
#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PLL3R) || \
(STM32_LPTIM2SEL == STM32_LPTIM2SEL_PLL3R) || \
(STM32_LPTIM3SEL == STM32_LPTIM3SEL_PLL3R) || \
(STM32_LPTIM4SEL == STM32_LPTIM4SEL_PLL3R) || \
(STM32_LPTIM5SEL == STM32_LPTIM5SEL_PLL3R) || \
(STM32_LPTIM6SEL == STM32_LPTIM6SEL_PLL3R) || \
(STM32_I2C1SEL == STM32_I2C1SEL_PLL3R) || \
(STM32_I2C2SEL == STM32_I2C2SEL_PLL3R) || \
(STM32_I2C3SEL == STM32_I2C3SEL_PLL3R) || \
@ -2232,17 +2236,17 @@
/**
* @brief System clock source.
*/
#if STM32_NO_INIT || defined(__DOXYGEN__)
#if (STM32_SW == STM32_SW_HSI) || defined(__DOXYGEN__)
#define STM32_SYSCLK STM32_HSICLK
#elif (STM32_SW == STM32_SW_HSI)
#define STM32_SYSCLK STM32_HSICLK
#elif STM32_SW == STM32_SW_CSI
#define STM32_SYSCLK STM32_CSICLK
#elif (STM32_SW == STM32_SW_HSE)
#elif STM32_SW == STM32_SW_HSE
#define STM32_SYSCLK STM32_HSECLK
#elif (STM32_SW == STM32_SW_PLLRCLK)
#define STM32_SYSCLK STM32_PLL_R_CLKOUT
#elif STM32_SW == STM32_SW_PLL1P
#define STM32_SYSCLK STM32_PLL1_P_CLKOUT
#else
#error "invalid STM32_SW value specified"
@ -2289,15 +2293,6 @@
#error "invalid STM32_RTCPRECLK_VALUE value specified"
#endif
#elif (STM32_MCO1PRE_VALUE > STM32_MCO1PRE_NOCLOCK) && \
(STM32_MCO1PRE_VALUE < 16)
#define STM32_MCO1PRE STM32_MCO1PRE_FIELD(STM32_MCO1PRE_VALUE)
#define STM32_MCO1CLK (STM32_MCO1DIVCLK / STM32_MCO1PRE_VALUE)
#else
#error "invalid STM32_MCO1PRE_VALUE value specified"
#endif
/**
* @brief MCO1 source clock.
*/
@ -2327,10 +2322,11 @@
* @brief MCO1 output pin clock frequency.
*/
#if (STM32_MCO1PRE_VALUE == STM32_MCO1PRE_NOCLOCK) || defined(__DOXYGEN__)
#define STM32_MCO1CLK 0
#define STM32_MCO1PRE 0U
#define STM32_MCO1CLK 0U
#elif (STM32_MCO1PRE_VALUE > STM32_MCO1PRE_NOCLOCK) && \
(STM32_MCO1PRE_VALUE < 16)
(STM32_MCO1PRE_VALUE <= 15)
#define STM32_MCO1PRE STM32_MCO1PRE_FIELD(STM32_MCO1PRE_VALUE)
#define STM32_MCO1CLK (STM32_MCO1DIVCLK / STM32_MCO1PRE_VALUE)
@ -2367,10 +2363,11 @@
* @brief MCO2 output pin clock frequency.
*/
#if (STM32_MCO2PRE_VALUE == STM32_MCO2PRE_NOCLOCK) || defined(__DOXYGEN__)
#define STM32_MCO2CLK 0
#define STM32_MCO2PRE 0U
#define STM32_MCO2CLK 0U
#elif (STM32_MCO2PRE_VALUE > STM32_MCO2PRE_NOCLOCK) && \
(STM32_MCO2PRE_VALUE < 16)
(STM32_MCO2PRE_VALUE <= 15)
#define STM32_MCO2PRE STM32_MCO2PRE_FIELD(STM32_MCO2PRE_VALUE)
#define STM32_MCO2CLK (STM32_MCO2DIVCLK / STM32_MCO2PRE_VALUE)
@ -3261,6 +3258,9 @@
#elif STM32_DACSEL == STM32_DACSEL_LSE
#define STM32_DACSELCLK STM32_LSECLK
#elif STM32_DACSEL == STM32_DACSEL_IGNORE
#define STM32_DACSELCLK 0
#else
#error "invalid source selected for DACSEL clock"
#endif
@ -3280,6 +3280,9 @@
#elif STM32_RNGSEL == STM32_RNGSEL_LSI
#define STM32_RNGCLK STM32_LSICLK
#elif STM32_RNGSEL == STM32_RNGSEL_IGNORE
#define STM32_RNGCLK 0
#else
#error "invalid source selected for RNG clock"
#endif
@ -3296,6 +3299,9 @@
#elif STM32_CECSEL == STM32_CECSEL_CSIDIV128
#define STM32_CECCLK (STM32_CSICLK / 128)
#elif STM32_CECSEL == STM32_CECSEL_IGNORE
#define STM32_CECCLK 0
#else
#error "invalid source selected for CEC clock"
#endif
@ -3312,6 +3318,9 @@
#elif STM32_FDCANSEL == STM32_FDCANSEL_PLL2Q
#define STM32_FDCANCLK hal_lld_get_clock_point(CLK_PLL2Q)
#elif STM32_FDCANSEL == STM32_FDCANSEL_IGNORE
#define STM32_FDCANCLK 0
#else
#error "invalid source selected for FDCAN clock"
#endif
@ -3319,10 +3328,7 @@
/**
* @brief SAI1 clock frequency.
*/
#if (STM32_SAI1SEL == STM32_SAI1SEL_SYSCLK) || defined(__DOXYGEN__)
#define STM32_SAI1CLK hal_lld_get_clock_point(CLK_SYSCLK)
#elif STM32_SAI1SEL == STM32_SAI1SEL_PLL1Q
#if (STM32_SAI1SEL == STM32_SAI1SEL_PLL1Q) || defined(__DOXYGEN__)
#define STM32_SAI1CLK hal_lld_get_clock_point(CLK_PLL1Q)
#elif STM32_SAI1SEL == STM32_SAI2SEL_PLL2P
@ -3344,10 +3350,7 @@
/**
* @brief SAI2 clock frequency.
*/
#if (STM32_SAI2SEL == STM32_SAI2SEL_SYSCLK) || defined(__DOXYGEN__)
#define STM32_SAI2CLK hal_lld_get_clock_point(CLK_SYSCLK)
#elif STM32_SAI2SEL == STM32_SAI2SEL_PLL1Q
#if (STM32_SAI2SEL == STM32_SAI2SEL_PLL1Q) || defined(__DOXYGEN__)
#define STM32_SAI2CLK hal_lld_get_clock_point(CLK_PLL1Q)
#elif STM32_SAI2SEL == STM32_SAI2SEL_PLL2P
@ -3528,7 +3531,7 @@ typedef struct {
#include "stm32_isr.h"
//#include "stm32_dma.h"
#include "stm32_exti.h"
#include "stm32_rcc.h"
//#include "stm32_rcc.h"
#include "stm32_tim.h"
#if defined(HAL_LLD_USE_CLOCK_MANAGEMENT) && !defined(__DOXYGEN__)

1
os/hal/ports/STM32/STM32H5xx/platform.mk
View File

@ -25,6 +25,7 @@ else
endif
# Drivers compatible with the platform.
include $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/RCCv1/driver.mk
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SYSTICKv1/driver.mk

49
os/hal/ports/STM32/STM32H5xx/stm32_limits.h
View File

@ -38,10 +38,6 @@
#define STM32_VOS0_LSECLK_BYP_MAX 1000000
#define STM32_VOS0_LSECLK_MIN 32768
#define STM32_VOS0_LSECLK_BYP_MIN 32768
#define STM32_VOS0_PLLIN_MAX 16000000
#define STM32_VOS0_PLLIN_MIN 2000000
#define STM32_VOS0_PLLVCO_MAX 560000000
#define STM32_VOS0_PLLVCO_MIN 128000000
#define STM32_VOS0_PLLP_MAX 250000000
#define STM32_VOS0_PLLP_MIN 1000000
#define STM32_VOS0_PLLQ_MAX 250000000
@ -50,7 +46,7 @@
#define STM32_VOS0_PLLR_MIN 1000000
#define STM32_VOS0_PCLK1_MAX 250000000
#define STM32_VOS0_PCLK2_MAX 250000000
#define STM32_VOS0_PCLK2_MAX 250000000
#define STM32_VOS0_PCLK3_MAX 250000000
#define STM32_VOS0_ADCCLK_MAX 125000000
#define STM32_VOS0_0WS_THRESHOLD 42000000
@ -73,10 +69,6 @@
#define STM32_VOS1_LSECLK_BYP_MAX 1000000
#define STM32_VOS1_LSECLK_MIN 32768
#define STM32_VOS1_LSECLK_BYP_MIN 32768
#define STM32_VOS1_PLLIN_MAX 16000000
#define STM32_VOS1_PLLIN_MIN 2000000
#define STM32_VOS1_PLLVCO_MAX 560000000
#define STM32_VOS1_PLLVCO_MIN 128000000
#define STM32_VOS1_PLLP_MAX 200000000
#define STM32_VOS1_PLLP_MIN 1000000
#define STM32_VOS1_PLLQ_MAX 200000000
@ -108,10 +100,6 @@
#define STM32_VOS2_LSECLK_BYP_MAX 1000000
#define STM32_VOS2_LSECLK_MIN 32768
#define STM32_VOS2_LSECLK_BYP_MIN 32768
#define STM32_VOS2_PLLIN_MAX 16000000
#define STM32_VOS2_PLLIN_MIN 2000000
#define STM32_VOS2_PLLVCO_MAX 560000000
#define STM32_VOS2_PLLVCO_MIN 128000000
#define STM32_VOS2_PLLP_MAX 150000000
#define STM32_VOS2_PLLP_MIN 1000000
#define STM32_VOS2_PLLQ_MAX 150000000
@ -143,10 +131,6 @@
#define STM32_VOS3_LSECLK_BYP_MAX 1000000
#define STM32_VOS3_LSECLK_MIN 32768
#define STM32_VOS3_LSECLK_BYP_MIN 32768
#define STM32_VOS3_PLLIN_MAX 16000000
#define STM32_VOS3_PLLIN_MIN 2000000
#define STM32_VOS3_PLLVCO_MAX 560000000
#define STM32_VOS3_PLLVCO_MIN 128000000
#define STM32_VOS3_PLLP_MAX 100000000
#define STM32_VOS3_PLLP_MIN 1000000
#define STM32_VOS3_PLLQ_MAX 100000000
@ -179,10 +163,6 @@
#define STM32_LSECLK_BYP_MAX STM32_VOS0_LSECLK_BYP_MAX
#define STM32_LSECLK_MIN STM32_VOS0_LSECLK_MIN
#define STM32_LSECLK_BYP_MIN STM32_VOS0_LSECLK_BYP_MIN
#define STM32_PLLIN_MAX STM32_VOS0_PLLIN_MAX
#define STM32_PLLIN_MIN STM32_VOS0_PLLIN_MIN
#define STM32_PLLVCO_MAX STM32_VOS0_PLLVCO_MAX
#define STM32_PLLVCO_MIN STM32_VOS0_PLLVCO_MIN
#define STM32_PLLP_MAX STM32_VOS0_PLLP_MAX
#define STM32_PLLP_MIN STM32_VOS0_PLLP_MIN
#define STM32_PLLP_MIN STM32_VOS0_PLLP_MIN
@ -216,10 +196,6 @@
#define STM32_LSECLK_BYP_MAX STM32_VOS1_LSECLK_BYP_MAX
#define STM32_LSECLK_MIN STM32_VOS1_LSECLK_MIN
#define STM32_LSECLK_BYP_MIN STM32_VOS1_LSECLK_BYP_MIN
#define STM32_PLLIN_MAX STM32_VOS1_PLLIN_MAX
#define STM32_PLLIN_MIN STM32_VOS1_PLLIN_MIN
#define STM32_PLLVCO_MAX STM32_VOS1_PLLVCO_MAX
#define STM32_PLLVCO_MIN STM32_VOS1_PLLVCO_MIN
#define STM32_PLLP_MAX STM32_VOS1_PLLP_MAX
#define STM32_PLLP_MIN STM32_VOS1_PLLP_MIN
#define STM32_PLLQ_MAX STM32_VOS1_PLLQ_MAX
@ -251,10 +227,6 @@
#define STM32_LSECLK_BYP_MAX STM32_VOS2_LSECLK_BYP_MAX
#define STM32_LSECLK_MIN STM32_VOS2_LSECLK_MIN
#define STM32_LSECLK_BYP_MIN STM32_VOS2_LSECLK_BYP_MIN
#define STM32_PLLIN_MAX STM32_VOS2_PLLIN_MAX
#define STM32_PLLIN_MIN STM32_VOS2_PLLIN_MIN
#define STM32_PLLVCO_MAX STM32_VOS2_PLLVCO_MAX
#define STM32_PLLVCO_MIN STM32_VOS2_PLLVCO_MIN
#define STM32_PLLP_MAX STM32_VOS2_PLLP_MAX
#define STM32_PLLP_MIN STM32_VOS2_PLLP_MIN
#define STM32_PLLQ_MAX STM32_VOS2_PLLQ_MAX
@ -286,10 +258,6 @@
#define STM32_LSECLK_BYP_MAX STM32_VOS3_LSECLK_BYP_MAX
#define STM32_LSECLK_MIN STM32_VOS3_LSECLK_MIN
#define STM32_LSECLK_BYP_MIN STM32_VOS3_LSECLK_BYP_MIN
#define STM32_PLLIN_MAX STM32_VOS3_PLLIN_MAX
#define STM32_PLLIN_MIN STM32_VOS3_PLLIN_MIN
#define STM32_PLLVCO_MAX STM32_VOS3_PLLVCO_MAX
#define STM32_PLLVCO_MIN STM32_VOS3_PLLVCO_MIN
#define STM32_PLLP_MAX STM32_VOS3_PLLP_MAX
#define STM32_PLLP_MIN STM32_VOS3_PLLP_MIN
#define STM32_PLLQ_MAX STM32_VOS3_PLLQ_MAX
@ -316,13 +284,26 @@
#endif
/**
* @name PLL input thresholds
* @name PLL input ranges
*/
#define STM32_PLLIN_MIN 2000000
#define STM32_PLLIN_MAX 16000000
#define STM32_PLLIN_THRESHOLD1 2000000
#define STM32_PLLIN_THRESHOLD2 4000000
#define STM32_PLLIN_THRESHOLD3 8000000
/** @} */
/**
* @name PLL output ranges
*/
#define STM32_PLLVCO_MIN 128000000
#define STM32_PLLVCO_MAX 560000000
#define STM32_PLLVCO_WIDE_MIN 128000000
#define STM32_PLLVCO_WIDE_MAX 560000000
#define STM32_PLLVCO_MEDIUM_MIN 150000000
#define STM32_PLLVCO_MEDIUM_MAX 420000000
/** @} */
/**
* @name PLL dividers ranges
* @{