SPIv3 tentative enhancements, not complete and broken. Some documentation fixes.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14967 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio
parent
4bd8290a35
commit
184683e70c
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@ -165,7 +165,7 @@ struct hal_spi_config {
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#endif
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#if (SPI_SUPPORTS_SLAVE_MODE == TRUE) || defined(__DOXYGEN__)
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/**
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* @brief Enables the circular buffer mode.
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* @brief Enables the slave mode.
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*/
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bool slave;
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#endif
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@ -15,8 +15,8 @@
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*/
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/**
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* @file SPIv2/hal_spi_lld.c
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* @brief STM32 SPI subsystem low level driver source.
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* @file SPIv2/hal_spi_v2_lld.c
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* @brief STM32 SPI (v2) subsystem low level driver source.
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*
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* @addtogroup SPI
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* @{
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@ -15,8 +15,8 @@
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*/
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/**
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* @file SPIv2/hal_spi_lld.h
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* @brief STM32 SPI subsystem low level driver header.
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* @file SPIv2/hal_spi_v2_lld.h
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* @brief STM32 SPI (v2) subsystem low level driver header.
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*
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* @addtogroup SPI
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* @{
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@ -0,0 +1,9 @@
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ifeq ($(USE_SMART_BUILD),yes)
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ifneq ($(findstring HAL_USE_SPI TRUE,$(HALCONF)),)
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PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv3/hal_spi_v2_lld.c
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endif
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else
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PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv3/hal_spi_v2_lld.c
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endif
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PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv3
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,605 @@
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file SPIv3/hal_spi_v2_lld.h
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* @brief STM32 SPI (v2) subsystem low level driver header.
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*
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* @addtogroup SPI
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* @{
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*/
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#ifndef HAL_SPI_LLD_H
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#define HAL_SPI_LLD_H
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#if HAL_USE_SPI || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Circular mode support flag.
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*/
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#define SPI_SUPPORTS_CIRCULAR TRUE
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/**
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* @brief Slave mode support flag.
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*/
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#define SPI_SUPPORTS_SLAVE_MODE FALSE
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/**
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* @name Register helpers not found in ST headers
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* @{
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*/
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#define SPI_CFG1_MBR_VALUE(n) ((n) << SPI_CFG1_MBR_Pos)
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#define SPI_CFG1_MBR_DIV2 SPI_CFG1_MBR_VALUE(0)
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#define SPI_CFG1_MBR_DIV4 SPI_CFG1_MBR_VALUE(1)
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#define SPI_CFG1_MBR_DIV8 SPI_CFG1_MBR_VALUE(2)
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#define SPI_CFG1_MBR_DIV16 SPI_CFG1_MBR_VALUE(3)
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#define SPI_CFG1_MBR_DIV32 SPI_CFG1_MBR_VALUE(4)
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#define SPI_CFG1_MBR_DIV64 SPI_CFG1_MBR_VALUE(5)
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#define SPI_CFG1_MBR_DIV128 SPI_CFG1_MBR_VALUE(6)
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#define SPI_CFG1_MBR_DIV256 SPI_CFG1_MBR_VALUE(7)
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#define SPI_CFG1_CRCSIZE_VALUE(n) ((n) << SPI_CFG1_CRCSIZE_Pos)
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#define SPI_CFG1_UDRDET_VALUE(n) ((n) << SPI_CFG1_UDRDET_Pos)
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#define SPI_CFG1_UDRCFG_VALUE(n) ((n) << SPI_CFG1_UDRCFG_Pos)
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#define SPI_CFG1_FTHLV_VALUE(n) ((n) << SPI_CFG1_FTHLV_Pos)
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#define SPI_CFG1_DSIZE_VALUE(n) ((n) << SPI_CFG1_DSIZE_Pos)
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#define SPI_CFG2_SP_VALUE(n) ((n) << SPI_CFG2_SP_Pos)
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#define SPI_CFG2_COMM_VALUE(n) ((n) << SPI_CFG2_COMM_Pos)
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#define SPI_CFG2_COMM_FULL_DUPLEX SPI_CFG2_COMM_VALUE(0)
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#define SPI_CFG2_COMM_TRANSMITTER SPI_CFG2_COMM_VALUE(1)
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#define SPI_CFG2_COMM_RECEIVER SPI_CFG2_COMM_VALUE(2)
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#define SPI_CFG2_COMM_HALF_DUPLEX SPI_CFG2_COMM_VALUE(3)
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#define SPI_CFG2_MIDI_VALUE(n) ((n) << SPI_CFG2_MIDI_Pos)
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#define SPI_CFG2_MSSI_VALUE(n) ((n) << SPI_CFG2_MSSI_Pos)
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief SPI1 driver enable switch.
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* @details If set to @p TRUE the support for SPI1 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_SPI_USE_SPI1) || defined(__DOXYGEN__)
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#define STM32_SPI_USE_SPI1 FALSE
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#endif
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/**
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* @brief SPI2 driver enable switch.
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* @details If set to @p TRUE the support for SPI2 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_SPI_USE_SPI2) || defined(__DOXYGEN__)
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#define STM32_SPI_USE_SPI2 FALSE
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#endif
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/**
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* @brief SPI3 driver enable switch.
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* @details If set to @p TRUE the support for SPI3 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_SPI_USE_SPI3) || defined(__DOXYGEN__)
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#define STM32_SPI_USE_SPI3 FALSE
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#endif
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/**
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* @brief SPI4 driver enable switch.
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* @details If set to @p TRUE the support for SPI4 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_SPI_USE_SPI4) || defined(__DOXYGEN__)
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#define STM32_SPI_USE_SPI4 FALSE
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#endif
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/**
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* @brief SPI5 driver enable switch.
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* @details If set to @p TRUE the support for SPI5 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_SPI_USE_SPI5) || defined(__DOXYGEN__)
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#define STM32_SPI_USE_SPI5 FALSE
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#endif
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/**
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* @brief SPI6 driver enable switch.
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* @details If set to @p TRUE the support for SPI6 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_SPI_USE_SPI6) || defined(__DOXYGEN__)
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#define STM32_SPI_USE_SPI6 FALSE
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#endif
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/**
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* @brief Filler pattern used when there is nothing to transmit.
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*/
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#if !defined(STM32_SPI_FILLER_PATTERN) || defined(__DOXYGEN__)
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#define STM32_SPI_FILLER_PATTERN 0xFFFFFFFFU
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#endif
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/**
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* @brief SPI1 interrupt priority level setting.
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*/
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#if !defined(STM32_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI1_IRQ_PRIORITY 10
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#endif
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/**
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* @brief SPI2 interrupt priority level setting.
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*/
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#if !defined(STM32_SPI_SPI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI2_IRQ_PRIORITY 10
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#endif
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/**
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* @brief SPI3 interrupt priority level setting.
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*/
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#if !defined(STM32_SPI_SPI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI3_IRQ_PRIORITY 10
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#endif
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/**
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* @brief SPI4 interrupt priority level setting.
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*/
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#if !defined(STM32_SPI_SPI4_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI4_IRQ_PRIORITY 10
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#endif
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/**
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* @brief SPI5 interrupt priority level setting.
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*/
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#if !defined(STM32_SPI_SPI5_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI5_IRQ_PRIORITY 10
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#endif
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/**
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* @brief SPI6 interrupt priority level setting.
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*/
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#if !defined(STM32_SPI_SPI6_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI6_IRQ_PRIORITY 10
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#endif
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/**
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* @brief SPI1 DMA priority (0..3|lowest..highest).
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* @note The priority level is used for both the TX and RX DMA streams but
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* because of the streams ordering the RX stream has always priority
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* over the TX stream.
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*/
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#if !defined(STM32_SPI_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI1_DMA_PRIORITY 1
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#endif
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/**
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* @brief SPI2 DMA priority (0..3|lowest..highest).
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* @note The priority level is used for both the TX and RX DMA streams but
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* because of the streams ordering the RX stream has always priority
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* over the TX stream.
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*/
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#if !defined(STM32_SPI_SPI2_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI2_DMA_PRIORITY 1
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#endif
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/**
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* @brief SPI3 DMA priority (0..3|lowest..highest).
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* @note The priority level is used for both the TX and RX DMA streams but
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* because of the streams ordering the RX stream has always priority
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* over the TX stream.
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*/
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#if !defined(STM32_SPI_SPI3_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI3_DMA_PRIORITY 1
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#endif
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/**
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* @brief SPI4 DMA priority (0..3|lowest..highest).
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* @note The priority level is used for both the TX and RX DMA streams but
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* because of the streams ordering the RX stream has always priority
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* over the TX stream.
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*/
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#if !defined(STM32_SPI_SPI4_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI4_DMA_PRIORITY 1
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#endif
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/**
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* @brief SPI5 DMA priority (0..3|lowest..highest).
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* @note The priority level is used for both the TX and RX DMA streams but
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* because of the streams ordering the RX stream has always priority
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* over the TX stream.
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*/
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#if !defined(STM32_SPI_SPI5_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI5_DMA_PRIORITY 1
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#endif
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/**
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* @brief SPI6 DMA priority (0..3|lowest..highest).
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* @note The priority level is used for both the TX and RX DMA streams but
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* because of the streams ordering the RX stream has always priority
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* over the TX stream.
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*/
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#if !defined(STM32_SPI_SPI6_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_SPI_SPI6_DMA_PRIORITY 1
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#endif
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/**
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* @brief SPI DMA error hook.
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*/
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#if !defined(STM32_SPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
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#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
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#endif
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if STM32_SPI_USE_SPI1 && !STM32_HAS_SPI1
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#error "SPI1 not present in the selected device"
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#endif
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#if STM32_SPI_USE_SPI2 && !STM32_HAS_SPI2
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#error "SPI2 not present in the selected device"
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#endif
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#if STM32_SPI_USE_SPI3 && !STM32_HAS_SPI3
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#error "SPI3 not present in the selected device"
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#endif
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#if STM32_SPI_USE_SPI4 && !STM32_HAS_SPI4
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#error "SPI4 not present in the selected device"
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#endif
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#if STM32_SPI_USE_SPI5 && !STM32_HAS_SPI5
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#error "SPI5 not present in the selected device"
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#endif
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#if STM32_SPI_USE_SPI6 && !STM32_HAS_SPI6
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#error "SPI6 not present in the selected device"
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#endif
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#if !STM32_SPI_USE_SPI1 && !STM32_SPI_USE_SPI2 && !STM32_SPI_USE_SPI3 && \
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!STM32_SPI_USE_SPI4 && !STM32_SPI_USE_SPI5 && !STM32_SPI_USE_SPI6
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#error "SPI driver activated but no SPI peripheral assigned"
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#endif
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#if STM32_SPI_USE_SPI1 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI1_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to SPI1"
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#endif
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#if STM32_SPI_USE_SPI2 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI2_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to SPI2"
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#endif
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#if STM32_SPI_USE_SPI3 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI3_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to SPI3"
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#endif
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#if STM32_SPI_USE_SPI4 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI4_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to SPI4"
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#endif
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#if STM32_SPI_USE_SPI5 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI5_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to SPI5"
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#endif
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#if STM32_SPI_USE_SPI6 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(STM32_SPI_SPI6_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to SPI6"
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#endif
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/* Check on the presence of the DMA streams settings in mcuconf.h.*/
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#if STM32_SPI_USE_SPI1 && (!defined(STM32_SPI_SPI1_RX_DMA_STREAM) || \
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!defined(STM32_SPI_SPI1_TX_DMA_STREAM))
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#error "SPI1 DMA streams not defined"
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#endif
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#if STM32_SPI_USE_SPI2 && (!defined(STM32_SPI_SPI2_RX_DMA_STREAM) || \
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!defined(STM32_SPI_SPI2_TX_DMA_STREAM))
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#error "SPI2 DMA streams not defined"
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#endif
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#if STM32_SPI_USE_SPI3 && (!defined(STM32_SPI_SPI3_RX_DMA_STREAM) || \
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!defined(STM32_SPI_SPI3_TX_DMA_STREAM))
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#error "SPI3 DMA streams not defined"
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#endif
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#if STM32_SPI_USE_SPI4 && (!defined(STM32_SPI_SPI4_RX_DMA_STREAM) || \
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!defined(STM32_SPI_SPI4_TX_DMA_STREAM))
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#error "SPI4 DMA streams not defined"
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#endif
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#if STM32_SPI_USE_SPI5 && (!defined(STM32_SPI_SPI5_RX_DMA_STREAM) || \
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!defined(STM32_SPI_SPI5_TX_DMA_STREAM))
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#error "SPI5 DMA streams not defined"
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#endif
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#if STM32_SPI_USE_SPI6 && (!defined(STM32_SPI_SPI6_RX_BDMA_STREAM) || \
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!defined(STM32_SPI_SPI6_TX_BDMA_STREAM))
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#error "SPI6 BDMA streams not defined"
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#endif
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/* Check on the validity of the assigned DMA streams.*/
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#if STM32_SPI_USE_SPI1 && \
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!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI1_RX_DMA_STREAM)
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#error "Invalid DMA stream assigned to SPI1 RX"
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#endif
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#if STM32_SPI_USE_SPI1 && \
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!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI1_TX_DMA_STREAM)
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#error "Invalid DMA stream assigned to SPI1 TX"
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#endif
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#if STM32_SPI_USE_SPI2 && \
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!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM)
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#error "Invalid DMA stream assigned to SPI2 RX"
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#endif
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#if STM32_SPI_USE_SPI2 && \
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!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM)
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#error "Invalid DMA stream assigned to SPI2 TX"
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#endif
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#if STM32_SPI_USE_SPI3 && \
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!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI3_RX_DMA_STREAM)
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#error "Invalid DMA stream assigned to SPI3 RX"
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#endif
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#if STM32_SPI_USE_SPI3 && \
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!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM)
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#error "Invalid DMA stream assigned to SPI3 TX"
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#endif
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#if STM32_SPI_USE_SPI4 && \
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!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI4_RX_DMA_STREAM)
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#error "Invalid DMA stream assigned to SPI4 RX"
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#endif
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#if STM32_SPI_USE_SPI4 && \
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!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI4_TX_DMA_STREAM)
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#error "Invalid DMA stream assigned to SPI4 TX"
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#endif
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#if STM32_SPI_USE_SPI5 && \
|
||||
!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI5_RX_DMA_STREAM)
|
||||
#error "Invalid DMA stream assigned to SPI5 RX"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI5 && \
|
||||
!STM32_DMA_IS_VALID_STREAM(STM32_SPI_SPI5_TX_DMA_STREAM)
|
||||
#error "Invalid DMA stream assigned to SPI5 TX"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI6 && \
|
||||
!STM32_BDMA_IS_VALID_STREAM(STM32_SPI_SPI6_RX_BDMA_STREAM)
|
||||
#error "Invalid BDMA stream assigned to SPI6 RX"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI6 && \
|
||||
!STM32_BDMA_IS_VALID_STREAM(STM32_SPI_SPI6_TX_BDMA_STREAM)
|
||||
#error "Invalid BDMA stream assigned to SPI6 TX"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI1 && \
|
||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI1_DMA_PRIORITY)
|
||||
#error "Invalid DMA priority assigned to SPI1"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI2 && \
|
||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI2_DMA_PRIORITY)
|
||||
#error "Invalid DMA priority assigned to SPI2"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI3 && \
|
||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI3_DMA_PRIORITY)
|
||||
#error "Invalid DMA priority assigned to SPI3"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI4 && \
|
||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI4_DMA_PRIORITY)
|
||||
#error "Invalid DMA priority assigned to SPI4"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI5 && \
|
||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI5_DMA_PRIORITY)
|
||||
#error "Invalid DMA priority assigned to SPI5"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI6 && \
|
||||
!STM32_DMA_IS_VALID_PRIORITY(STM32_SPI_SPI6_DMA_PRIORITY)
|
||||
#error "Invalid DMA priority assigned to SPI6"
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI1 || STM32_SPI_USE_SPI2 || STM32_SPI_USE_SPI3 || \
|
||||
STM32_SPI_USE_SPI4 || STM32_SPI_USE_SPI5
|
||||
#define STM32_SPI_DMA_REQUIRED
|
||||
#if !defined(STM32_DMA_REQUIRED)
|
||||
#define STM32_DMA_REQUIRED
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI6
|
||||
#define STM32_SPI_BDMA_REQUIRED
|
||||
#if !defined(STM32_BDMA_REQUIRED)
|
||||
#define STM32_BDMA_REQUIRED
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if SPI_SELECT_MODE == SPI_SELECT_MODE_LLD
|
||||
#error "SPI_SELECT_MODE_LLD not supported by this driver"
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver data structures and types. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver macros. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if (defined(STM32_SPI_DMA_REQUIRED) && \
|
||||
defined(STM32_SPI_BDMA_REQUIRED)) || defined(__DOXYGEN__)
|
||||
#define spi_lld_driver_fields \
|
||||
/* Pointer to the SPIx registers block.*/ \
|
||||
SPI_TypeDef *spi; \
|
||||
/** DMA type for this instance.*/ \
|
||||
bool is_bdma; \
|
||||
/** Union of the RX DMA streams.*/ \
|
||||
union { \
|
||||
/* Receive DMA stream.*/ \
|
||||
const stm32_dma_stream_t *dma; \
|
||||
/* Receive BDMA stream.*/ \
|
||||
const stm32_bdma_stream_t *bdma; \
|
||||
} rx; \
|
||||
/* Union of the TX DMA streams.*/ \
|
||||
union { \
|
||||
/* Transmit DMA stream.*/ \
|
||||
const stm32_dma_stream_t *dma; \
|
||||
/* Transmit DMA stream.*/ \
|
||||
const stm32_bdma_stream_t *bdma; \
|
||||
} tx; \
|
||||
/* RX DMA mode bit mask.*/ \
|
||||
uint32_t rxdmamode; \
|
||||
/* TX DMA mode bit mask.*/ \
|
||||
uint32_t txdmamode; \
|
||||
/* Sink for discarded data.*/ \
|
||||
uint32_t rxsink; \
|
||||
/* Source for default TX pattern.*/ \
|
||||
uint32_t txsource
|
||||
#endif
|
||||
|
||||
#if defined(STM32_SPI_DMA_REQUIRED) && !defined(STM32_SPI_BDMA_REQUIRED)
|
||||
#define spi_lld_driver_fields \
|
||||
/* Pointer to the SPIx registers block.*/ \
|
||||
SPI_TypeDef *spi; \
|
||||
/** Union of the RX DMA streams.*/ \
|
||||
union { \
|
||||
/* Receive DMA stream.*/ \
|
||||
const stm32_dma_stream_t *dma; \
|
||||
} rx; \
|
||||
/* Union of the TX DMA streams.*/ \
|
||||
union { \
|
||||
/* Transmit DMA stream.*/ \
|
||||
const stm32_dma_stream_t *dma; \
|
||||
} tx; \
|
||||
/* RX DMA mode bit mask.*/ \
|
||||
uint32_t rxdmamode; \
|
||||
/* TX DMA mode bit mask.*/ \
|
||||
uint32_t txdmamode; \
|
||||
/* Sink for discarded data.*/ \
|
||||
uint32_t rxsink; \
|
||||
/* Source for default TX pattern.*/ \
|
||||
uint32_t txsource
|
||||
#endif
|
||||
|
||||
#if !defined(STM32_SPI_DMA_REQUIRED) && defined(STM32_SPI_BDMA_REQUIRED)
|
||||
#define spi_lld_driver_fields \
|
||||
/* Pointer to the SPIx registers block.*/ \
|
||||
SPI_TypeDef *spi; \
|
||||
/** Union of the RX DMA streams.*/ \
|
||||
union { \
|
||||
/* Receive BDMA stream.*/ \
|
||||
const stm32_bdma_stream_t *bdma; \
|
||||
} rx; \
|
||||
/* Union of the TX DMA streams.*/ \
|
||||
union { \
|
||||
/* Transmit DMA stream.*/ \
|
||||
const stm32_bdma_stream_t *bdma; \
|
||||
} tx; \
|
||||
/* RX DMA mode bit mask.*/ \
|
||||
uint32_t rxdmamode; \
|
||||
/* TX DMA mode bit mask.*/ \
|
||||
uint32_t txdmamode; \
|
||||
/* Sink for discarded data.*/ \
|
||||
uint32_t rxsink; \
|
||||
/* Source for default TX pattern.*/ \
|
||||
uint32_t txsource
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Low level fields of the SPI configuration structure.
|
||||
*/
|
||||
#define spi_lld_config_fields \
|
||||
/* SPI CFG1 register initialization data.*/ \
|
||||
uint32_t cfg1; \
|
||||
/* SPI CFG2 register initialization data.*/ \
|
||||
uint32_t cfg2
|
||||
|
||||
/*===========================================================================*/
|
||||
/* External declarations. */
|
||||
/*===========================================================================*/
|
||||
|
||||
#if STM32_SPI_USE_SPI1 && !defined(__DOXYGEN__)
|
||||
extern SPIDriver SPID1;
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI2 && !defined(__DOXYGEN__)
|
||||
extern SPIDriver SPID2;
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI3 && !defined(__DOXYGEN__)
|
||||
extern SPIDriver SPID3;
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI4 && !defined(__DOXYGEN__)
|
||||
extern SPIDriver SPID4;
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI5 && !defined(__DOXYGEN__)
|
||||
extern SPIDriver SPID5;
|
||||
#endif
|
||||
|
||||
#if STM32_SPI_USE_SPI6 && !defined(__DOXYGEN__)
|
||||
extern SPIDriver SPID6;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void spi_lld_init(void);
|
||||
msg_t spi_lld_start(SPIDriver *spip);
|
||||
void spi_lld_stop(SPIDriver *spip);
|
||||
#if (SPI_SELECT_MODE == SPI_SELECT_MODE_LLD) || defined(__DOXYGEN__)
|
||||
void spi_lld_select(SPIDriver *spip);
|
||||
void spi_lld_unselect(SPIDriver *spip);
|
||||
#endif
|
||||
msg_t spi_lld_ignore(SPIDriver *spip, size_t n);
|
||||
msg_t spi_lld_exchange(SPIDriver *spip, size_t n,
|
||||
const void *txbuf, void *rxbuf);
|
||||
msg_t spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
|
||||
msg_t spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
|
||||
msg_t spi_lld_stop_transfer(SPIDriver *spip, size_t *sizep);
|
||||
uint32_t spi_lld_polled_exchange(SPIDriver *spip, uint32_t frame);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* HAL_USE_SPI */
|
||||
|
||||
#endif /* HAL_SPI_LLD_H */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -43,6 +43,11 @@
|
|||
/* Driver constants. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @brief Requires use of SPIv2 driver model.
|
||||
*/
|
||||
#define HAL_LLD_SELECT_SPI_V2 TRUE
|
||||
|
||||
/**
|
||||
* @name Platform identification macros
|
||||
* @{
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ include $(CHIBIOS)/os/hal/ports/STM32/LLD/MDMAv1/driver.mk
|
|||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/OTGv1/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv2/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SDMMCv2/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv3/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SPIv3/driver_v2.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/RNGv1/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/RTCv2/driver.mk
|
||||
include $(CHIBIOS)/os/hal/ports/STM32/LLD/SYSTICKv1/driver.mk
|
||||
|
|
|
|||
|
|
@ -35,41 +35,45 @@
|
|||
/*===========================================================================*/
|
||||
|
||||
void spi_circular_cb(SPIDriver *spip);
|
||||
void spi_error_cb(SPIDriver *spip);
|
||||
|
||||
/*
|
||||
* Circular SPI configuration (25MHz, CPHA=0, CPOL=0, MSb first).
|
||||
*/
|
||||
const SPIConfig c_spicfg = {
|
||||
true,
|
||||
spi_circular_cb,
|
||||
GPIOD,
|
||||
14,
|
||||
SPI_CFG1_MBR_DIV8 | SPI_CFG1_DSIZE_VALUE(7),
|
||||
0
|
||||
.circular = true,
|
||||
.data_cb = spi_circular_cb,
|
||||
.error_cb = spi_error_cb,
|
||||
.ssport = GPIOD,
|
||||
.sspad = 14U,
|
||||
.cfg1 = SPI_CFG1_MBR_DIV8 | SPI_CFG1_DSIZE_VALUE(7),
|
||||
.cfg2 = 0U
|
||||
};
|
||||
|
||||
/*
|
||||
* Maximum speed SPI configuration (25MHz, CPHA=0, CPOL=0, MSb first).
|
||||
*/
|
||||
const SPIConfig hs_spicfg = {
|
||||
false,
|
||||
NULL,
|
||||
GPIOD,
|
||||
14,
|
||||
SPI_CFG1_MBR_DIV8 | SPI_CFG1_DSIZE_VALUE(7),
|
||||
0
|
||||
.circular = false,
|
||||
.data_cb = NULL,
|
||||
.error_cb = spi_error_cb,
|
||||
.ssport = GPIOD,
|
||||
.sspad = 14U,
|
||||
.cfg1 = SPI_CFG1_MBR_DIV8 | SPI_CFG1_DSIZE_VALUE(7),
|
||||
.cfg2 = 0U
|
||||
};
|
||||
|
||||
/*
|
||||
* Low speed SPI configuration (1.5625MHz, CPHA=0, CPOL=0, MSb first).
|
||||
*/
|
||||
const SPIConfig ls_spicfg = {
|
||||
false,
|
||||
NULL,
|
||||
GPIOD,
|
||||
14,
|
||||
SPI_CFG1_MBR_DIV128 | SPI_CFG1_DSIZE_VALUE(7),
|
||||
0
|
||||
.circular = false,
|
||||
.data_cb = NULL,
|
||||
.error_cb = spi_error_cb,
|
||||
.ssport = GPIOD,
|
||||
.sspad = 14U,
|
||||
.cfg1 = SPI_CFG1_MBR_DIV128 | SPI_CFG1_DSIZE_VALUE(7),
|
||||
.cfg2 = 0U
|
||||
};
|
||||
|
||||
/*===========================================================================*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue