git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7401 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio
parent
b2ea156265
commit
18e6c991a7
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@ -63,6 +63,7 @@ _port_get_cpsr:
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.code 32
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mrs r0, CPSR
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bx lr
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.endfunc
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.balign 16
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.code 16
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@ -78,6 +79,7 @@ _port_disable_thumb:
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orr r3, #F_BIT
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msr CPSR_c, r3
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bx lr
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.endfunc
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.balign 16
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.code 16
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@ -87,7 +89,6 @@ _port_suspend_thumb:
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// Goes into _port_unlock_thumb
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.code 16
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.thumb_func
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.global _port_lock_thumb
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_port_lock_thumb:
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mov r3, pc
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@ -95,6 +96,7 @@ _port_lock_thumb:
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.code 32
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msr CPSR_c, #MODE_SYS | I_BIT
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bx lr
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.endfunc
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.balign 16
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.code 16
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@ -104,7 +106,6 @@ _port_enable_thumb:
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// Goes into _port_unlock_thumb
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.code 16
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.thumb_func
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.global _port_unlock_thumb
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_port_unlock_thumb:
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mov r3, pc
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@ -112,6 +113,7 @@ _port_unlock_thumb:
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.code 32
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msr CPSR_c, #MODE_SYS
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bx lr
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.endfunc
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#endif /* defined(THUMB_PRESENT) */
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.balign 16
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@ -138,6 +140,7 @@ _port_switch_arm:
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#else /* !defined(THUMB_PRESENT)T */
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ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc}
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#endif /* !defined(THUMB_PRESENT) */
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.endfunc
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/*
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* Common IRQ code. It expects a macro ARM_IRQ_VECTOR_REG with the address
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@ -168,14 +171,7 @@ Irq_Handler:
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ldr r0, [r0]
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ldr lr, =_port_irq_common // ISR return point.
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bx r0 // Calling the ISR.
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#if 0
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stmfd sp!, {r0-r3, r12, lr}
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ldr r0, =ARM_IRQ_VECTOR_REG
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ldr r0, [r0]
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ldr lr, =_port_irq_common
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bx r0
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#endif
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.endfunc
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/*
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* Common exit point for all IRQ routines, it performs the rescheduling if
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@ -204,20 +200,15 @@ Irq_Handler:
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* SP-> | r4 | -+
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* Low +------------+
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*/
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#if defined(THUMB_NO_INTERWORKING)
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.balign 16
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.code 16
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.thumb_func
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#else /* !defined(THUMB_NO_INTERWORKING) */
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.balign 16
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.code 32
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.func
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#endif
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.globl _port_irq_common
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_port_irq_common:
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msr CPSR_c, #MODE_SYS | I_BIT
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bl chSchIsPreemptionRequired
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cmp r0, #0
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jne noschd
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beq noschd
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#if CH_DBG_SYSTEM_STATE_CHECK
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bl _dbg_check_lock
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#endif
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@ -226,12 +217,6 @@ _port_irq_common:
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bl _dbg_check_unlock
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#endif
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noschd:
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#if defined(THUMB_NO_INTERWORKING)
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mov lr, pc
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bx lr
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.code 32
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#endif
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msr CPSR_c, #MODE_SYS | I_BIT
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ldmfd sp!, {r0, r1} // Pop R0=SPSR, R1=LR_IRQ.
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msr CPSR_c, #MODE_IRQ | I_BIT
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msr SPSR_fsxc, r0
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@ -240,78 +225,7 @@ noschd:
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ldmfd sp!, {r0-r3, r12, lr}
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msr CPSR_c, #MODE_IRQ | I_BIT
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subs pc, lr, #4
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#if 0
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#if defined(THUMB_NO_INTERWORKING)
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.code 16
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.thumb_func
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.globl _port_irq_common
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_port_irq_common:
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bl chSchIsPreemptionRequired
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mov lr, pc
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bx lr
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.code 32
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#else /* !defined(THUMB_NO_INTERWORKING) */
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.code 32
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.globl _port_irq_common
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_port_irq_common:
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bl chSchIsPreemptionRequired
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#endif /* !defined(THUMB_NO_INTERWORKING) */
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cmp r0, #0 // Simply returns if a
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ldmeqfd sp!, {r0-r3, r12, lr} // reschedule is not
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subeqs pc, lr, #4 // required.
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// Saves the IRQ mode registers in the system stack.
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ldmfd sp!, {r0-r3, r12, lr} // IRQ stack now empty.
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msr CPSR_c, #MODE_SYS | I_BIT
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stmfd sp!, {r0-r3, r12, lr} // Registers on System Stack.
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msr CPSR_c, #MODE_IRQ | I_BIT
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mrs r0, SPSR
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mov r1, lr
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msr CPSR_c, #MODE_SYS | I_BIT
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stmfd sp!, {r0, r1} // Push R0=SPSR, R1=LR_IRQ.
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// Context switch.
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#if defined(THUMB_NO_INTERWORKING)
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add r0, pc, #1
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bx r0
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.code 16
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#if CH_DBG_SYSTEM_STATE_CHECK
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bl _dbg_check_lock
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#endif
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bl chSchDoReschedule
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#if CH_DBG_SYSTEM_STATE_CHECK
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bl _dbg_check_unlock
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#endif
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mov lr, pc
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bx lr
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.code 32
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#else /* !defined(THUMB_NO_INTERWORKING) */
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#if CH_DBG_SYSTEM_STATE_CHECK
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bl _dbg_check_lock
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#endif
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bl chSchDoReschedule
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#if CH_DBG_SYSTEM_STATE_CHECK
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bl _dbg_check_unlock
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#endif
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#endif /* !defined(THUMB_NO_INTERWORKING) */
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// Re-establish the IRQ conditions again.
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ldmfd sp!, {r0, r1} // Pop R0=SPSR, R1=LR_IRQ.
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msr CPSR_c, #MODE_IRQ | I_BIT
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msr SPSR_fsxc, r0
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mov lr, r1
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msr CPSR_c, #MODE_SYS | I_BIT
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ldmfd sp!, {r0-r3, r12, lr}
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msr CPSR_c, #MODE_IRQ | I_BIT
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subs pc, lr, #4
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#endif
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.endfunc
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/*
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* Threads trampoline code.
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@ -320,6 +234,7 @@ _port_irq_common:
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*/
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.balign 16
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.code 32
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.func
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.globl _port_thread_start
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_port_thread_start:
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#if defined(THUMB_NO_INTERWORKING)
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@ -340,6 +255,7 @@ _port_thread_start:
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mov lr, pc
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bx r4
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bl chThdExit
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.endfunc
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#if 0
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#if CH_DBG_SYSTEM_STATE_CHECK
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