Added PowerPC documentation files. Few fixes to the startup file.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1647 35acf78f-673a-0410-8e92-d51de3d6d3f4
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gdisirio
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@ -584,6 +584,8 @@ INPUT = ../docs/src \
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../os/ports/GCC/ARM7/chcoreasm.s \
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../os/ports/GCC/ARMCM3 \
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../os/ports/GCC/ARMCM3/crt0.s \
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../os/ports/GCC/PPC \
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../os/ports/GCC/PPC/crt0.s \
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../os/ports/GCC/MSP430 \
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../os/ports/GCC/AVR \
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../os/hal \
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@ -63,7 +63,7 @@
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* used by the interrupt handlers.<br>
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* The default for this value is @p 32, this space is allocated for each
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* thread so be careful in order to not waste precious RAM space.<br>
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* The default value is set into <b>./ports/AVR/chcore.h</b>.
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* The default value is set into <b>./os/ports/GCC/AVR/chcore.h</b>.
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* .
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* @ingroup AVR
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*/
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@ -69,7 +69,7 @@
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* used by the interrupt handlers.<br>
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* The default for this value is @p 32, this space is allocated for each
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* thread so be careful in order to not waste precious RAM space.<br>
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* The default value is set into <b>./ports/MSP430/chcore.h</b>.
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* The default value is set into <b>./os/ports/GCC/MSP430/chcore.h</b>.
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* .
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* @ingroup MSP430
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*/
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@ -18,10 +18,10 @@
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*/
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/**
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* @file PPCE200Z/chcore.h
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* @brief PowerPC E200Zx architecture port macros and structures.
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* @file PPC/chcore.h
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* @brief PowerPC architecture port macros and structures.
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*
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* @addtogroup PPCE200Z_CORE
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* @addtogroup PPC_CORE
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* @{
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*/
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@ -18,9 +18,10 @@
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*/
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/**
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* @file PPCE200Z/chtypes.h
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* @brief PPC E200Zx architecture port system types.
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* @addtogroup PPCE200Z_CORE
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* @file PPC/chtypes.h
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* @brief PowerPC architecture port system types.
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*
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* @addtogroup PPC_CORE
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* @{
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*/
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@ -38,8 +38,20 @@ _boot_address:
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li %r0, 0
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stwu %r0, -8(%r1)
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/*
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* Early initialization.
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*/
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* IVPR initialization.
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*/
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lis %r4, __ivpr_base__@h
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mtIVPR %r4
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/*
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* Small sections registers initialization.
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*/
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lis %r2, __sdata2_start__@h
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ori %r2, %r2, __sdata2_start__@l
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lis %r13, __sdata_start__@h
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ori %r13, %r13, __sdata_start__@l
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/*
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* Early initialization.
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*/
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bl hwinit0
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/*
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* BSS clearing.
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@ -74,18 +86,6 @@ _boot_address:
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addi %r5, %r5, 4
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b .dataloop
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.dataend:
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/*
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* Small sections registers initialization.
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*/
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lis %r2, __sdata2_start__@h
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ori %r2, %r2, __sdata2_start__@l
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lis %r13, __sdata_start__@h
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ori %r13, %r13, __sdata_start__@l
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/*
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* IVPR initialization.
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*/
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lis %r4, __ivpr_base__@h
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mtIVPR %r4
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/*
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* Late initialization.
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*/
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@ -0,0 +1,128 @@
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @defgroup PPC PowerPC
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* @details PowerPC port details. This section describes how the ChibiOS/RT
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* features are implemented on this architecture.
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*
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* @section PPC_STATES Mapping of the System States in the PowerPC port
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* The ChibiOS/RT logical @ref system_states are mapped as follow in the
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* PowerPC port:
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* - <b>Init</b>. This state is represented by the startup code and the
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* initialization code before @p chSysInit() is executed. It has not a
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* special hardware state associated.
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* - <b>Normal</b>. This is the state the system has after executing
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* @p chSysInit(). Interrupts are enabled.
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* - <b>Suspended</b>. Interrupts are disabled.
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* - <b>Disabled</b>. Interrupts are enabled. This state is equivalent to the
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* Suspended state because there are no fast interrupts in this architecture.
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* - <b>Sleep</b>. This state is entered with the execution of the specific
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* instruction @p <b>wait</b>.
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* - <b>S-Locked</b>. Interrupts are disabled.
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* - <b>I-Locked</b>. This state is equivalent to the SRI state, the
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* @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in
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* order to formally change state because this may change).
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* - <b>Serving Regular Interrupt</b>. Normal interrupt service code.
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* - <b>Serving Fast Interrupt</b>. Not present in this architecture.
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* - <b>Serving Non-Maskable Interrupt</b>. The PowerPC has several non
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* maskable interrupt sources that can be associated to this state.
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* - <b>Halted</b>. Implemented as an infinite loop with interrupts disabled.
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* .
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* @section PPC_NOTES The PowerPC port notes
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* The PowerPC port is organized as follow:
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* - The @p main() function is invoked in privileged mode.
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* - Each thread has a private stack with extra storage for interrupts
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* servicing.
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* - The Book-E Decrementer Timer, mapped on IVOR10, is used for system tick.
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* - Interrupt nesting is not currently supported.
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* .
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* @ingroup ports
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*/
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/**
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* @defgroup PPC_CONF Configuration Options
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* @brief PowerPC Configuration Options.
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* @details The PowerPC port allows some architecture-specific configurations
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* settings that can be specified externally, as example on the compiler
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* command line:
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* - @p INT_REQUIRED_STACK, this value represent the amount of stack space used
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* by an interrupt handler between the @p extctx and @p intctx
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* structures.
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* The default for this value is @p 128 bytes, this space is allocated for
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* each thread so be careful in order to not waste precious RAM space.<br>
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* The default value is set into <b>./os/ports/GCC/PPC/chcore.h</b>.
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* - @p ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the @p <b>wait</b>
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* instruction from within the idle loop. This is defaulted to 0 because
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* it can create problems with some debuggers. Setting this option to 1
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* reduces the system power requirements.
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* .
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* @ingroup PPC
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*/
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/**
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* @defgroup PPC_CORE Core Port Implementation
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* @brief PowerPC specific port code, structures and macros.
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*
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* @ingroup PPC
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*/
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/**
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* @defgroup PPC_STARTUP Startup Support
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* @brief PPC startup code support.
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* @details ChibiOS/RT provides its own generic startup file for the PowerPC
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* port.
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* Of course it is not mandatory to use it but care should be taken about the
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* startup phase details.
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*
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* <h2>Startup Process</h2>
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* The startup process, as implemented, is the following:
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* -# The stacks pointer is initialized into the area defined in the linker
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* script.
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* -# The IVPR register is setup according to the linker script.
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* -# The R2 and R13 registers are set to pointer to the SDA areas according
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* to the EABI specification.
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* -# An early initialization routine @p hwinit0 is invoked, if the symbol is
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* not defined then an empty default routine is executed (weak symbol).
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* -# DATA and BSS segments are initialized.
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* -# A late initialization routine @p hwinit1 is invoked, if the symbol not
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* defined then an empty default routine is executed (weak symbol).<br>
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* This late initialization function is also the proper place for a
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* @a bootloader, if your application requires one.
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* -# The @p main() function is invoked with the parameters @p argc and @p argv
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* set to zero.
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* -# Should the @p main() function return a branch is performed to the weak
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* symbol @p main_exit. The default code is an endless empty loop.
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* .
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* <h2>Expected linker symbols</h2>
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* The startup code starts at the symbol @p _boot_address and expects the
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* following symbols to be defined in the linker script:
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* - @p __ram_end__ RAM end location +1.
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* - @p __sdata2_start__ small constants data area
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* - @p __sdata_start__ small variables data area
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* - @p __romdata_start__ address of the data segment source read only data.
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* - @p __data_start__ data segment start location.
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* - @p __data_end__ data segment end location +1.
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* - @p __bss_start__ BSS start location.
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* - @p __bss_end__ BSS end location +1.
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* - @p __ivpr_base__ IVPR register initialization address.
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* .
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* @ingroup PPC
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* @file PPC/crt0.s Startup code.
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*/
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