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ChibiOS
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1796 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2010-03-27 16:15:55 +00:00
parent 783f4514f1
commit 193bbcc9dd
1 changed files with 74 additions and 11 deletions
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83
os/hal/platforms/LPC11xx/hal_lld.h
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@ -41,12 +41,18 @@
#define PLATFORM_NAME "LPC11xx"
#define IRCOSCCLK 12000000 /**< High speed internal clock. */
#define WDGOSCCLK 12000000 /**< Watchdog internal clock. */
#define SYSPLLCLKSEL_IRCOCS 0 /**< Internal RC oscillator
clock source. */
#define SYSPLLCLKSEL_SYSOSC 1 /**< System oscillator clock
source. */
#define SYSMAINCLKSEL_IRCOCS 0
#define SYSMAINCLKSEL_PLLIN 1
#define SYSMAINCLKSEL_WDGOSC 2
#define SYSMAINCLKSEL_PLLOUT 3
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@ -54,8 +60,8 @@
/**
* @brief System PLL clock source.
*/
#if !defined(LPC11xx_SYSPLL_SOURCE) || defined(__DOXYGEN__)
#define LPC11xx_SYSPLLCLKSEL SYSPLLCLKSEL_SYSOSC
#if !defined(LPC11xx_PLLCLK_SOURCE) || defined(__DOXYGEN__)
#define LPC11xx_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC
#endif
/**
@ -67,31 +73,88 @@
#define LPC11xx_SYSPLL_MUL 16
#endif
/**
* @brief System PLL divider.
* @note The value must be chosen between (2, 4, 8, 16).
*/
#if !defined(LPC11xx_SYSPLL_DIV) || defined(__DOXYGEN__)
#define LPC11xx_SYSPLL_DIV 4
#endif
/**
* @brief System main clock source.
*/
#if !defined(LPC11xx_MAINCLK_SOURCE) || defined(__DOXYGEN__)
#define LPC11xx_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT
#endif
/**
* @brief AHB divider.
* @note The value must be chosen between (1...255).
*/
#if !defined(LPC11xx_SYSCLK_DIV) || defined(__DOXYGEN__)
#define LPC11xx_SYSCLK_DIV 1
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
#if LPC11xx_SYSPLLCLKSEL == SYSPLLCLKSEL_SYSOSC
/**
* @brief PLL input clock frequency.
*/
#if (LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC) || defined(__DOXYGEN__)
#define LPC11xx_SYSPLLCLKIN SYSOSCCLK
#elif LPC11xx_SYSPLLCLKSEL == SYSPLLCLKSEL_IRCOCS
#elif LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_IRCOCS
#define LPC11xx_SYSPLLCLKIN IRCOSCCLK
#else
#error "invalid LPC11xx_SYSPLLCLKSEL clock source specified"
#error "invalid LPC11xx_PLLCLK_SOURCE clock source specified"
#endif
#if (LPC11xx_SYSPLL_MUL < 1) || (LPC11xx_SYSPLL_MUL > 32)
#error "LPC11xx_SYSPLL_MUL out of range (1...32)"
#endif
/**
* @brief PLL output clock.
*/
#define LPC11xx_SYSPLLCLKOUT (LPC11xx_SYSPLLCLKIN * LPC11xx_SYSPLL_MUL)
#if (LPC11xx_SYSPLL_DIV != 2) && (LPC11xx_SYSPLL_DIV != 4) && \
(LPC11xx_SYSPLL_DIV != 8) && (LPC11xx_SYSPLL_DIV != 16)
#error "invalid LPC11xx_SYSPLL_DIV value (2,4,8,16)"
#endif
#if (LPC11xx_SYSPLLCLKOUT < 156000000) || (LPC11xx_SYSPLLCLKOUT > 320000000)
/**
* @brief CCP frequency.
*/
#define LPC11xx_SYSPLLCCO (LPC11xx_SYSPLLCLKIN * LPC11xx_SYSPLL_MUL)
#if (LPC11xx_SYSPLLCCO < 156000000) || (LPC11xx_SYSPLLCCO > 320000000)
#error "CCO frequency out of the acceptable range (156...320)"
#endif
/**
* @brief PLL output clock frequency.
*/
#define LPC11xx_SYSPLLCLKOUT (LPC11xx_SYSPLLCCO / LPC11xx_SYSPLL_DIV)
#if (LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_IRCOCS) || defined(__DOXYGEN__)
#define LPC11xx_MAINCLK IRCOSCCLK
#elif LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLIN
#define LPC11xx_MAINCLK LPC11xx_SYSPLLCLKIN
#elif LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_WDGOSC
#define LPC11xx_MAINCLK WDGOSCCLK
#elif LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT
#define LPC11xx_MAINCLK LPC11xx_SYSPLLCLKOUT
#else
#error "invalid LPC11xx_MAINCLK_SOURCE clock source specified"
#endif
/**
* @brief AHB clock.
*/
#define LPC11xx_SYSCLK (LPC11xx_MAINCLK / LPC11xx_SYSCLK_DIV)
#if LPC11xx_SYSCLK > 50000000
#error "AHB clock frequency out of the acceptable range (50MHz max)"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/