From 1a3c934a2790dc2cb6810c9adfbab5718b7c2607 Mon Sep 17 00:00:00 2001
From: Giovanni Di Sirio <gdisirio@gmail.com>
Date: Sat, 5 Jun 2021 07:16:28 +0000
Subject: [PATCH] Documentation improvements.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14481 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
---
 os/rt/include/chsys.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/os/rt/include/chsys.h b/os/rt/include/chsys.h
index fef83d657..c41db48d3 100644
--- a/os/rt/include/chsys.h
+++ b/os/rt/include/chsys.h
@@ -52,12 +52,24 @@
 /* Derived constants and error checks.                                       */
 /*===========================================================================*/
 
+/**
+ * @brief   Core zero memory affinity macro.
+ * @note    The memory is meant to be reachable by both cores but
+ *          preferred by core zero.
+ * @note    Only uninitialized variables can be tagged with this attribute.
+ */
 #if defined(PORT_CORE0_BSS_SECTION) || defined(__DOXYGEN__)
 #define CH_SYS_CORE0_MEMORY             PORT_CORE0_BSS_SECTION
 #else
 #define CH_SYS_CORE0_MEMORY             /* Default.*/
 #endif
 
+/**
+ * @brief   Core one memory affinity macro.
+ * @note    The memory is meant to be reachable by both cores but
+ *          preferred by core one.
+ * @note    Only uninitialized variables can be tagged with this attribute.
+ */
 #if defined(PORT_CORE1_BSS_SECTION) || defined(__DOXYGEN__)
 #define CH_SYS_CORE1_MEMORY             PORT_CORE1_BSS_SECTION
 #else