Proper support for rev-V and newer ones.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13309 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
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@ -150,7 +150,7 @@ CPPWARN = -Wall -Wextra -Wundef
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#
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# List all user C define here, like -D_DEBUG=1
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UDEFS =
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UDEFS = -DSTM32_ENFORCE_H7_REV_V # Must be removed for non-Rev-V devices.
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# Define ASM defines here
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UADEFS =
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@ -97,9 +97,9 @@ static inline void init_pwr(void) {
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(void)pwr;
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#endif
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PWR->CR1 = STM32_PWR_CR1 | 0xF0000000;
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PWR->CR1 = STM32_PWR_CR1 | 0xF0000000U;
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PWR->CR2 = STM32_PWR_CR2;
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PWR->CR3 = STM32_PWR_CR3;
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PWR->CR3 = STM32_PWR_CR3 | 0x00000004U; /* SCUEN enforced. */
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PWR->CPUCR = STM32_PWR_CPUCR;
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PWR->D3CR = STM32_VOS;
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#if !defined(STM32_ENFORCE_H7_REV_V)
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@ -135,8 +135,9 @@ void hal_lld_init(void) {
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board files.*/
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rccResetAHB1(~0);
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rccResetAHB2(~0);
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rccResetAHB3(~(RCC_AHB3RSTR_FMCRST));
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rccResetAHB4(~(STM32_GPIO_EN_MASK));
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rccResetAHB3(~(RCC_AHB3RSTR_FMCRST |
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0x80000000U)); /* Was RCC_AHB3RSTR_CPURST in Rev-V.*/
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rccResetAHB4(~(RCC_APB4RSTR_SYSCFGRST | STM32_GPIO_EN_MASK));
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rccResetAPB1L(~0);
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rccResetAPB1H(~0);
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rccResetAPB2(~0);
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@ -205,13 +206,17 @@ void stm32_clock_init(void) {
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#endif
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#if STM32_NO_INIT == FALSE
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#if !defined(STM32_DISABLE_ERRATA_2_2_15)
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#if defined(STM32_ENFORCE_H7_REV_V)
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/* Fix for errata 2.2.15: Reading from AXI SRAM might lead to data
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read corruption.
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AXI->TARG7_FN_MOD.*/
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*((volatile uint32_t *)(0x51000000 + 0x1108 + 0x7000)) = 0x00000001U;
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#endif
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/* SYSCFG clock enabled here because it is a multi-functional unit shared
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among multiple drivers.*/
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rccEnableAPB4(RCC_APB4ENR_SYSCFGEN, true);
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/* PWR initialization.*/
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init_pwr();
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@ -402,10 +407,6 @@ void stm32_clock_init(void) {
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rccEnableSRAM1(true);
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rccEnableSRAM2(true);
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rccEnableSRAM3(true);
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/* SYSCFG clock enabled here because it is a multi-functional unit shared
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among multiple drivers.*/
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rccEnableAPB4(RCC_APB4ENR_SYSCFGEN, true);
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}
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/** @} */
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