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Proper support for rev-V and newer ones. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13309 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2020-01-29 09:38:45 +00:00
parent 3d22c7bd6e
commit 1a5c3d0cfc
2 changed files with 11 additions and 10 deletions
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2
demos/STM32/RT-STM32H743I-NUCLEO144/Makefile
View File

@ -150,7 +150,7 @@ CPPWARN = -Wall -Wextra -Wundef
# #
# List all user C define here, like -D_DEBUG=1 # List all user C define here, like -D_DEBUG=1
UDEFS = UDEFS = -DSTM32_ENFORCE_H7_REV_V # Must be removed for non-Rev-V devices.
# Define ASM defines here # Define ASM defines here
UADEFS = UADEFS =

19
os/hal/ports/STM32/STM32H7xx/hal_lld.c
View File

@ -97,9 +97,9 @@ static inline void init_pwr(void) {
(void)pwr; (void)pwr;
#endif #endif
PWR->CR1 = STM32_PWR_CR1 | 0xF0000000; PWR->CR1 = STM32_PWR_CR1 | 0xF0000000U;
PWR->CR2 = STM32_PWR_CR2; PWR->CR2 = STM32_PWR_CR2;
PWR->CR3 = STM32_PWR_CR3; PWR->CR3 = STM32_PWR_CR3 | 0x00000004U; /* SCUEN enforced. */
PWR->CPUCR = STM32_PWR_CPUCR; PWR->CPUCR = STM32_PWR_CPUCR;
PWR->D3CR = STM32_VOS; PWR->D3CR = STM32_VOS;
#if !defined(STM32_ENFORCE_H7_REV_V) #if !defined(STM32_ENFORCE_H7_REV_V)
@ -135,8 +135,9 @@ void hal_lld_init(void) {
board files.*/ board files.*/
rccResetAHB1(~0); rccResetAHB1(~0);
rccResetAHB2(~0); rccResetAHB2(~0);
rccResetAHB3(~(RCC_AHB3RSTR_FMCRST)); rccResetAHB3(~(RCC_AHB3RSTR_FMCRST |
rccResetAHB4(~(STM32_GPIO_EN_MASK)); 0x80000000U)); /* Was RCC_AHB3RSTR_CPURST in Rev-V.*/
rccResetAHB4(~(RCC_APB4RSTR_SYSCFGRST | STM32_GPIO_EN_MASK));
rccResetAPB1L(~0); rccResetAPB1L(~0);
rccResetAPB1H(~0); rccResetAPB1H(~0);
rccResetAPB2(~0); rccResetAPB2(~0);
@ -205,13 +206,17 @@ void stm32_clock_init(void) {
#endif #endif
#if STM32_NO_INIT == FALSE #if STM32_NO_INIT == FALSE
#if !defined(STM32_DISABLE_ERRATA_2_2_15) #if defined(STM32_ENFORCE_H7_REV_V)
/* Fix for errata 2.2.15: Reading from AXI SRAM might lead to data /* Fix for errata 2.2.15: Reading from AXI SRAM might lead to data
read corruption. read corruption.
AXI->TARG7_FN_MOD.*/ AXI->TARG7_FN_MOD.*/
*((volatile uint32_t *)(0x51000000 + 0x1108 + 0x7000)) = 0x00000001U; *((volatile uint32_t *)(0x51000000 + 0x1108 + 0x7000)) = 0x00000001U;
#endif #endif
/* SYSCFG clock enabled here because it is a multi-functional unit shared
among multiple drivers.*/
rccEnableAPB4(RCC_APB4ENR_SYSCFGEN, true);
/* PWR initialization.*/ /* PWR initialization.*/
init_pwr(); init_pwr();
@ -402,10 +407,6 @@ void stm32_clock_init(void) {
rccEnableSRAM1(true); rccEnableSRAM1(true);
rccEnableSRAM2(true); rccEnableSRAM2(true);
rccEnableSRAM3(true); rccEnableSRAM3(true);
/* SYSCFG clock enabled here because it is a multi-functional unit shared
among multiple drivers.*/
rccEnableAPB4(RCC_APB4ENR_SYSCFGEN, true);
} }
/** @} */ /** @} */