git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5416 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio
parent
2e1184107a
commit
1c0fb671da
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@ -137,6 +137,7 @@
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#define SPC5_ETIMER1_CLK SPC5_MCONTROL_CLK
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#define SPC5_HAS_ETIMER2 FALSE
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/** @} */
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#endif /* _SPC560P_REGISTRY_H_ */
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@ -13,7 +13,7 @@
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*/
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/**
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* @file SPC56ELxx/spc560p_registry.h
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* @file SPC56ELxx/spc56el_registry.h
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* @brief SPC56ELxx capabilities registry.
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*
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* @addtogroup HAL
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@ -186,6 +186,7 @@
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#define SPC5_ETIMER2_TC5IR_NUMBER 227
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#define SPC5_ETIMER2_RCF_NUMBER 232
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#define SPC5_ETIMER2_CLK SPC5_MCONTROL_CLK
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/** @} */
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#endif /* _SPC56EL_REGISTRY_H_ */
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@ -293,14 +293,14 @@ CH_IRQ_HANDLER(Vector140) {
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CH_IRQ_PROLOGUE();
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pr = EXTI->PR & ((1 << 21) | (1 << 22) | (1 << 23));
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pr = EXTI->PR & ((1 << 21) | (1 << 22) | (1 << 29));
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EXTI->PR = pr;
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if (pr & (1 << 21))
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EXTD1.config->channels[21].cb(&EXTD1, 21);
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if (pr & (1 << 22))
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EXTD1.config->channels[22].cb(&EXTD1, 22);
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if (pr & (1 << 23))
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EXTD1.config->channels[23].cb(&EXTD1, 23);
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if (pr & (1 << 29))
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EXTD1.config->channels[29].cb(&EXTD1, 29);
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CH_IRQ_EPILOGUE();
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}
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@ -41,6 +41,7 @@
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#define _HAL_LLD_H_
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#include "stm32.h"
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#include "stm32_registry.h"
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/*===========================================================================*/
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/* Driver constants. */
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@ -282,173 +283,6 @@
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#define STM32_UART5SW_HSI (3 << 22) /**< USART5 clock is HSI. */
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/** @} */
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/*===========================================================================*/
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/* Platform capabilities. */
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/*===========================================================================*/
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/**
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* @name STM32F30x capabilities
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* @{
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*/
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
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#define STM32_ADC1_DMA_CHN 0x00000000
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#define STM32_HAS_ADC2 TRUE
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#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) | \
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STM32_DMA_STREAM_ID_MSK(2, 3))
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#define STM32_ADC2_DMA_CHN 0x00000000
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#define STM32_HAS_ADC3 TRUE
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#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
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#define STM32_ADC3_DMA_CHN 0x00000000
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#define STM32_HAS_ADC4 TRUE
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#define STM32_ADC4_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) | \
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STM32_DMA_STREAM_ID_MSK(2, 4))
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#define STM32_ADC4_DMA_CHN 0x00000000
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/* CAN attributes.*/
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#define STM32_HAS_CAN1 TRUE
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#define STM32_HAS_CAN2 FALSE
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#define STM32_CAN_MAX_FILTERS 14
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/* DAC attributes.*/
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#define STM32_HAS_DAC TRUE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA FALSE
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#define STM32_HAS_DMA1 TRUE
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#define STM32_HAS_DMA2 TRUE
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/* ETH attributes.*/
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#define STM32_HAS_ETH FALSE
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/* EXTI attributes.*/
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#define STM32_EXTI_NUM_CHANNELS 34
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/* GPIO attributes.*/
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_GPIOI FALSE
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
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#define STM32_I2C1_RX_DMA_CHN 0x00000000
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#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
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#define STM32_I2C1_TX_DMA_CHN 0x00000000
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#define STM32_HAS_I2C2 TRUE
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#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
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#define STM32_I2C2_RX_DMA_CHN 0x00000000
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#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
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#define STM32_I2C2_TX_DMA_CHN 0x00000000
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#define STM32_HAS_I2C3 FALSE
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#define STM32_I2C3_RX_DMA_MSK 0
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#define STM32_I2C3_RX_DMA_CHN 0x00000000
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#define STM32_I2C3_TX_DMA_MSK 0
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#define STM32_I2C3_TX_DMA_CHN 0x00000000
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/* RTC attributes.*/
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#define STM32_HAS_RTC TRUE
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#define STM32_RTC_HAS_SUBSECONDS TRUE
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#define STM32_RTC_IS_CALENDAR TRUE
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/* SDIO attributes.*/
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#define STM32_HAS_SDIO FALSE
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/* SPI attributes.*/
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#define STM32_HAS_SPI1 TRUE
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#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
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#define STM32_SPI1_RX_DMA_CHN 0x00000000
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#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
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#define STM32_SPI1_TX_DMA_CHN 0x00000000
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#define STM32_HAS_SPI2 TRUE
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#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
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#define STM32_SPI2_RX_DMA_CHN 0x00000000
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#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
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#define STM32_SPI2_TX_DMA_CHN 0x00000000
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#define STM32_HAS_SPI3 TRUE
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#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1)
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#define STM32_SPI3_RX_DMA_CHN 0x00000000
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#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2)
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#define STM32_SPI3_TX_DMA_CHN 0x00000000
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/* TIM attributes.*/
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#define STM32_HAS_TIM1 TRUE
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#define STM32_HAS_TIM2 TRUE
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#define STM32_HAS_TIM3 TRUE
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#define STM32_HAS_TIM4 TRUE
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#define STM32_HAS_TIM5 FALSE
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#define STM32_HAS_TIM6 TRUE
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#define STM32_HAS_TIM7 TRUE
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#define STM32_HAS_TIM8 TRUE
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#define STM32_HAS_TIM9 FALSE
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#define STM32_HAS_TIM10 FALSE
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#define STM32_HAS_TIM11 FALSE
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#define STM32_HAS_TIM12 FALSE
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#define STM32_HAS_TIM13 FALSE
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#define STM32_HAS_TIM14 FALSE
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#define STM32_HAS_TIM15 TRUE
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#define STM32_HAS_TIM16 TRUE
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#define STM32_HAS_TIM17 TRUE
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#define STM32_HAS_TIM18 FALSE
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#define STM32_HAS_TIM19 FALSE
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/* USART attributes.*/
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#define STM32_HAS_USART1 TRUE
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#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
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#define STM32_USART1_RX_DMA_CHN 0x00000000
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#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
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#define STM32_USART1_TX_DMA_CHN 0x00000000
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#define STM32_HAS_USART2 TRUE
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#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
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#define STM32_USART2_RX_DMA_CHN 0x00000000
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#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
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#define STM32_USART2_TX_DMA_CHN 0x00000000
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#define STM32_HAS_USART3 TRUE
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#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
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#define STM32_USART3_RX_DMA_CHN 0x00000000
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#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
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#define STM32_USART3_TX_DMA_CHN 0x00000000
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#define STM32_HAS_UART4 FALSE
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#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3))
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#define STM32_UART4_RX_DMA_CHN 0x00000000
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#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
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#define STM32_UART4_TX_DMA_CHN 0x00000000
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#define STM32_HAS_UART5 FALSE
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#define STM32_UART5_RX_DMA_MSK 0
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#define STM32_UART5_RX_DMA_CHN 0x00000000
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#define STM32_UART5_TX_DMA_MSK 0
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#define STM32_UART5_TX_DMA_CHN 0x00000000
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#define STM32_HAS_USART6 FALSE
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#define STM32_USART6_RX_DMA_MSK 0
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#define STM32_USART6_RX_DMA_CHN 0x00000000
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#define STM32_USART6_TX_DMA_MSK 0
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#define STM32_USART6_TX_DMA_CHN 0x00000000
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/* USB attributes.*/
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#define STM32_HAS_USB TRUE
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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@ -0,0 +1,213 @@
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012,2013 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file STM32F30x/stm32_registry.h
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* @brief STM32F30x capabilities registry.
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef _STM32_REGISTRY_H_
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#define _STM32_REGISTRY_H_
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/*===========================================================================*/
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/* Platform capabilities. */
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/*===========================================================================*/
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/**
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* @name STM32F30x capabilities
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* @{
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*/
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
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#define STM32_ADC1_DMA_CHN 0x00000000
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#define STM32_HAS_ADC2 TRUE
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#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) | \
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STM32_DMA_STREAM_ID_MSK(2, 3))
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#define STM32_ADC2_DMA_CHN 0x00000000
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#define STM32_HAS_ADC3 TRUE
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#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
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#define STM32_ADC3_DMA_CHN 0x00000000
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#define STM32_HAS_ADC4 TRUE
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#define STM32_ADC4_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) | \
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STM32_DMA_STREAM_ID_MSK(2, 4))
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#define STM32_ADC4_DMA_CHN 0x00000000
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#define STM32_HAS_SDADC1 FALSE
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#define STM32_SDADC1_DMA_MSK 0
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#define STM32_SDADC1_DMA_CHN 0x00000000
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#define STM32_HAS_SDADC2 FALSE
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#define STM32_SDADC2_DMA_MSK 0
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#define STM32_SDADC2_DMA_CHN 0x00000000
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#define STM32_HAS_SDADC3 FALSE
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#define STM32_SDADC3_DMA_MSK 0
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#define STM32_SDADC3_DMA_CHN 0x00000000
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/* CAN attributes.*/
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#define STM32_HAS_CAN1 TRUE
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#define STM32_HAS_CAN2 FALSE
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#define STM32_CAN_MAX_FILTERS 14
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/* DAC attributes.*/
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#define STM32_HAS_DAC TRUE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA FALSE
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#define STM32_HAS_DMA1 TRUE
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#define STM32_HAS_DMA2 TRUE
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/* ETH attributes.*/
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#define STM32_HAS_ETH FALSE
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/* EXTI attributes.*/
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#define STM32_EXTI_NUM_CHANNELS 34
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/* GPIO attributes.*/
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE TRUE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_GPIOI FALSE
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
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#define STM32_I2C1_RX_DMA_CHN 0x00000000
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#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
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#define STM32_I2C1_TX_DMA_CHN 0x00000000
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#define STM32_HAS_I2C2 TRUE
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#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
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#define STM32_I2C2_RX_DMA_CHN 0x00000000
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#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
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#define STM32_I2C2_TX_DMA_CHN 0x00000000
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#define STM32_HAS_I2C3 FALSE
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#define STM32_I2C3_RX_DMA_MSK 0
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#define STM32_I2C3_RX_DMA_CHN 0x00000000
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#define STM32_I2C3_TX_DMA_MSK 0
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#define STM32_I2C3_TX_DMA_CHN 0x00000000
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/* RTC attributes.*/
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#define STM32_HAS_RTC TRUE
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#define STM32_RTC_HAS_SUBSECONDS TRUE
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#define STM32_RTC_IS_CALENDAR TRUE
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/* SDIO attributes.*/
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#define STM32_HAS_SDIO FALSE
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/* SPI attributes.*/
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#define STM32_HAS_SPI1 TRUE
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#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
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#define STM32_SPI1_RX_DMA_CHN 0x00000000
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#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
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#define STM32_SPI1_TX_DMA_CHN 0x00000000
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#define STM32_HAS_SPI2 TRUE
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#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
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#define STM32_SPI2_RX_DMA_CHN 0x00000000
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#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
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#define STM32_SPI2_TX_DMA_CHN 0x00000000
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#define STM32_HAS_SPI3 TRUE
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#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1)
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#define STM32_SPI3_RX_DMA_CHN 0x00000000
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#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2)
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#define STM32_SPI3_TX_DMA_CHN 0x00000000
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/* TIM attributes.*/
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#define STM32_HAS_TIM1 TRUE
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#define STM32_HAS_TIM2 TRUE
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#define STM32_HAS_TIM3 TRUE
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#define STM32_HAS_TIM4 TRUE
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#define STM32_HAS_TIM5 FALSE
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#define STM32_HAS_TIM6 TRUE
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#define STM32_HAS_TIM7 TRUE
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#define STM32_HAS_TIM8 TRUE
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#define STM32_HAS_TIM9 FALSE
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#define STM32_HAS_TIM10 FALSE
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#define STM32_HAS_TIM11 FALSE
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#define STM32_HAS_TIM12 FALSE
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#define STM32_HAS_TIM13 FALSE
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#define STM32_HAS_TIM14 FALSE
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#define STM32_HAS_TIM15 TRUE
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#define STM32_HAS_TIM16 TRUE
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#define STM32_HAS_TIM17 TRUE
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#define STM32_HAS_TIM18 FALSE
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#define STM32_HAS_TIM19 FALSE
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/* USART attributes.*/
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#define STM32_HAS_USART1 TRUE
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#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
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#define STM32_USART1_RX_DMA_CHN 0x00000000
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#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
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#define STM32_USART1_TX_DMA_CHN 0x00000000
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#define STM32_HAS_USART2 TRUE
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#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
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#define STM32_USART2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
|
||||
#define STM32_USART2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_USART3 TRUE
|
||||
#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
|
||||
#define STM32_USART3_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
|
||||
#define STM32_USART3_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_UART4 FALSE
|
||||
#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3))
|
||||
#define STM32_UART4_RX_DMA_CHN 0x00000000
|
||||
#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
|
||||
#define STM32_UART4_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_UART5 FALSE
|
||||
#define STM32_UART5_RX_DMA_MSK 0
|
||||
#define STM32_UART5_RX_DMA_CHN 0x00000000
|
||||
#define STM32_UART5_TX_DMA_MSK 0
|
||||
#define STM32_UART5_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_USART6 FALSE
|
||||
#define STM32_USART6_RX_DMA_MSK 0
|
||||
#define STM32_USART6_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART6_TX_DMA_MSK 0
|
||||
#define STM32_USART6_TX_DMA_CHN 0x00000000
|
||||
|
||||
/* USB attributes.*/
|
||||
#define STM32_HAS_USB TRUE
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
/** @} */
|
||||
|
||||
#endif /* _STM32_REGISTRY_H_ */
|
||||
|
||||
/** @} */
|
||||
|
|
@ -282,9 +282,9 @@ CH_IRQ_HANDLER(Vector4C) {
|
|||
}
|
||||
#endif
|
||||
|
||||
#if !defined(STM32_DISABLE_EXTI21_23_HANDLER)
|
||||
#if !defined(STM32_DISABLE_EXTI21_22_HANDLER)
|
||||
/**
|
||||
* @brief EXTI[21]...EXTI[23] interrupt handler (COMP1, COMP2, COMP3).
|
||||
* @brief EXTI[21]..EXTI[22] interrupt handler (COMP1, COMP2).
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
|
|
@ -306,50 +306,6 @@ CH_IRQ_HANDLER(Vector140) {
|
|||
}
|
||||
#endif
|
||||
|
||||
#if !defined(STM32_DISABLE_EXTI30_32_HANDLER)
|
||||
/**
|
||||
* @brief EXTI[30]...EXTI[32] interrupt handler (COMP4, COMP5, COMP6).
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(Vector144) {
|
||||
uint32_t pr;
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
pr = EXTI->PR & ((1 << 30) | (1 << 31));
|
||||
EXTI->PR = pr;
|
||||
if (pr & (1 << 30))
|
||||
EXTD1.config->channels[30].cb(&EXTD1, 30);
|
||||
if (pr & (1 << 31))
|
||||
EXTD1.config->channels[31].cb(&EXTD1, 31);
|
||||
|
||||
pr = EXTI->PR2 & (1 << 0);
|
||||
EXTI->PR2 = pr;
|
||||
if (pr & (1 << 0))
|
||||
EXTD1.config->channels[32].cb(&EXTD1, 32);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !defined(STM32_DISABLE_EXTI33_HANDLER)
|
||||
/**
|
||||
* @brief EXTI[33] interrupt handler (COMP7).
|
||||
*
|
||||
* @isr
|
||||
*/
|
||||
CH_IRQ_HANDLER(RTC_WKUP_IRQHandler) {
|
||||
|
||||
CH_IRQ_PROLOGUE();
|
||||
|
||||
EXTI->PR2 = (1 << 1);
|
||||
EXTD1.config->channels[33].cb(&EXTD1, 33);
|
||||
|
||||
CH_IRQ_EPILOGUE();
|
||||
}
|
||||
#endif
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver exported functions. */
|
||||
/*===========================================================================*/
|
||||
|
|
@ -386,11 +342,7 @@ void ext_lld_exti_irq_enable(void) {
|
|||
nvicEnableVector(RTC_WKUP_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY));
|
||||
nvicEnableVector(COMP1_2_3_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_23_IRQ_PRIORITY));
|
||||
nvicEnableVector(COMP4_5_6_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI30_32_IRQ_PRIORITY));
|
||||
nvicEnableVector(COMP7_IRQn,
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI33_IRQ_PRIORITY));
|
||||
CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_22_29_IRQ_PRIORITY));
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -413,8 +365,6 @@ void ext_lld_exti_irq_disable(void) {
|
|||
nvicDisableVector(TAMPER_STAMP_IRQn);
|
||||
nvicDisableVector(RTC_WKUP_IRQn);
|
||||
nvicDisableVector(COMP1_2_3_IRQn);
|
||||
nvicDisableVector(COMP4_5_6_IRQn);
|
||||
nvicDisableVector(COMP7_IRQn);
|
||||
}
|
||||
|
||||
#endif /* HAL_USE_EXT */
|
||||
|
|
|
|||
|
|
@ -128,24 +128,10 @@
|
|||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI21..23 interrupt priority level setting.
|
||||
* @brief EXTI21..22 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI21_23_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI21_22_29_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI30..32 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI30_32_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief EXTI33 interrupt priority level setting.
|
||||
*/
|
||||
#if !defined(STM32_EXT_EXTI33_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI33_IRQ_PRIORITY 6
|
||||
#if !defined(STM32_EXT_EXTI21_22_IRQ_PRIORITY) || defined(__DOXYGEN__)
|
||||
#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 6
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
|
|
|
|||
|
|
@ -41,6 +41,7 @@
|
|||
#define _HAL_LLD_H_
|
||||
|
||||
#include "stm32.h"
|
||||
#include "stm32_registry.h"
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver constants. */
|
||||
|
|
@ -263,173 +264,6 @@
|
|||
#define STM32_USART3SW_HSI (3 << 18) /**< USART3 clock is HSI. */
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Platform capabilities. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name STM32F37x capabilities
|
||||
* @{
|
||||
*/
|
||||
/* ADC attributes.*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
|
||||
#define STM32_ADC1_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_ADC2 TRUE
|
||||
#define STM32_ADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1) | \
|
||||
STM32_DMA_STREAM_ID_MSK(2, 3))
|
||||
#define STM32_ADC2_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_ADC3 TRUE
|
||||
#define STM32_ADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
|
||||
#define STM32_ADC3_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_ADC4 TRUE
|
||||
#define STM32_ADC4_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2) | \
|
||||
STM32_DMA_STREAM_ID_MSK(2, 4))
|
||||
#define STM32_ADC4_DMA_CHN 0x00000000
|
||||
|
||||
/* CAN attributes.*/
|
||||
#define STM32_HAS_CAN1 TRUE
|
||||
#define STM32_HAS_CAN2 FALSE
|
||||
#define STM32_CAN_MAX_FILTERS 14
|
||||
|
||||
/* DAC attributes.*/
|
||||
#define STM32_HAS_DAC TRUE
|
||||
|
||||
/* DMA attributes.*/
|
||||
#define STM32_ADVANCED_DMA FALSE
|
||||
#define STM32_HAS_DMA1 TRUE
|
||||
#define STM32_HAS_DMA2 TRUE
|
||||
|
||||
/* ETH attributes.*/
|
||||
#define STM32_HAS_ETH FALSE
|
||||
|
||||
/* EXTI attributes.*/
|
||||
#define STM32_EXTI_NUM_CHANNELS 34
|
||||
|
||||
/* GPIO attributes.*/
|
||||
#define STM32_HAS_GPIOA TRUE
|
||||
#define STM32_HAS_GPIOB TRUE
|
||||
#define STM32_HAS_GPIOC TRUE
|
||||
#define STM32_HAS_GPIOD TRUE
|
||||
#define STM32_HAS_GPIOE TRUE
|
||||
#define STM32_HAS_GPIOF TRUE
|
||||
#define STM32_HAS_GPIOG FALSE
|
||||
#define STM32_HAS_GPIOH FALSE
|
||||
#define STM32_HAS_GPIOI FALSE
|
||||
|
||||
/* I2C attributes.*/
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
|
||||
#define STM32_I2C1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
|
||||
#define STM32_I2C1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_I2C2 TRUE
|
||||
#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
|
||||
#define STM32_I2C2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
|
||||
#define STM32_I2C2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_I2C3 FALSE
|
||||
#define STM32_I2C3_RX_DMA_MSK 0
|
||||
#define STM32_I2C3_RX_DMA_CHN 0x00000000
|
||||
#define STM32_I2C3_TX_DMA_MSK 0
|
||||
#define STM32_I2C3_TX_DMA_CHN 0x00000000
|
||||
|
||||
/* RTC attributes.*/
|
||||
#define STM32_HAS_RTC TRUE
|
||||
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
||||
#define STM32_RTC_IS_CALENDAR TRUE
|
||||
|
||||
/* SDIO attributes.*/
|
||||
#define STM32_HAS_SDIO FALSE
|
||||
|
||||
/* SPI attributes.*/
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
||||
#define STM32_SPI1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
||||
#define STM32_SPI1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_SPI2 TRUE
|
||||
#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
||||
#define STM32_SPI2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
||||
#define STM32_SPI2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_SPI3 TRUE
|
||||
#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1)
|
||||
#define STM32_SPI3_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2)
|
||||
#define STM32_SPI3_TX_DMA_CHN 0x00000000
|
||||
|
||||
/* TIM attributes.*/
|
||||
#define STM32_HAS_TIM1 TRUE
|
||||
#define STM32_HAS_TIM2 TRUE
|
||||
#define STM32_HAS_TIM3 TRUE
|
||||
#define STM32_HAS_TIM4 TRUE
|
||||
#define STM32_HAS_TIM5 FALSE
|
||||
#define STM32_HAS_TIM6 TRUE
|
||||
#define STM32_HAS_TIM7 TRUE
|
||||
#define STM32_HAS_TIM8 TRUE
|
||||
#define STM32_HAS_TIM9 FALSE
|
||||
#define STM32_HAS_TIM10 FALSE
|
||||
#define STM32_HAS_TIM11 FALSE
|
||||
#define STM32_HAS_TIM12 FALSE
|
||||
#define STM32_HAS_TIM13 FALSE
|
||||
#define STM32_HAS_TIM14 FALSE
|
||||
#define STM32_HAS_TIM15 TRUE
|
||||
#define STM32_HAS_TIM16 TRUE
|
||||
#define STM32_HAS_TIM17 TRUE
|
||||
#define STM32_HAS_TIM18 TRUE
|
||||
#define STM32_HAS_TIM19 TRUE
|
||||
|
||||
/* USART attributes.*/
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
|
||||
#define STM32_USART1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
|
||||
#define STM32_USART1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
|
||||
#define STM32_USART2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
|
||||
#define STM32_USART2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_USART3 TRUE
|
||||
#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
|
||||
#define STM32_USART3_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
|
||||
#define STM32_USART3_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_UART4 FALSE
|
||||
#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3))
|
||||
#define STM32_UART4_RX_DMA_CHN 0x00000000
|
||||
#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
|
||||
#define STM32_UART4_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_UART5 FALSE
|
||||
#define STM32_UART5_RX_DMA_MSK 0
|
||||
#define STM32_UART5_RX_DMA_CHN 0x00000000
|
||||
#define STM32_UART5_TX_DMA_MSK 0
|
||||
#define STM32_UART5_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_USART6 FALSE
|
||||
#define STM32_USART6_RX_DMA_MSK 0
|
||||
#define STM32_USART6_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART6_TX_DMA_MSK 0
|
||||
#define STM32_USART6_TX_DMA_CHN 0x00000000
|
||||
|
||||
/* USB attributes.*/
|
||||
#define STM32_HAS_USB TRUE
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Driver pre-compile time settings. */
|
||||
/*===========================================================================*/
|
||||
|
|
|
|||
|
|
@ -0,0 +1,211 @@
|
|||
/*
|
||||
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
|
||||
2011,2012,2013 Giovanni Di Sirio.
|
||||
|
||||
This file is part of ChibiOS/RT.
|
||||
|
||||
ChibiOS/RT is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
ChibiOS/RT is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file STM32F37x/stm32_registry.h
|
||||
* @brief STM32F37x capabilities registry.
|
||||
*
|
||||
* @addtogroup HAL
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef _STM32_REGISTRY_H_
|
||||
#define _STM32_REGISTRY_H_
|
||||
|
||||
/*===========================================================================*/
|
||||
/* Platform capabilities. */
|
||||
/*===========================================================================*/
|
||||
|
||||
/**
|
||||
* @name STM32F37x capabilities
|
||||
* @{
|
||||
*/
|
||||
/* ADC attributes.*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
|
||||
#define STM32_ADC1_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_ADC2 FALSE
|
||||
#define STM32_ADC2_DMA_MSK 0
|
||||
#define STM32_ADC2_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_ADC3 FALSE
|
||||
#define STM32_ADC3_DMA_MSK 0
|
||||
#define STM32_ADC3_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_ADC4 FALSE
|
||||
#define STM32_ADC4_DMA_MSK 0
|
||||
#define STM32_ADC4_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_SDADC1 TRUE
|
||||
#define STM32_SDADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3))
|
||||
#define STM32_SDADC1_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_SDADC2 TRUE
|
||||
#define STM32_SDADC2_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4))
|
||||
#define STM32_SDADC2_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_SDADC3 TRUE
|
||||
#define STM32_SDADC3_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
|
||||
#define STM32_SDADC3_DMA_CHN 0x00000000
|
||||
|
||||
/* CAN attributes.*/
|
||||
#define STM32_HAS_CAN1 TRUE
|
||||
#define STM32_HAS_CAN2 FALSE
|
||||
#define STM32_CAN_MAX_FILTERS 14
|
||||
|
||||
/* DAC attributes.*/
|
||||
#define STM32_HAS_DAC TRUE
|
||||
|
||||
/* DMA attributes.*/
|
||||
#define STM32_ADVANCED_DMA FALSE
|
||||
#define STM32_HAS_DMA1 TRUE
|
||||
#define STM32_HAS_DMA2 TRUE
|
||||
|
||||
/* ETH attributes.*/
|
||||
#define STM32_HAS_ETH FALSE
|
||||
|
||||
/* EXTI attributes.*/
|
||||
#define STM32_EXTI_NUM_CHANNELS 29
|
||||
|
||||
/* GPIO attributes.*/
|
||||
#define STM32_HAS_GPIOA TRUE
|
||||
#define STM32_HAS_GPIOB TRUE
|
||||
#define STM32_HAS_GPIOC TRUE
|
||||
#define STM32_HAS_GPIOD TRUE
|
||||
#define STM32_HAS_GPIOE TRUE
|
||||
#define STM32_HAS_GPIOF TRUE
|
||||
#define STM32_HAS_GPIOG FALSE
|
||||
#define STM32_HAS_GPIOH FALSE
|
||||
#define STM32_HAS_GPIOI FALSE
|
||||
|
||||
/* I2C attributes.*/
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
|
||||
#define STM32_I2C1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
|
||||
#define STM32_I2C1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_I2C2 TRUE
|
||||
#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
|
||||
#define STM32_I2C2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
|
||||
#define STM32_I2C2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_I2C3 FALSE
|
||||
#define STM32_I2C3_RX_DMA_MSK 0
|
||||
#define STM32_I2C3_RX_DMA_CHN 0x00000000
|
||||
#define STM32_I2C3_TX_DMA_MSK 0
|
||||
#define STM32_I2C3_TX_DMA_CHN 0x00000000
|
||||
|
||||
/* RTC attributes.*/
|
||||
#define STM32_HAS_RTC TRUE
|
||||
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
||||
#define STM32_RTC_IS_CALENDAR TRUE
|
||||
|
||||
/* SDIO attributes.*/
|
||||
#define STM32_HAS_SDIO FALSE
|
||||
|
||||
/* SPI attributes.*/
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2)
|
||||
#define STM32_SPI1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3)
|
||||
#define STM32_SPI1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_SPI2 TRUE
|
||||
#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
|
||||
#define STM32_SPI2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
|
||||
#define STM32_SPI2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_SPI3 TRUE
|
||||
#define STM32_SPI3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1)
|
||||
#define STM32_SPI3_RX_DMA_CHN 0x00000000
|
||||
#define STM32_SPI3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2)
|
||||
#define STM32_SPI3_TX_DMA_CHN 0x00000000
|
||||
|
||||
/* TIM attributes.*/
|
||||
#define STM32_HAS_TIM1 TRUE
|
||||
#define STM32_HAS_TIM2 TRUE
|
||||
#define STM32_HAS_TIM3 TRUE
|
||||
#define STM32_HAS_TIM4 TRUE
|
||||
#define STM32_HAS_TIM5 FALSE
|
||||
#define STM32_HAS_TIM6 TRUE
|
||||
#define STM32_HAS_TIM7 TRUE
|
||||
#define STM32_HAS_TIM8 TRUE
|
||||
#define STM32_HAS_TIM9 FALSE
|
||||
#define STM32_HAS_TIM10 FALSE
|
||||
#define STM32_HAS_TIM11 FALSE
|
||||
#define STM32_HAS_TIM12 FALSE
|
||||
#define STM32_HAS_TIM13 FALSE
|
||||
#define STM32_HAS_TIM14 FALSE
|
||||
#define STM32_HAS_TIM15 TRUE
|
||||
#define STM32_HAS_TIM16 TRUE
|
||||
#define STM32_HAS_TIM17 TRUE
|
||||
#define STM32_HAS_TIM18 TRUE
|
||||
#define STM32_HAS_TIM19 TRUE
|
||||
|
||||
/* USART attributes.*/
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
|
||||
#define STM32_USART1_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
|
||||
#define STM32_USART1_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
|
||||
#define STM32_USART2_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
|
||||
#define STM32_USART2_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_USART3 TRUE
|
||||
#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
|
||||
#define STM32_USART3_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
|
||||
#define STM32_USART3_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_UART4 FALSE
|
||||
#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 3))
|
||||
#define STM32_UART4_RX_DMA_CHN 0x00000000
|
||||
#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 5))
|
||||
#define STM32_UART4_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_UART5 FALSE
|
||||
#define STM32_UART5_RX_DMA_MSK 0
|
||||
#define STM32_UART5_RX_DMA_CHN 0x00000000
|
||||
#define STM32_UART5_TX_DMA_MSK 0
|
||||
#define STM32_UART5_TX_DMA_CHN 0x00000000
|
||||
|
||||
#define STM32_HAS_USART6 FALSE
|
||||
#define STM32_USART6_RX_DMA_MSK 0
|
||||
#define STM32_USART6_RX_DMA_CHN 0x00000000
|
||||
#define STM32_USART6_TX_DMA_MSK 0
|
||||
#define STM32_USART6_TX_DMA_CHN 0x00000000
|
||||
|
||||
/* USB attributes.*/
|
||||
#define STM32_HAS_USB TRUE
|
||||
#define STM32_HAS_OTG1 FALSE
|
||||
#define STM32_HAS_OTG2 FALSE
|
||||
/** @} */
|
||||
|
||||
#endif /* _STM32_REGISTRY_H_ */
|
||||
|
||||
/** @} */
|
||||
Loading…
Reference in New Issue