From 1c48d25c587a32aa029b4bcac78eff552a654876 Mon Sep 17 00:00:00 2001
From: Giovanni Di Sirio <gdisirio@gmail.com>
Date: Sat, 7 Nov 2015 07:48:30 +0000
Subject: [PATCH] Fixed bug #665.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8436 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/ports/STM32/STM32F3xx/adc_lld.c   | 10 +++++++++-
 os/hal/ports/STM32/STM32F3xx/stm32_rcc.h | 24 ++++++++++++++++++++++++
 readme.txt                               |  2 ++
 3 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/os/hal/ports/STM32/STM32F3xx/adc_lld.c b/os/hal/ports/STM32/STM32F3xx/adc_lld.c
index f19765b96..35f79b20a 100644
--- a/os/hal/ports/STM32/STM32F3xx/adc_lld.c
+++ b/os/hal/ports/STM32/STM32F3xx/adc_lld.c
@@ -93,7 +93,7 @@ static void adc_lld_vreg_on(ADCDriver *adcp) {
 #if STM32_ADC_DUAL_MODE
   adcp->adcs->CR = ADC_CR_ADVREGEN_0;
 #endif
-  osalSysPolledDelayX(US2RTC(STM32_HCLK, 10));
+  osalSysPolledDelayX(OSAL_US2RTC(STM32_HCLK, 10));
 }
 
 /**
@@ -326,7 +326,11 @@ void adc_lld_init(void) {
 #if STM32_ADC_USE_ADC1
   /* Driver initialization.*/
   adcObjectInit(&ADCD1);
+#if defined(ADC1_2_COMMON)
   ADCD1.adcc = ADC1_2_COMMON;
+#else
+  ADCD1.adcc = ADC1_COMMON;
+#endif
   ADCD1.adcm = ADC1;
 #if STM32_ADC_DUAL_MODE
   ADCD1.adcs = ADC2;
@@ -343,7 +347,11 @@ void adc_lld_init(void) {
 #if STM32_ADC_USE_ADC3
   /* Driver initialization.*/
   adcObjectInit(&ADCD3);
+#if defined(ADC3_4_COMMON)
   ADCD3.adcc = ADC3_4_COMMON;
+#else
+  ADCD3.adcc = ADC3_COMMON;
+#endif
   ADCD3.adcm = ADC3;
 #if STM32_ADC_DUAL_MODE
   ADCD3.adcs = ADC4;
diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h
index 19aa6850a..253d4c115 100644
--- a/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h
@@ -171,7 +171,11 @@
  *
  * @api
  */
+#if defined(RCC_AHBENR_ADC12EN) || defined(__DOXYGEN__)
 #define rccEnableADC12(lp) rccEnableAHB(RCC_AHBENR_ADC12EN, lp)
+#else
+#define rccEnableADC12(lp) rccEnableAHB(RCC_AHBENR_ADC1EN, lp)
+#endif
 
 /**
  * @brief   Disables the ADC1/ADC2 peripheral clock.
@@ -180,14 +184,22 @@
  *
  * @api
  */
+#if defined(RCC_AHBENR_ADC12EN) || defined(__DOXYGEN__)
 #define rccDisableADC12(lp) rccDisableAHB(RCC_AHBENR_ADC12EN, lp)
+#else
+#define rccDisableADC12(lp) rccDisableAHB(RCC_AHBENR_ADC1EN, lp)
+#endif
 
 /**
  * @brief   Resets the ADC1/ADC2 peripheral.
  *
  * @api
  */
+#if defined(RCC_AHBRSTR_ADC12RST) || defined(__DOXYGEN__)
 #define rccResetADC12() rccResetAHB(RCC_AHBRSTR_ADC12RST)
+#else
+#define rccResetADC12() rccResetAHB(RCC_AHBRSTR_ADC1RST)
+#endif
 
 /**
  * @brief   Enables the ADC3/ADC4 peripheral clock.
@@ -196,7 +208,11 @@
  *
  * @api
  */
+#if defined(RCC_AHBENR_ADC34EN) || defined(__DOXYGEN__)
 #define rccEnableADC34(lp) rccEnableAHB(RCC_AHBENR_ADC34EN, lp)
+#else
+#define rccEnableADC34(lp) rccEnableAHB(RCC_AHBENR_ADC3EN, lp)
+#endif
 
 /**
  * @brief   Disables the ADC3/ADC4 peripheral clock.
@@ -205,14 +221,22 @@
  *
  * @api
  */
+#if defined(RCC_AHBENR_ADC34EN) || defined(__DOXYGEN__)
 #define rccDisableADC34(lp) rccDisableAHB(RCC_AHBENR_ADC34EN, lp)
+#else
+#define rccDisableADC34(lp) rccDisableAHB(RCC_AHBENR_ADC3EN, lp)
+#endif
 
 /**
  * @brief   Resets the ADC3/ADC4 peripheral.
  *
  * @api
  */
+#if defined(RCC_AHBRSTR_ADC34RST) || defined(__DOXYGEN__)
 #define rccResetADC34() rccResetAHB(RCC_AHBRSTR_ADC34RST)
+#else
+#define rccResetADC34() rccResetAHB(RCC_AHBRSTR_ADC3RST)
+#endif
 /** @} */
 
 /**
diff --git a/readme.txt b/readme.txt
index d1472f495..3cd2d010e 100644
--- a/readme.txt
+++ b/readme.txt
@@ -130,6 +130,8 @@
 - HAL: Updated STM32F0xx headers to STM32CubeF0 version 1.3.0. Added support
        for STM32F030xC, STM32F070x6, STM32F070xB, STM32F091xC,
        STM32F098xx devices.
+- HAL: Fixed differences in STM32F3 ADC macro definitions (bug #665)
+       (backported to 3.0.3).
 - HAL: Fixed invalid class type for sdPutWouldBlock() and sdGetWouldBlock()
        functions (bug #659)(backported to 3.0.3 and 2.6.10).
 - HAL: Fixed STM32F0xx HAL missing MCOPRE support (bug #658).