Implemented ADuCM36x Serial lld
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13107 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Rocco Marco Guglielmi
parent
a4caa90fb3
commit
1dc0acd5a6
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file ADUCM36x/hal_serial_lld.c
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* @brief ADUCM serial subsystem low level driver source.
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*
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* @addtogroup SERIAL
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* @{
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*/
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#include "hal.h"
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#if HAL_USE_SERIAL || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/**
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* @name ADUCM UART Fractional BR Divider register's bitfields.
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* @{
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*/
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#define ADUCM_COMFBR_ENABLE COMFBR_ENABLE_EN
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#define ADUCM_COMFBR_DIVM(m) ((m) << 11U)
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#define ADUCM_COMFBR_DIVN(n) ((n) << 0U)
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief USART1 serial driver identifier.*/
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#if (ADUCM_SERIAL_USE_UART0 == TRUE) || defined(__DOXYGEN__)
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SerialDriver SD0;
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#endif
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/**
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* @brief Driver default configuration.
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*/
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static const SerialConfig default_config = {
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SERIAL_DEFAULT_BITRATE,
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COMLCR_WLS_8BITS
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};
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#if ADUCM_SERIAL_USE_UART0 || defined(__DOXYGEN__)
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/** @brief Input buffer for SD0.*/
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static uint8_t sd_in_buf0[ADUCM_SERIAL_UART0_IN_BUF_SIZE];
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/** @brief Output buffer for SD0.*/
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static uint8_t sd_out_buf0[ADUCM_SERIAL_UART0_OUT_BUF_SIZE];
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#endif
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief USART initialization.
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* @details This function must be invoked with interrupts disabled.
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*
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* @param[in] sdp pointer to a @p SerialDriver object
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* @param[in] config the architecture-dependent serial driver configuration
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*/
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static void uart_init(SerialDriver *sdp, const SerialConfig *config) {
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uint32_t comdiv, divn, divm;
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/* Reseting the UART state machine. */
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sdp->uart->COMCON = COMCON_DISABLE_EN;
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/* Baud rate setting.*/
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osalDbgAssert(((sdp->clock / 32U) > config->speed),
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"invalid baud rate vs input clock");
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/* The Baudrate comes from the formula:
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BR = (UDIV/DIV) / (32 * comdiv) / (M + N/2048)
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Whereas:
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- 0 < comdiv < 65536
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- 0 <= M < 4
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- 0 <= N < 2048
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The following computation is deduced from the fact the the maximum value
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of M is 3 and that N/2048 is always smaller than 1.
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Thus, is it possible to find M and comdiv in an interative way increasing
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comdiv until M does not reaches an allowed value.
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Once founded comdiv and M it is possible to find N inverting the equation.
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Note that N only refines the value introducing a decimal part to the last
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dividend.
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*/
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comdiv = 1U;
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divm = sdp->clock / config->speed / 32U / comdiv;
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while(divm > 3U) {
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comdiv++;
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divm = sdp->clock / config->speed / 32U / comdiv;
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}
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osalDbgAssert((divm <= 3), "invalid divm value");
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osalDbgAssert((comdiv <= 65535U) && (comdiv >= 1), "invalid comdiv value");
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divn = (uint32_t)((((uint64_t)sdp->clock * 2048U) / config->speed / 32U /
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comdiv) - (divm * 2048U));
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osalDbgAssert((divn <= 2047), "invalid divn value");
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sdp->uart->COMFBR = ADUCM_COMFBR_ENABLE | ADUCM_COMFBR_DIVM(divm) |
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ADUCM_COMFBR_DIVN(divn);
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sdp->uart->COMDIV = comdiv;
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/* Line and modem configurations*/
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sdp->uart->COMLCR = config->lcr;
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sdp->uart->COMIEN = COMIEN_EDMAR_DIS | COMIEN_EDMAT_DIS | COMIEN_EDSSI_EN |
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COMIEN_ELSI_EN | COMIEN_ETBEI_EN | COMIEN_ERBFI_EN;
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sdp->uart->COMCON = COMCON_DISABLE_DIS;
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}
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/**
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* @brief USART de-initialization.
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* @details This function must be invoked with interrupts disabled.
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*
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* @param[in] sdp pointer to a @p SerialDriver object
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*/
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static void uart_deinit(SerialDriver *sdp) {
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sdp->uart->COMIEN = 0;
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sdp->uart->COMCON = COMCON_DISABLE_EN;
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}
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/**
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* @brief Error handling routine.
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*
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* @param[in] sdp pointer to a @p SerialDriver object
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* @param[in] lsr UART LSR register value
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*/
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static void set_error(SerialDriver *sdp, uint32_t lsr) {
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eventflags_t sts = 0;
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if (lsr & COMLSR_OE)
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sts |= SD_OVERRUN_ERROR;
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if (lsr & COMLSR_PE)
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sts |= SD_PARITY_ERROR;
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if (lsr & COMLSR_FE)
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sts |= SD_FRAMING_ERROR;
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osalSysLockFromISR();
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chnAddFlagsI(sdp, sts);
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osalSysUnlockFromISR();
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}
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#if ADUCM_SERIAL_USE_UART0 || defined(__DOXYGEN__)
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static void notify0(io_queue_t *qp) {
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(void)qp;
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pADI_UART->COMIEN |= COMIEN_ETBEI_EN;
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}
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#endif
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if ADUCM_SERIAL_USE_UART0 || defined(__DOXYGEN__)
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#if !defined(ADUCM_UART0_HANDLER)
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#error "ADUCM_UART0_HANDLER not defined"
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#endif
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/**
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* @brief UART0 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(ADUCM_UART0_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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sd_lld_serve_interrupt(&SD0);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level serial driver initialization.
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*
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* @notapi
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*/
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void sd_lld_init(void) {
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#if ADUCM_SERIAL_USE_UART0 == TRUE
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sdObjectInit(&SD0);
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iqObjectInit(&SD0.iqueue, sd_in_buf0, sizeof sd_in_buf0, NULL, &SD0);
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oqObjectInit(&SD0.oqueue, sd_out_buf0, sizeof sd_out_buf0, notify0, &SD0);
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SD0.uart = pADI_UART;
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SD0.clock = ADUCM_UARTCLK;
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nvicEnableVector(ADUCM_UART0_NUMBER, ADUCM_SERIAL_UART0_PRIORITY);
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#endif
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}
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/**
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* @brief Low level serial driver configuration and (re)start.
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*
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* @param[in] sdp pointer to a @p SerialDriver object
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* @param[in] config the architecture-dependent serial driver configuration.
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* If this parameter is set to @p NULL then a default
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* configuration is used.
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*
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* @notapi
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*/
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void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
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if (config == NULL) {
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config = &default_config;
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}
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if (sdp->state == SD_STOP) {
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#if ADUCM_SERIAL_USE_UART0 == TRUE
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if (&SD0 == sdp) {
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ccEnableUART0();
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}
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#endif
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}
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uart_init(sdp, config);
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}
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/**
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* @brief Low level serial driver stop.
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* @details De-initializes the USART, stops the associated clock, resets the
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* interrupt vector.
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*
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* @param[in] sdp pointer to a @p SerialDriver object
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*
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* @notapi
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*/
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void sd_lld_stop(SerialDriver *sdp) {
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if (sdp->state == SD_READY) {
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/* UART is de-initialized then clocks are disabled.*/
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uart_deinit(sdp);
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#if ADUCM_SERIAL_USE_UART0 == TRUE
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if (&SD0 == sdp) {
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ccDisableUART0();
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return;
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}
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#endif
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}
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}
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/**
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* @brief Common IRQ handler.
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*
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* @param[in] sdp communication channel associated to the USART
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*/
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void sd_lld_serve_interrupt(SerialDriver *sdp) {
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uint32_t irr = sdp->uart->COMIIR;
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uint32_t ien = sdp->uart->COMIEN;
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if(!(irr & COMIIR_NINT_MSK)) {
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if(irr == COMIIR_STA_MODEMSTATUS) {
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volatile uint32_t msr;
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/* Clearing the interrupt. */
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msr = sdp->uart->COMMSR;
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(void) msr;
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}
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/* Data available, note it is a while in order to handle two situations:
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1) Another byte arrived after removing the previous one, this would cause
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an extra interrupt to serve.
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2) FIFO mode is enabled on devices that support it, we need to empty
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the FIFO.*/
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while (irr & COMIIR_STA_RXBUFFULL) {
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osalSysLockFromISR();
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sdIncomingDataI(sdp, (uint8_t)sdp->uart->COMRX);
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osalSysUnlockFromISR();
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irr = sdp->uart->COMIIR;
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}
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/* Transmission buffer empty, note it is a while in order to handle two
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situations:
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1) The data registers has been emptied immediately after writing it, this
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would cause an extra interrupt to serve.
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2) FIFO mode is enabled on devices that support it, we need to fill
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the FIFO.*/
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if (ien & COMIEN_ETBEI) {
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while (irr & COMIIR_STA_TXBUFEMPTY) {
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msg_t b;
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osalSysLockFromISR();
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b = oqGetI(&sdp->oqueue);
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if (b < MSG_OK) {
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chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
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sdp->uart->COMIEN = ien & ~COMIEN_ETBEI;
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osalSysUnlockFromISR();
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break;
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}
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sdp->uart->COMTX = b;
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osalSysUnlockFromISR();
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irr = sdp->uart->COMIIR;
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}
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}
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if(irr == COMIIR_STA_RXLINESTATUS) {
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uint32_t lsr;
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/* Clearing the interrupt. */
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lsr = sdp->uart->COMLSR;
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/* Error handling. */
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if(lsr & 0x0EU) {
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set_error(sdp, lsr);
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}
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/* Error handling. */
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if(lsr & COMLSR_TEMT) {
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set_error(sdp, lsr);
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}
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/* Physical transmission end.*/
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if (lsr & COMLSR_TEMT) {
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osalSysLockFromISR();
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if (oqIsEmptyI(&sdp->oqueue)) {
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chnAddFlagsI(sdp, CHN_TRANSMISSION_END);
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}
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osalSysUnlockFromISR();
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}
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}
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}
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}
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#endif /* HAL_USE_SERIAL == TRUE */
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/** @} */
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@ -0,0 +1,158 @@
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/*
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ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file ADUCM36x/hal_serial_lld.h
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* @brief ADUCM serial subsystem low level driver header.
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*
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* @addtogroup SERIAL
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* @{
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*/
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#ifndef HAL_SERIAL_LLD_H
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#define HAL_SERIAL_LLD_H
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#if HAL_USE_SERIAL || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Advanced buffering support switch.
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* @details This constants enables the advanced buffering support in the
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* low level driver, the queue buffer is no more part of the
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* @p SerialDriver structure, each driver can have a different
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* queue size.
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*/
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#define SERIAL_ADVANCED_BUFFERING_SUPPORT TRUE
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver pre-compile time settings. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name ADUCM configuration options
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @brief UART0 driver enable switch.
|
||||||
|
* @details If set to @p TRUE the support for UART0 is included.
|
||||||
|
* @note The default is @p FALSE.
|
||||||
|
*/
|
||||||
|
#if !defined(ADUCM_SERIAL_USE_UART0) || defined(__DOXYGEN__)
|
||||||
|
#define ADUCM_SERIAL_USE_UART0 FALSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief UART0 interrupt priority level setting.
|
||||||
|
*/
|
||||||
|
#if !defined(ADUCM_SERIAL_UART0_PRIORITY) || defined(__DOXYGEN__)
|
||||||
|
#define ADUCM_SERIAL_UART0_PRIORITY 12
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Input buffer size for UART0.
|
||||||
|
*/
|
||||||
|
#if !defined(ADUCM_SERIAL_UART0_IN_BUF_SIZE) || defined(__DOXYGEN__)
|
||||||
|
#define ADUCM_SERIAL_UART0_IN_BUF_SIZE SERIAL_BUFFERS_SIZE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Output buffer size for UART0.
|
||||||
|
*/
|
||||||
|
#if !defined(ADUCM_SERIAL_UART0_OUT_BUF_SIZE) || defined(__DOXYGEN__)
|
||||||
|
#define ADUCM_SERIAL_UART0_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE
|
||||||
|
#endif
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Derived constants and error checks. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
#if !ADUCM_SERIAL_USE_UART0
|
||||||
|
#error "SERIAL driver activated but no UART peripheral assigned"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver data structures and types. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief ADUCM Serial Driver configuration structure.
|
||||||
|
* @details An instance of this structure must be passed to @p sdStart()
|
||||||
|
* in order to configure and start a serial driver operations.
|
||||||
|
* @note This structure content is architecture dependent, each driver
|
||||||
|
* implementation defines its own version and the custom static
|
||||||
|
* initializers.
|
||||||
|
*/
|
||||||
|
typedef struct {
|
||||||
|
/**
|
||||||
|
* @brief Bit rate.
|
||||||
|
*/
|
||||||
|
uint32_t speed;
|
||||||
|
/* End of the mandatory fields.*/
|
||||||
|
/**
|
||||||
|
* @brief Initialization value for the Line Control Register.
|
||||||
|
*/
|
||||||
|
uint32_t lcr;
|
||||||
|
} SerialConfig;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief @p SerialDriver specific data.
|
||||||
|
*/
|
||||||
|
#define _serial_driver_data \
|
||||||
|
_base_asynchronous_channel_data \
|
||||||
|
/* Driver state.*/ \
|
||||||
|
sdstate_t state; \
|
||||||
|
/* Input queue.*/ \
|
||||||
|
input_queue_t iqueue; \
|
||||||
|
/* Output queue.*/ \
|
||||||
|
output_queue_t oqueue; \
|
||||||
|
/* End of the mandatory fields.*/ \
|
||||||
|
/* Pointer to the UART registers block.*/ \
|
||||||
|
ADI_UART_TypeDef *uart; \
|
||||||
|
/* Clock frequency for the associated UART.*/ \
|
||||||
|
uint32_t clock;
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* Driver macros. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
/*===========================================================================*/
|
||||||
|
/* External declarations. */
|
||||||
|
/*===========================================================================*/
|
||||||
|
|
||||||
|
#if (ADUCM_SERIAL_USE_UART0 == TRUE) && !defined(__DOXYGEN__)
|
||||||
|
extern SerialDriver SD0;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
void sd_lld_init(void);
|
||||||
|
void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
|
||||||
|
void sd_lld_stop(SerialDriver *sdp);
|
||||||
|
void sd_lld_serve_interrupt(SerialDriver *sdp);
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* HAL_USE_SERIAL == TRUE */
|
||||||
|
|
||||||
|
#endif /* HAL_SERIAL_LLD_H */
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -3,6 +3,7 @@ PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
|
||||||
$(CHIBIOS)/os/hal/ports/ADUCM/ADUCM36x/aducm_isr.c \
|
$(CHIBIOS)/os/hal/ports/ADUCM/ADUCM36x/aducm_isr.c \
|
||||||
$(CHIBIOS)/os/hal/ports/ADUCM/ADUCM36x/hal_lld.c \
|
$(CHIBIOS)/os/hal/ports/ADUCM/ADUCM36x/hal_lld.c \
|
||||||
$(CHIBIOS)/os/hal/ports/ADUCM/ADUCM36x/hal_pal_lld.c \
|
$(CHIBIOS)/os/hal/ports/ADUCM/ADUCM36x/hal_pal_lld.c \
|
||||||
|
$(CHIBIOS)/os/hal/ports/ADUCM/ADUCM36x/hal_serial_lld.c \
|
||||||
$(CHIBIOS)/os/hal/ports/ADUCM/ADUCM36x/hal_st_lld.c
|
$(CHIBIOS)/os/hal/ports/ADUCM/ADUCM36x/hal_st_lld.c
|
||||||
|
|
||||||
# Required include directories.
|
# Required include directories.
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue