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Fixed support for QUADSPI on F4xx. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10120 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Giovanni Di Sirio 2017-03-06 14:26:19 +00:00
parent 8d1dc1313c
commit 1eabe1e911
2 changed files with 32 additions and 2 deletions
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30
os/hal/ports/STM32/STM32F4xx/stm32_rcc.h
View File

@ -713,6 +713,36 @@
#define rccDisableOTG_HSULPI(lp) rccDisableAHB1(RCC_AHB1ENR_OTGHSULPIEN, lp)
/** @} */
/**
* @name QUADSPI peripherals specific RCC operations
* @{
*/
/**
* @brief Enables the QUADSPI1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccEnableQUADSPI1(lp) rccEnableAHB3(RCC_AHB3ENR_QSPIEN, lp)
/**
* @brief Disables the QUADSPI1 peripheral clock.
*
* @param[in] lp low power enable flag
*
* @api
*/
#define rccDisableQUADSPI1(lp) rccDisableAHB3(RCC_AHB3ENR_QSPIEN, lp)
/**
* @brief Resets the QUADSPI1 peripheral.
*
* @api
*/
#define rccResetQUADSPI1() rccResetAHB3(RCC_AHB3RSTR_QSPIRST)
/** @} */
/**
* @name SDIO peripheral specific RCC operations
* @{

4
os/hal/ports/STM32/STM32F4xx/stm32_registry.h
View File

@ -595,8 +595,8 @@
/* QUADSPI attributes.*/
#define STM32_HAS_QUADSPI1 TRUE
#define STM32_QUADSPI1_HANDLER Vector1AC
#define STM32_QUADSPI1_NUMBER 91
#define STM32_QUADSPI1_HANDLER Vector1B0
#define STM32_QUADSPI1_NUMBER 92
#define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
#define STM32_QUADSPI1_DMA_CHN 0x30000000