diff --git a/os/hal/ports/STM32/LLD/ADCv2/hal_adc_lld.c b/os/hal/ports/STM32/LLD/ADCv2/hal_adc_lld.c
index 02df387de..280ecc49c 100644
--- a/os/hal/ports/STM32/LLD/ADCv2/hal_adc_lld.c
+++ b/os/hal/ports/STM32/LLD/ADCv2/hal_adc_lld.c
@@ -224,6 +224,11 @@ void adc_lld_init(void) {
                   STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
 #endif
 
+#if defined(rccResetADC)
+  /* Shared reset case.*/
+  rccResetADC();
+#endif
+
   /* The shared vector is initialized on driver initialization and never
      disabled because sharing.*/
   nvicEnableVector(STM32_ADC_NUMBER, STM32_ADC_IRQ_PRIORITY);
@@ -248,7 +253,9 @@ void adc_lld_start(ADCDriver *adcp) {
                                      (void *)adcp);
       osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
       dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
-      rccResetADC1(true);
+#if defined(rccResetADC1)
+      rccResetADC1();
+#endif
       rccEnableADC1(true);
     }
 #endif /* STM32_ADC_USE_ADC1 */
@@ -261,7 +268,9 @@ void adc_lld_start(ADCDriver *adcp) {
                                      (void *)adcp);
       osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
       dmaStreamSetPeripheral(adcp->dmastp, &ADC2->DR);
-      rccResetADC2(true);
+#if defined(rccResetADC2)
+      rccResetADC2();
+#endif
       rccEnableADC2(true);
     }
 #endif /* STM32_ADC_USE_ADC2 */
@@ -274,7 +283,9 @@ void adc_lld_start(ADCDriver *adcp) {
                                      (void *)adcp);
       osalDbgAssert(adcp->dmastp != NULL, "unable to allocate stream");
       dmaStreamSetPeripheral(adcp->dmastp, &ADC3->DR);
-      rccResetADC3(true);
+#if defined(rccResetADC3)
+      rccResetADC3();
+#endif
       rccEnableADC3(true);
     }
 #endif /* STM32_ADC_USE_ADC3 */
diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h
index cc401ce05..3f7488daf 100644
--- a/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h
@@ -269,6 +269,13 @@
  * @name    ADC peripherals specific RCC operations
  * @{
  */
+/**
+ * @brief   Resets ADC peripherals.
+ *
+ * @api
+ */
+#define rccResetADC() rccResetAPB2(RCC_APB2RSTR_ADCRST)
+
 /**
  * @brief   Enables the ADC1 peripheral clock.
  *
@@ -285,13 +292,6 @@
  */
 #define rccDisableADC1() rccDisableAPB2(RCC_APB2ENR_ADC1EN)
 
-/**
- * @brief   Resets the ADC1 peripheral.
- *
- * @api
- */
-#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
-
 /**
  * @brief   Enables the ADC2 peripheral clock.
  *
@@ -308,13 +308,6 @@
  */
 #define rccDisableADC2() rccDisableAPB2(RCC_APB2ENR_ADC2EN)
 
-/**
- * @brief   Resets the ADC2 peripheral.
- *
- * @api
- */
-#define rccResetADC2() rccResetAPB2(RCC_APB2RSTR_ADC2RST)
-
 /**
  * @brief   Enables the ADC3 peripheral clock.
  *
@@ -330,13 +323,6 @@
  * @api
  */
 #define rccDisableADC3() rccDisableAPB2(RCC_APB2ENR_ADC3EN)
-
-/**
- * @brief   Resets the ADC3 peripheral.
- *
- * @api
- */
-#define rccResetADC3() rccResetAPB2(RCC_APB2RSTR_ADC3RST)
 /** @} */
 
 /**
diff --git a/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h
index a303e04f4..650567bc2 100644
--- a/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32F7xx/stm32_rcc.h
@@ -270,6 +270,13 @@
  * @name    ADC peripherals specific RCC operations
  * @{
  */
+/**
+ * @brief   Resets ADC peripherals.
+ *
+ * @api
+ */
+#define rccResetADC() rccResetAPB2(RCC_APB2RSTR_ADCRST)
+
 /**
  * @brief   Enables the ADC1 peripheral clock.
  *
@@ -286,13 +293,6 @@
  */
 #define rccDisableADC1() rccDisableAPB2(RCC_APB2ENR_ADC1EN)
 
-/**
- * @brief   Resets the ADC1 peripheral.
- *
- * @api
- */
-#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST)
-
 /**
  * @brief   Enables the ADC2 peripheral clock.
  *
@@ -309,13 +309,6 @@
  */
 #define rccDisableADC2() rccDisableAPB2(RCC_APB2ENR_ADC2EN)
 
-/**
- * @brief   Resets the ADC2 peripheral.
- *
- * @api
- */
-#define rccResetADC2() rccResetAPB2(RCC_APB2RSTR_ADC2RST)
-
 /**
  * @brief   Enables the ADC3 peripheral clock.
  *
@@ -331,13 +324,6 @@
  * @api
  */
 #define rccDisableADC3() rccDisableAPB2(RCC_APB2ENR_ADC3EN)
-
-/**
- * @brief   Resets the ADC3 peripheral.
- *
- * @api
- */
-#define rccResetADC3() rccResetAPB2(RCC_APB2RSTR_ADC3RST)
 /** @} */
 
 /**
diff --git a/testhal/STM32/STM32F4xx/DMA_STORM/main.c b/testhal/STM32/STM32F4xx/DMA_STORM/main.c
index e1aad44f1..45cd8fc12 100644
--- a/testhal/STM32/STM32F4xx/DMA_STORM/main.c
+++ b/testhal/STM32/STM32F4xx/DMA_STORM/main.c
@@ -88,12 +88,14 @@ static const ADCConversionGroup adcgrpcfg2 = {
  * Maximum speed SPI configuration (21MHz, CPHA=0, CPOL=0, MSb first).
  */
 static const SPIConfig hs_spicfg = {
-  false,
-  NULL,
-  GPIOB,
-  12,
-  0,
-  0
+  .circular         = false,
+  .slave            = false,
+  .data_cb          = NULL,
+  .error_cb         = NULL,
+  .ssport           = GPIOB,
+  .sspad            = 12,
+  .cr1              = 0,
+  .cr2              = 0
 };
 
 /*