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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7596 35acf78f-673a-0410-8e92-d51de3d6d3f4

This commit is contained in:
gdisirio 2014-12-22 11:34:55 +00:00
parent 7462417ba4
commit 2042374417
4 changed files with 43 additions and 26 deletions
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42
os/hal/boards/OLIMEX_STM32_E407_REV_D/board.c
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@ -1,5 +1,5 @@
/* /*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License"); Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License. you may not use this file except in compliance with the License.
@ -14,7 +14,6 @@
limitations under the License. limitations under the License.
*/ */
#include "ch.h"
#include "hal.h" #include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__) #if HAL_USE_PAL || defined(__DOXYGEN__)
@ -23,26 +22,43 @@
* @details Digital I/O ports static configuration as defined in @p board.h. * @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver. * This variable is used by the HAL when initializing the PAL driver.
*/ */
const PALConfig pal_default_config = const PALConfig pal_default_config = {
{ #if STM32_HAS_GPIOA
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
#endif
#if STM32_HAS_GPIOB
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
#endif
#if STM32_HAS_GPIOC
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
#endif
#if STM32_HAS_GPIOD
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
#endif
#if STM32_HAS_GPIOE
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
#endif
#if STM32_HAS_GPIOF
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
#endif
#if STM32_HAS_GPIOG
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
#endif
#if STM32_HAS_GPIOH
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
#endif
#if STM32_HAS_GPIOI
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
#endif
}; };
#endif #endif
@ -60,21 +76,21 @@ void __early_init(void) {
/** /**
* @brief SDC card detection. * @brief SDC card detection.
*/ */
bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
static bool_t last_status = FALSE; static bool last_status = false;
if (blkIsTransferring(sdcp)) if (blkIsTransferring(sdcp))
return last_status; return last_status;
return last_status = (bool_t)palReadPad(GPIOC, GPIOC_SD_D3); return last_status = (bool)palReadPad(GPIOC, GPIOC_SD_D3);
} }
/** /**
* @brief SDC card write protection detection. * @brief SDC card write protection detection.
*/ */
bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
(void)sdcp; (void)sdcp;
return FALSE; return false;
} }
#endif /* HAL_USE_SDC */ #endif /* HAL_USE_SDC */
@ -82,21 +98,21 @@ bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
/** /**
* @brief MMC_SPI card detection. * @brief MMC_SPI card detection.
*/ */
bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
(void)mmcp; (void)mmcp;
/* TODO: Fill the implementation.*/ /* TODO: Fill the implementation.*/
return TRUE; return true;
} }
/** /**
* @brief MMC_SPI card write protection detection. * @brief MMC_SPI card write protection detection.
*/ */
bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
(void)mmcp; (void)mmcp;
/* TODO: Fill the implementation.*/ /* TODO: Fill the implementation.*/
return FALSE; return false;
} }
#endif #endif

10
os/hal/boards/OLIMEX_STM32_E407_REV_D/board.h
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@ -1,5 +1,5 @@
/* /*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License"); Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License. you may not use this file except in compliance with the License.
@ -18,14 +18,14 @@
#define _BOARD_H_ #define _BOARD_H_
/* /*
* Setup for Olimex STM32-E407 board. * Setup for Olimex STM32-E407 (rev.D) board.
*/ */
/* /*
* Board identifier. * Board identifier.
*/ */
#define BOARD_OLIMEX_STM32_E407 #define BOARD_OLIMEX_STM32_E407_REV_D
#define BOARD_NAME "Olimex STM32-E407" #define BOARD_NAME "Olimex STM32-E407 (rev.D)"
/* /*
* Ethernet PHY type. * Ethernet PHY type.
@ -53,7 +53,7 @@
/* /*
* MCU type as defined in the ST header. * MCU type as defined in the ST header.
*/ */
#define STM32F40_41xxx #define STM32F407xx
/* /*
* IO pins assignments. * IO pins assignments.

4
os/hal/boards/OLIMEX_STM32_E407_REV_D/board.mk
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@ -1,5 +1,5 @@
# List of all the board related files. # List of all the board related files.
BOARDSRC = ${CHIBIOS}/boards/OLIMEX_STM32_E407/board.c BOARDSRC = ${CHIBIOS}/os/hal/boards/OLIMEX_STM32_E407_REV_D/board.c
# Required include directories # Required include directories
BOARDINC = ${CHIBIOS}/boards/OLIMEX_STM32_E407 BOARDINC = ${CHIBIOS}/os/hal/boards/OLIMEX_STM32_E407_REV_D

13
os/hal/boards/OLIMEX_STM32_E407_REV_D/cfg/board.chcfg
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@ -5,24 +5,25 @@
<configuration_settings> <configuration_settings>
<templates_path>resources/gencfg/processors/boards/stm32f4xx/templates</templates_path> <templates_path>resources/gencfg/processors/boards/stm32f4xx/templates</templates_path>
<output_path>..</output_path> <output_path>..</output_path>
<hal_version>3.0.x</hal_version>
</configuration_settings> </configuration_settings>
<board_name>Olimex STM32-E407</board_name> <board_name>Olimex STM32-E407 (rev.D)</board_name>
<board_id>OLIMEX_STM32_E407</board_id> <board_id>OLIMEX_STM32_E407_REV_D</board_id>
<board_functions> <board_functions>
<sdc_lld_is_card_inserted><![CDATA[ static bool_t last_status = FALSE; <sdc_lld_is_card_inserted><![CDATA[ static bool last_status = false;
if (blkIsTransferring(sdcp)) if (blkIsTransferring(sdcp))
return last_status; return last_status;
return last_status = (bool_t)palReadPad(GPIOC, GPIOC_SD_D3);]]></sdc_lld_is_card_inserted> return last_status = (bool)palReadPad(GPIOC, GPIOC_SD_D3);]]></sdc_lld_is_card_inserted>
<sdc_lld_is_write_protected> <sdc_lld_is_write_protected>
<![CDATA[ (void)sdcp; <![CDATA[ (void)sdcp;
return FALSE;]]></sdc_lld_is_write_protected> return false;]]></sdc_lld_is_write_protected>
</board_functions> </board_functions>
<ethernet_phy> <ethernet_phy>
<identifier>MII_LAN8710A_ID</identifier> <identifier>MII_LAN8710A_ID</identifier>
<bus_type>RMII</bus_type> <bus_type>RMII</bus_type>
</ethernet_phy> </ethernet_phy>
<subtype>STM32F40_41xxx</subtype> <subtype>STM32F407xx</subtype>
<clocks <clocks
HSEFrequency="12000000" HSEFrequency="12000000"
HSEBypass="false" HSEBypass="false"