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Fixed Bug #843 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10230 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Rocco Marco Guglielmi 2017-05-29 19:43:54 +00:00
parent ceb326112d
commit 2045fd61b9
2 changed files with 19 additions and 17 deletions
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34
os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c
View File

@ -677,10 +677,10 @@ void gpt_lld_start(GPTDriver *gptp) {
"invalid frequency"); "invalid frequency");
/* Timer configuration.*/ /* Timer configuration.*/
gptp->tim->CR1 = 0; /* Initially stopped. */ gptp->tim->CR1 = 0; /* Initially stopped. */
gptp->tim->CR2 = gptp->config->cr2; gptp->tim->CR2 = gptp->config->cr2;
gptp->tim->PSC = psc; /* Prescaler value. */ gptp->tim->PSC = psc; /* Prescaler value. */
gptp->tim->SR = 0; /* Clear pending IRQs. */ gptp->tim->SR = 0; /* Clear pending IRQs. */
gptp->tim->DIER = gptp->config->dier & /* DMA-related DIER bits. */ gptp->tim->DIER = gptp->config->dier & /* DMA-related DIER bits. */
~STM32_TIM_DIER_IRQ_MASK; ~STM32_TIM_DIER_IRQ_MASK;
} }
@ -695,9 +695,9 @@ void gpt_lld_start(GPTDriver *gptp) {
void gpt_lld_stop(GPTDriver *gptp) { void gpt_lld_stop(GPTDriver *gptp) {
if (gptp->state == GPT_READY) { if (gptp->state == GPT_READY) {
gptp->tim->CR1 = 0; /* Timer disabled. */ gptp->tim->CR1 = 0; /* Timer disabled. */
gptp->tim->DIER = 0; /* All IRQs disabled. */ gptp->tim->DIER = 0; /* All IRQs disabled. */
gptp->tim->SR = 0; /* Clear pending IRQs. */ gptp->tim->SR = 0; /* Clear pending IRQs. */
#if STM32_GPT_USE_TIM1 #if STM32_GPT_USE_TIM1
if (&GPTD1 == gptp) { if (&GPTD1 == gptp) {
@ -819,14 +819,14 @@ void gpt_lld_stop(GPTDriver *gptp) {
*/ */
void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
gptp->tim->ARR = (uint32_t)(interval - 1); /* Time constant. */ gptp->tim->ARR = (uint32_t)(interval); /* Time constant. */
gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */ gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */
gptp->tim->CNT = 0; /* Reset counter. */ gptp->tim->CNT = 0; /* Reset counter. */
/* NOTE: After generating the UG event it takes several clock cycles before /* NOTE: After generating the UG event it takes several clock cycles before
SR bit 0 goes to 1. This is why the clearing of CNT has been inserted SR bit 0 goes to 1. This is why the clearing of CNT has been inserted
before the clearing of SR, to give it some time.*/ before the clearing of SR, to give it some time.*/
gptp->tim->SR = 0; /* Clear pending IRQs. */ gptp->tim->SR = 0; /* Clear pending IRQs. */
if (NULL != gptp->config->callback) if (NULL != gptp->config->callback)
gptp->tim->DIER |= STM32_TIM_DIER_UIE; /* Update Event IRQ enabled.*/ gptp->tim->DIER |= STM32_TIM_DIER_UIE; /* Update Event IRQ enabled.*/
gptp->tim->CR1 = STM32_TIM_CR1_ARPE | STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN; gptp->tim->CR1 = STM32_TIM_CR1_ARPE | STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN;
@ -841,8 +841,8 @@ void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) {
*/ */
void gpt_lld_stop_timer(GPTDriver *gptp) { void gpt_lld_stop_timer(GPTDriver *gptp) {
gptp->tim->CR1 = 0; /* Initially stopped. */ gptp->tim->CR1 = 0; /* Initially stopped. */
gptp->tim->SR = 0; /* Clear pending IRQs. */ gptp->tim->SR = 0; /* Clear pending IRQs. */
/* All interrupts disabled.*/ /* All interrupts disabled.*/
gptp->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK; gptp->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK;
@ -861,13 +861,13 @@ void gpt_lld_stop_timer(GPTDriver *gptp) {
*/ */
void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) {
gptp->tim->ARR = (uint32_t)(interval - 1); /* Time constant. */ gptp->tim->ARR = (uint32_t)(interval); /* Time constant. */
gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */ gptp->tim->EGR = STM32_TIM_EGR_UG; /* Update event. */
gptp->tim->SR = 0; /* Clear pending IRQs. */ gptp->tim->SR = 0; /* Clear pending IRQs. */
gptp->tim->CR1 = STM32_TIM_CR1_OPM | STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN; gptp->tim->CR1 = STM32_TIM_CR1_OPM | STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN;
while (!(gptp->tim->SR & STM32_TIM_SR_UIF)) while (!(gptp->tim->SR & STM32_TIM_SR_UIF))
; ;
gptp->tim->SR = 0; /* Clear pending IRQs. */ gptp->tim->SR = 0; /* Clear pending IRQs. */
} }
/** /**

2
readme.txt
View File

@ -161,6 +161,8 @@
- RT: Merged RT4. - RT: Merged RT4.
- NIL: Merged NIL2. - NIL: Merged NIL2.
- NIL: Added STM32F7 demo. - NIL: Added STM32F7 demo.
- HAL: Fixed wrong ARR initialization in STM32 GPT driver (bug #843)(backported
to 16.1.9).
- HAL: Fixed wrong configuration in STM32L4xx GPT-ADC demo (bug #842)(backported - HAL: Fixed wrong configuration in STM32L4xx GPT-ADC demo (bug #842)(backported
to 16.1.9). to 16.1.9).
- HAL: Fixed invalid DMA channels for STM32F334 ADC2 (bug #840)(backported - HAL: Fixed invalid DMA channels for STM32F334 ADC2 (bug #840)(backported