diff --git a/os/hal/include/hal_wspi.h b/os/hal/include/hal_wspi.h index 887aa0a21..d0a99c1c6 100644 --- a/os/hal/include/hal_wspi.h +++ b/os/hal/include/hal_wspi.h @@ -71,9 +71,10 @@ typedef enum { WSPI_UNINIT = 0, /**< Not initialized. */ WSPI_STOP = 1, /**< Stopped. */ WSPI_READY = 2, /**< Ready. */ - WSPI_ACTIVE = 3, /**< Exchanging data. */ - WSPI_COMPLETE = 4, /**< Asynchronous operation complete. */ - WSPI_MEMMAP = 5 /**< In memory mapped mode. */ + WSPI_SEND = 3, /**< Sending data. */ + WSPI_RECEIVE = 4, /**< Receiving data. */ + WSPI_COMPLETE = 5, /**< Asynchronous operation complete. */ + WSPI_MEMMAP = 6 /**< In memory mapped mode. */ } wspistate_t; /** @@ -274,7 +275,7 @@ struct hal_wspi_driver { osalDbgAssert(((cmdp)->cfg & WSPI_CFG_DATA_MODE_MASK) == \ WSPI_CFG_DATA_MODE_NONE, \ "data mode specified"); \ - (wspip)->state = WSPI_ACTIVE; \ + (wspip)->state = WSPI_SEND; \ wspi_lld_command(wspip, cmdp); \ } @@ -294,7 +295,7 @@ struct hal_wspi_driver { osalDbgAssert(((cmdp)->cfg & WSPI_CFG_DATA_MODE_MASK) != \ WSPI_CFG_DATA_MODE_NONE, \ "data mode required"); \ - (wspip)->state = WSPI_ACTIVE; \ + (wspip)->state = WSPI_SEND; \ wspi_lld_send(wspip, cmdp, n, txbuf); \ } @@ -314,7 +315,7 @@ struct hal_wspi_driver { osalDbgAssert(((cmdp)->cfg & WSPI_CFG_DATA_MODE_MASK) != \ WSPI_CFG_DATA_MODE_NONE, \ "data mode required"); \ - (wspip)->state = WSPI_ACTIVE; \ + (wspip)->state = WSPI_RECEIVE; \ wspi_lld_receive(wspip, cmdp, n, rxbuf); \ } diff --git a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_wspi_lld.c b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_wspi_lld.c index fb8c790bb..678339a02 100644 --- a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_wspi_lld.c +++ b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_wspi_lld.c @@ -94,7 +94,14 @@ static void wspi_lld_serve_interrupt(WSPIDriver *wspip) { operation. Race condition hidden here.*/ while (dmaStreamGetTransactionSize(wspip->dma) > 0U) ; - dmaStreamDisable(wspip->dma); + + /* Handling of errata: Extra data written in the FIFO at the end of a + read transfer.*/ + if (wspip->state == WSPI_RECEIVE) { + while ((wspip->qspi->SR & QUADSPI_SR_BUSY) != 0U) { + (void) wspip->qspi->DR; + } + } } /*===========================================================================*/ diff --git a/readme.txt b/readme.txt index 34e4ee846..b78c1749d 100644 --- a/readme.txt +++ b/readme.txt @@ -100,6 +100,8 @@ MEMS Accelerometers. - NEW: Safer messages mechanism for sandboxes (to be backported to 20.3.1). - NEW: Added latency measurement test application. +- FIX: Fixed STM32 QSPI errata workaround (bug #1116) + (backported to 20.3.2). - FIX: Fixed wrong condition in STM32 BDMAv1 driver (bug #1115) (backported to 20.3.2). - FIX: Fixed HSI48 not getting enabled on STM32H7 (bug #1114) diff --git a/testhal/STM32/multi/WSPI-MFS/.cproject b/testhal/STM32/multi/WSPI-MFS/.cproject index ab58f5e52..09f2531d6 100644 --- a/testhal/STM32/multi/WSPI-MFS/.cproject +++ b/testhal/STM32/multi/WSPI-MFS/.cproject @@ -179,4 +179,5 @@ +