Reintegrate sama5d2_dev branch
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10878 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
isiora
parent
37f8ea73a8
commit
211dcdd26d
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@ -0,0 +1,135 @@
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/******************************************************************************
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* @file ARMCA5.h
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* @brief CMSIS Cortex-A5 Core Peripheral Access Layer Header File
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* @version V1.00
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* @data 16 Mar 2017
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*
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* @note
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*
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******************************************************************************/
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/*
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* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __ARMCA5_H__
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#define __ARMCA5_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ------------------------- Interrupt Number Definition ------------------------ */
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typedef enum IRQn
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{
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/****** SGI Interrupts Numbers ****************************************/
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SGI0_IRQn = 0,
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SGI1_IRQn = 1,
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SGI2_IRQn = 2,
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SGI3_IRQn = 3,
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SGI4_IRQn = 4,
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SGI5_IRQn = 5,
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SGI6_IRQn = 6,
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SGI7_IRQn = 7,
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SGI8_IRQn = 8,
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SGI9_IRQn = 9,
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SGI10_IRQn = 10,
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SGI11_IRQn = 11,
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SGI12_IRQn = 12,
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SGI13_IRQn = 13,
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SGI14_IRQn = 14,
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SGI15_IRQn = 15,
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/****** Cortex-A5 Processor Exceptions Numbers ****************************************/
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GlobalTimer_IRQn = 27, /*!< Global Timer Interrupt */
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PrivTimer_IRQn = 29, /*!< Private Timer Interrupt */
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PrivWatchdog_IRQn = 30, /*!< Private Watchdog Interrupt */
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/****** Platform Exceptions Numbers ***************************************************/
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Watchdog_IRQn = 32, /*!< SP805 Interrupt */
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Timer0_IRQn = 34, /*!< SP804 Interrupt */
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Timer1_IRQn = 35, /*!< SP804 Interrupt */
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RTClock_IRQn = 36, /*!< PL031 Interrupt */
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UART0_IRQn = 37, /*!< PL011 Interrupt */
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UART1_IRQn = 38, /*!< PL011 Interrupt */
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UART2_IRQn = 39, /*!< PL011 Interrupt */
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UART3_IRQn = 40, /*!< PL011 Interrupt */
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MCI0_IRQn = 41, /*!< PL180 Interrupt (1st) */
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MCI1_IRQn = 42, /*!< PL180 Interrupt (2nd) */
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AACI_IRQn = 43, /*!< PL041 Interrupt */
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Keyboard_IRQn = 44, /*!< PL050 Interrupt */
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Mouse_IRQn = 45, /*!< PL050 Interrupt */
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CLCD_IRQn = 46, /*!< PL111 Interrupt */
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Ethernet_IRQn = 47, /*!< SMSC_91C111 Interrupt */
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VFS2_IRQn = 73, /*!< VFS2 Interrupt */
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} IRQn_Type;
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/******************************************************************************/
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/* Peripheral memory map */
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/******************************************************************************/
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/* Peripheral and RAM base address */
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#define VE_A5_MP_FLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */
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#define VE_A5_MP_FLASH_BASE1 (0x08000000UL) /*!< (FLASH1 ) Base Address */
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#define VE_A5_MP_PERIPH_BASE (0x18000000UL) /*!< (Peripheral) Base Address */
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#define VE_A5_MP_SRAM_BASE (0x2E000000UL) /*!< (SRAM ) Base Address */
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#define VE_A5_MP_DRAM_BASE (0x80000000UL) /*!< (DRAM ) Base Address */
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#define VE_A5_MP_VRAM_BASE (0x18000000UL) /*!< (VRAM ) Base Address */
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#define VE_A5_MP_ETHERNET_BASE (0x02000000UL + VE_A5_MP_PERIPH_BASE) /*!< (ETHERNET ) Base Address */
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#define VE_A5_MP_USB_BASE (0x03000000UL + VE_A5_MP_PERIPH_BASE) /*!< (USB ) Base Address */
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#define VE_A5_MP_DAP_BASE (0x1C000000UL) /*!< (DAP ) Base Address */
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#define VE_A5_MP_SYSTEM_REG_BASE (0x00010000UL + 0x1C000000UL) /*!< (SYSTEM REG) Base Address */
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#define VE_A5_MP_SERIAL_BASE (0x00030000UL + 0x1C000000UL) /*!< (SERIAL ) Base Address */
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#define VE_A5_MP_AACI_BASE (0x00040000UL + 0x1C000000UL) /*!< (AACI ) Base Address */
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#define VE_A5_MP_MMCI_BASE (0x00050000UL + 0x1C000000UL) /*!< (MMCI ) Base Address */
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#define VE_A5_MP_KMI0_BASE (0x00060000UL + 0x1C000000UL) /*!< (KMI0 ) Base Address */
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#define VE_A5_MP_UART_BASE (0x00090000UL + 0x1C000000UL) /*!< (UART ) Base Address */
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#define VE_A5_MP_WDT_BASE (0x000F0000UL + 0x1C000000UL) /*!< (WDT ) Base Address */
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#define VE_A5_MP_TIMER_BASE (0x00110000UL + 0x1C000000UL) /*!< (TIMER ) Base Address */
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#define VE_A5_MP_DVI_BASE (0x00160000UL + 0x1C000000UL) /*!< (DVI ) Base Address */
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#define VE_A5_MP_RTC_BASE (0x00170000UL + 0x1C000000UL) /*!< (RTC ) Base Address */
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#define VE_A5_MP_UART4_BASE (0x001B0000UL + 0x1C000000UL) /*!< (UART4 ) Base Address */
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#define VE_A5_MP_CLCD_BASE (0x001F0000UL + 0x1C000000UL) /*!< (CLCD ) Base Address */
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#define VE_A5_MP_GIC_DISTRIBUTOR_BASE (0x00001000UL + 0x2C000000UL) /*!< (GIC DIST ) Base Address */
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#define VE_A5_MP_GIC_INTERFACE_BASE (0x00000100UL + 0x2C000000UL) /*!< (GIC CPU IF) Base Address */
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#define VE_A5_MP_PRIVATE_TIMER (0x00000600UL + 0x2C000000UL) /*!< (PTIM ) Base Address */
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#define GIC_DISTRIBUTOR_BASE VE_A5_MP_GIC_DISTRIBUTOR_BASE
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#define GIC_INTERFACE_BASE VE_A5_MP_GIC_INTERFACE_BASE
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#define TIMER_BASE VE_A5_MP_PRIVATE_TIMER
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//The VE-A5 model implements L1 cache as architecturally defined, but does not implement L2 cache.
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//Do not enable the L2 cache if you are running RTX on a VE-A5 model as it may cause a data abort.
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#define VE_A5_MP_PL310_BASE (0x2C0F0000UL) /*!< (L2C-310 ) Base Address */
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#define L2C_310_BASE VE_A5_MP_PL310_BASE
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/* -------- Configuration of the Cortex-A5 Processor and Core Peripherals ------- */
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#define __CA_REV 0x0000U /* Core revision r0p0 */
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#define __CORTEX_A 5U /* Cortex-A5 Core */
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#define __FPU_PRESENT 1U /* FPU present */
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#define __GIC_PRESENT 1U /* GIC present */
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#define __TIM_PRESENT 1U /* TIM present */
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#define __L2C_PRESENT 0U /* L2C present */
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#include "core_ca.h"
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#include <system_ARMCA5.h>
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#ifdef __cplusplus
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}
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#endif
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#endif // __ARMCA5_H__
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@ -558,7 +558,9 @@ __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
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/** \brief Get CBAR
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\return Configuration Base Address register value
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*/
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__STATIC_INLINE uint32_t __get_CBAR() {
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/* CHIBIOS FIX */
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//__STATIC_INLINE uint32_t __get_CBAR() {
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__STATIC_INLINE uint32_t __get_CBAR(void) {
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uint32_t result;
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__ASM volatile("MRC p15, 4, %0, c15, c0, 0" : "=r"(result));
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return result;
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@ -570,7 +572,9 @@ __STATIC_INLINE uint32_t __get_CBAR() {
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\return Translation Table Base Register 0 value
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*/
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__STATIC_INLINE uint32_t __get_TTBR0() {
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/* CHIBIOS FIX */
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//__STATIC_INLINE uint32_t __get_TTBR0() {
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__STATIC_INLINE uint32_t __get_TTBR0(void) {
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uint32_t result;
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__ASM volatile("MRC p15, 0, %0, c2, c0, 0" : "=r"(result));
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return result;
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@ -592,7 +596,9 @@ __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
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\return Domain Access Control Register value
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*/
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__STATIC_INLINE uint32_t __get_DACR() {
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/* CHIBIOS FIX */
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//__STATIC_INLINE uint32_t __get_DACR() {
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__STATIC_INLINE uint32_t __get_DACR(void) {
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uint32_t result;
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__ASM volatile("MRC p15, 0, %0, c3, c0, 0" : "=r"(result));
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return result;
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@ -622,7 +628,9 @@ __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
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/** \brief Get SCTLR
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\return System Control Register value
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*/
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__STATIC_INLINE uint32_t __get_SCTLR() {
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/* CHIBIOS FIX */
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//__STATIC_INLINE uint32_t __get_SCTLR() {
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__STATIC_INLINE uint32_t __get_SCTLR(void) {
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uint32_t result;
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__ASM volatile("MRC p15, 0, %0, c1, c0, 0" : "=r"(result));
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return result;
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@ -709,7 +717,9 @@ __STATIC_INLINE void __set_CNTP_TVAL(uint32_t value) {
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\return CNTP_TVAL Register value
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*/
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__STATIC_INLINE uint32_t __get_CNTP_TVAL() {
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/* CHIBIOS FIX */
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//__STATIC_INLINE uint32_t __get_CNTP_TVAL() {
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__STATIC_INLINE uint32_t __get_CNTP_TVAL(void) {
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uint32_t result;
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__ASM volatile("MRC p15, 0, %0, c14, c2, 0" : "=r"(result));
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return result;
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@ -728,7 +738,9 @@ __STATIC_INLINE void __set_CNTP_CTL(uint32_t value) {
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/** \brief Get CNTP_CTL register
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\return CNTP_CTL Register value
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*/
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__STATIC_INLINE uint32_t __get_CNTP_CTL() {
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/* CHIBIOS FIX */
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//__STATIC_INLINE uint32_t __get_CNTP_CTL() {
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__STATIC_INLINE uint32_t __get_CNTP_CTL(void) {
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uint32_t result;
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__ASM volatile("MRC p15, 0, %0, c14, c2, 1" : "=r"(result));
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return result;
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@ -792,7 +804,9 @@ __STATIC_INLINE void __set_CCSIDR(uint32_t value) {
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/** \brief Get CCSIDR
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\return CCSIDR Register value
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*/
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__STATIC_INLINE uint32_t __get_CCSIDR() {
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/* CHIBIOS FIX */
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//__STATIC_INLINE uint32_t __get_CCSIDR() {
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__STATIC_INLINE uint32_t __get_CCSIDR(void) {
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uint32_t result;
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__ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result));
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return result;
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@ -801,7 +815,9 @@ __STATIC_INLINE uint32_t __get_CCSIDR() {
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/** \brief Get CLIDR
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\return CLIDR Register value
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*/
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__STATIC_INLINE uint32_t __get_CLIDR() {
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/* CHIBIOS FIX */
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//__STATIC_INLINE uint32_t __get_CLIDR() {
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__STATIC_INLINE uint32_t __get_CLIDR(void) {
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uint32_t result;
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__ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result));
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return result;
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@ -1495,7 +1495,9 @@ __STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) {
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/** \brief Get the load value from timers LOAD register.
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* \return Timer_Type::LOAD
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*/
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__STATIC_INLINE uint32_t PTIM_GetLoadValue() {
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/* CHIBIOS FIX */
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//__STATIC_INLINE uint32_t PTIM_GetLoadValue() {
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__STATIC_INLINE uint32_t PTIM_GetLoadValue(void) {
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return(PTIM->LOAD);
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}
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@ -1508,7 +1510,9 @@ __STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value) {
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/** \brief Get current counter value from timers COUNTER register.
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* \result Timer_Type::COUNTER
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*/
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__STATIC_INLINE uint32_t PTIM_GetCurrentValue() {
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/* CHIBIOS FIX */
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//__STATIC_INLINE uint32_t PTIM_GetCurrentValue() {
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__STATIC_INLINE uint32_t PTIM_GetCurrentValue(void) {
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return(PTIM->COUNTER);
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}
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@ -0,0 +1,65 @@
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/******************************************************************************
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* @file system_ARMCA5.h
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* @brief CMSIS Device System Header File for ARM Cortex-A Device Series
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* @version V1.00
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* @date 16 Mar 2017
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*
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* @note
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*
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******************************************************************************/
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/*
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* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __SYSTEM_ARMCA5_H
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#define __SYSTEM_ARMCA5_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
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/**
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\brief Setup the microcontroller system.
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Initialize the System and update the SystemCoreClock variable.
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*/
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extern void SystemInit (void);
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/**
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\brief Update SystemCoreClock variable.
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Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
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*/
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extern void SystemCoreClockUpdate (void);
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/**
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\brief Create Translation Table.
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Creates Memory Management Unit Translation Table.
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*/
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extern void MMU_CreateTranslationTable(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __SYSTEM_ARMCA5_H */
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@ -5,6 +5,7 @@ STARTUPASM = $(CHIBIOS)/os/common/startup/ARM/devices/SAMA5D2/boot.S \
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$(CHIBIOS)/os/common/startup/ARM/compilers/GCC/vectors.S \
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$(CHIBIOS)/os/common/startup/ARM/compilers/GCC/crt0.S
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STARTUPINC = ${CHIBIOS}/os/common/startup/ARM/devices/SAMA5D2
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STARTUPINC = ${CHIBIOS}/os/common/startup/ARM/devices/SAMA5D2 \
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$(CHIBIOS)/os/common/ext/ARM/CMSIS/Core_A/Include
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STARTUPLD = ${CHIBIOS}/os/common/startup/ARM/compilers/GCC/ld
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@ -33,6 +33,11 @@
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*/
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#define ARM_CORE ARM_CORE_CORTEX_A5
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/**
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* @brief Cortex core model.
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*/
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#define CORTEX_MODEL 5
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/**
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* @brief Thumb-capable.
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*/
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@ -43,18 +48,44 @@
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*/
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#define ARM_SUPPORTS_THUMB2 1
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/**
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* @brief VFPv4-D16 FPU.
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*/
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#define TARGET_FEATURE_EXTENSION_REGISTER_COUNT 16
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/**
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* @brief Implementation of the wait-for-interrupt state enter.
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*/
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#define ARM_WFI_IMPL asm volatile ("wfi")
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#if !defined(_FROM_ASM_) || defined(__DOXYGEN__)
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/* If the device type is not externally defined, for example from the Makefile,
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then a file named board.h is included. This file must contain a device
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definition compatible with the vendor include file.*/
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#if !defined (SAMA5D21) && !defined (SAMA5D22) && !defined (SAMA5D23) && \
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!defined (SAMA5D24) && !defined (SAMA5D25) && !defined (SAMA5D26) && \
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!defined (SAMA5D27) && !defined (SAMA5D28)
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#include "board.h"
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#endif
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/* Including the device CMSIS header. Note, we are not using the definitions
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from this header because we need this file to be usable also from
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assembler source files. We verify that the info matches instead.*/
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#include "sama5d2x.h"
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/*lint -save -e9029 [10.4] Signedness comes from external files, it is
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unpredictable but gives no problems.*/
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#if CORTEX_MODEL != __CORTEX_A
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#error "CMSIS __CORTEX_A mismatch"
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#endif
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/**
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* @brief Address of the IRQ vector register in the interrupt controller.
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*/
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#define ARM_IRQ_VECTOR_REG 0xF803C010U
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#else
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#define ARM_IRQ_VECTOR_REG 0xF803C010
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#endif
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#endif /* ARMPARAMS_H */
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|
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@ -23,9 +23,11 @@
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*/
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#if !defined(__DOXYGEN__)
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.set AIC_REDIR_KEY, 0x5B6C0E26 << 1
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.set SFR_SN1, 0xF8030050
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.set SFR_AICREDIR, 0xF8030054
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.set AIC_REDIR_KEY, 0x5B6C0E26 << 1
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.set SFR_SN1, 0xF8030050
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.set SFR_AICREDIR, 0xF8030054
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.set SFR_L2CC_HRAMC, 0xF8030058
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.set L2CC_CR, 0x00A00100
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.section .boot
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.code 32
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|
@ -35,22 +37,45 @@
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*/
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.global Boot_Handler
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Boot_Handler:
|
||||
/*
|
||||
* Set VBAR to system vectors table
|
||||
*/
|
||||
ldr r0, =_start
|
||||
mcr p15, 0, r0, c12, c0, 0
|
||||
/*
|
||||
* Set VBAR to system vectors table
|
||||
*/
|
||||
ldr r0, =_start
|
||||
mcr p15, 0, r0, c12, c0, 0
|
||||
/*
|
||||
* Do not redirect secure interrupts to AIC
|
||||
*/
|
||||
ldr r0, =AIC_REDIR_KEY
|
||||
ldr r0, =AIC_REDIR_KEY
|
||||
ldr r1, =SFR_SN1
|
||||
ldr r1, [r1]
|
||||
eor r0, r0, r1
|
||||
bic r0, r0, #0x1
|
||||
ldr r1, =SFR_AICREDIR
|
||||
str r0, [r1]
|
||||
b Reset_Handler
|
||||
ldr r1, [r1]
|
||||
eor r0, r0, r1
|
||||
bic r0, r0, #0x1
|
||||
ldr r1, =SFR_AICREDIR
|
||||
str r0, [r1]
|
||||
/*
|
||||
* Reset SCTLR Settings
|
||||
*/
|
||||
mrc p15, 0, r0, c1, c0, 0 // Read CP15 System Control register
|
||||
bic r0, r0, #(0x1 << 12) // Clear I bit 12 to disable I Cache
|
||||
bic r0, r0, #(0x1 << 2) // Clear C bit 2 to disable D Cache
|
||||
bic r0, r0, #0x1 // Clear M bit 0 to disable MMU
|
||||
bic r0, r0, #(0x1 << 11) // Clear Z bit 11 to disable branch prediction
|
||||
bic r0, r0, #(0x1 << 13) // Clear V bit 13 to disable hivecs
|
||||
mcr p15, 0, r0, c1, c0, 0 // Write value back to CP15 System Control register
|
||||
isb
|
||||
/*
|
||||
* Turn off L2Cache
|
||||
*/
|
||||
bic r0, r0, #0x1
|
||||
ldr r1, =L2CC_CR
|
||||
str r0, [r1]
|
||||
/*
|
||||
* Configure the L2 cache to be used as an internal SRAM
|
||||
*/
|
||||
bic r0, r0, #0x1
|
||||
ldr r1, =SFR_L2CC_HRAMC
|
||||
str r0, [r1]
|
||||
b Reset_Handler
|
||||
#endif /* !defined(__DOXYGEN__) */
|
||||
|
||||
/** @} */
|
||||
|
|
|
|||
|
|
@ -32,16 +32,7 @@
|
|||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /**< Defines 'read-only' permissions */
|
||||
#else
|
||||
#define __I volatile const /**< Defines 'read-only' permissions */
|
||||
#endif
|
||||
|
||||
#define __O volatile /**< Defines 'write-only' permissions */
|
||||
#define __IO volatile /**< Defines 'read/write' permissions */
|
||||
|
||||
#include "ARMCA5.h"
|
||||
/**
|
||||
* @brief SAMA5D2 Family
|
||||
*/
|
||||
|
|
@ -70,6 +61,7 @@
|
|||
#else
|
||||
#error "Please select first the target SAMA5D2x device used in your application (in sama5d2x.h file)"
|
||||
#endif
|
||||
|
||||
/**@} */
|
||||
|
||||
/**
|
||||
|
|
@ -317,7 +309,56 @@
|
|||
#define ID_RXLP_MSK (1 << (ID_RXLP & 0x1F))
|
||||
#define ID_CHIPID_MSK (1 << (ID_CHIPID & 0x1F))
|
||||
|
||||
/**@} */
|
||||
/* MASTER MATRIX ID DEFINITION FOR SAMA5D2x */
|
||||
|
||||
#define H64MX_MASTER_BRIDGE_FROM_AXI 0
|
||||
#define H64MX_MASTER_XDMAC0_0 1
|
||||
#define H64MX_MASTER_XDMAC0_1 2
|
||||
#define H64MX_MASTER_XDMAC1_0 3
|
||||
#define H64MX_MASTER_XDMAC1_1 4
|
||||
#define H64MX_MASTER_LCDC_DMA_0 5
|
||||
#define H64MX_MASTER_LCDC_DMA_1 6
|
||||
#define H64MX_MASTER_SDMMC0 7
|
||||
#define H64MX_MASTER_SDMMC1 8
|
||||
#define H64MX_MASTER_ISC_DMA 9
|
||||
#define H64MX_MASTER_AESB 10
|
||||
#define H64MX_MASTER_BRIDGE_H64MX 11
|
||||
|
||||
#define H32MX_MASTER_BRIDGE_H32MX 0
|
||||
#define H32MX_MASTER_ICM 1
|
||||
#define H32MX_MASTER_UHPHS_EHCI_DMA 2
|
||||
#define H32MX_MASTER_UHPHS_OHCI_DMA 3
|
||||
#define H32MX_MASTER_UDPHS_DMA 4
|
||||
#define H32MX_MASTER_GMAC_DMA 5
|
||||
#define H32MX_MASTER_CAN0_DMA 6
|
||||
#define H32MX_MASTER_CAN1_DMA 7
|
||||
|
||||
/* SLAVE MATRIX ID DEFINITIONS FOR SAMA5D2x */
|
||||
|
||||
#define H64MX_SLAVE_BRIDGE_H32MX 0
|
||||
#define H64MX_SLAVE_APB 1
|
||||
#define H64MX_SLAVE_SDMMC 1
|
||||
#define H64MX_SLAVE_DDR_PORT0 2
|
||||
#define H64MX_SLAVE_DDR_PORT1 3
|
||||
#define H64MX_SLAVE_DDR_PORT2 4
|
||||
#define H64MX_SLAVE_DDR_PORT3 5
|
||||
#define H64MX_SLAVE_DDR_PORT4 6
|
||||
#define H64MX_SLAVE_DDR_PORT5 7
|
||||
#define H64MX_SLAVE_DDR_PORT6 8
|
||||
#define H64MX_SLAVE_DDR_PORT7 9
|
||||
#define H64MX_SLAVE_SRAM 10
|
||||
#define H64MX_SLAVE_L2C_SRAM 11
|
||||
#define H64MX_SLAVE_QSPI0 12
|
||||
#define H64MX_SLAVE_QSPI1 13
|
||||
#define H64MX_SLAVE_AESB 14
|
||||
|
||||
#define H32MX_SLAVE_BRIDGE_H64MX 0
|
||||
#define H32MX_SLAVE_APB0 1
|
||||
#define H32MX_SLAVE_APB1 2
|
||||
#define H32MX_SLAVE_EBI 3
|
||||
#define H32MX_SLAVE_NFC_CMD 3
|
||||
#define H32MX_SLAVE_NFC_SRAM 4
|
||||
#define H32MX_SLAVE_USB 5
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue