git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5188 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio
parent
5e0b152e0f
commit
216a856f99
|
|
@ -5,14 +5,14 @@ Settings: SYSCLK=64
|
||||||
|
|
||||||
*** ChibiOS/RT test suite
|
*** ChibiOS/RT test suite
|
||||||
***
|
***
|
||||||
*** Kernel: 2.5.1unstable
|
*** Kernel: 2.5.2unstable
|
||||||
*** Compiled: Nov 21 2012 - 11:53:56
|
*** Compiled: Feb 15 2013 - 12:24:06
|
||||||
*** Compiler: GCC 4.5.2 (build: 2011.11) build on 2011-11-30 Tool Version v1.4
|
*** Compiler: GCC 4.6.3 build on 2013-01-07
|
||||||
*** Architecture: Power Architecture
|
*** Architecture: Power Architecture
|
||||||
*** Core Variant: e200z0
|
*** Core Variant: e200z0
|
||||||
*** Port Info: VLE mode
|
*** Port Info: VLE mode
|
||||||
*** Platform: SPC560B/Cxx Car Body and Convenience
|
*** Platform: SPC560B/Cxx Car Body and Convenience
|
||||||
*** Test Board: Generic SPC560B/C
|
*** Test Board: Generic SPC560B/Cxx
|
||||||
|
|
||||||
----------------------------------------------------------------------------
|
----------------------------------------------------------------------------
|
||||||
--- Test Case 1.1 (Threads, enqueuing test #1)
|
--- Test Case 1.1 (Threads, enqueuing test #1)
|
||||||
|
|
@ -100,51 +100,51 @@ Settings: SYSCLK=64
|
||||||
--- Result: SUCCESS
|
--- Result: SUCCESS
|
||||||
----------------------------------------------------------------------------
|
----------------------------------------------------------------------------
|
||||||
--- Test Case 11.1 (Benchmark, messages #1)
|
--- Test Case 11.1 (Benchmark, messages #1)
|
||||||
--- Score : 199440 msgs/S, 398880 ctxswc/S
|
--- Score : 200707 msgs/S, 401414 ctxswc/S
|
||||||
--- Result: SUCCESS
|
--- Result: SUCCESS
|
||||||
----------------------------------------------------------------------------
|
----------------------------------------------------------------------------
|
||||||
--- Test Case 11.2 (Benchmark, messages #2)
|
--- Test Case 11.2 (Benchmark, messages #2)
|
||||||
--- Score : 167943 msgs/S, 335886 ctxswc/S
|
--- Score : 167517 msgs/S, 335034 ctxswc/S
|
||||||
--- Result: SUCCESS
|
--- Result: SUCCESS
|
||||||
----------------------------------------------------------------------------
|
----------------------------------------------------------------------------
|
||||||
--- Test Case 11.3 (Benchmark, messages #3)
|
--- Test Case 11.3 (Benchmark, messages #3)
|
||||||
--- Score : 167942 msgs/S, 335884 ctxswc/S
|
--- Score : 167515 msgs/S, 335030 ctxswc/S
|
||||||
--- Result: SUCCESS
|
--- Result: SUCCESS
|
||||||
----------------------------------------------------------------------------
|
----------------------------------------------------------------------------
|
||||||
--- Test Case 11.4 (Benchmark, context switch)
|
--- Test Case 11.4 (Benchmark, context switch)
|
||||||
--- Score : 582232 ctxswc/S
|
--- Score : 590272 ctxswc/S
|
||||||
--- Result: SUCCESS
|
--- Result: SUCCESS
|
||||||
----------------------------------------------------------------------------
|
----------------------------------------------------------------------------
|
||||||
--- Test Case 11.5 (Benchmark, threads, full cycle)
|
--- Test Case 11.5 (Benchmark, threads, full cycle)
|
||||||
--- Score : 133234 threads/S
|
--- Score : 132964 threads/S
|
||||||
--- Result: SUCCESS
|
--- Result: SUCCESS
|
||||||
----------------------------------------------------------------------------
|
----------------------------------------------------------------------------
|
||||||
--- Test Case 11.6 (Benchmark, threads, create only)
|
--- Test Case 11.6 (Benchmark, threads, create only)
|
||||||
--- Score : 188820 threads/S
|
--- Score : 189949 threads/S
|
||||||
--- Result: SUCCESS
|
--- Result: SUCCESS
|
||||||
----------------------------------------------------------------------------
|
----------------------------------------------------------------------------
|
||||||
--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads)
|
--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads)
|
||||||
--- Score : 51926 reschedules/S, 311556 ctxswc/S
|
--- Score : 51973 reschedules/S, 311838 ctxswc/S
|
||||||
--- Result: SUCCESS
|
--- Result: SUCCESS
|
||||||
----------------------------------------------------------------------------
|
----------------------------------------------------------------------------
|
||||||
--- Test Case 11.8 (Benchmark, round robin context switching)
|
--- Test Case 11.8 (Benchmark, round robin context switching)
|
||||||
--- Score : 407140 ctxswc/S
|
--- Score : 392160 ctxswc/S
|
||||||
--- Result: SUCCESS
|
--- Result: SUCCESS
|
||||||
----------------------------------------------------------------------------
|
----------------------------------------------------------------------------
|
||||||
--- Test Case 11.9 (Benchmark, I/O Queues throughput)
|
--- Test Case 11.9 (Benchmark, I/O Queues throughput)
|
||||||
--- Score : 593368 bytes/S
|
--- Score : 619272 bytes/S
|
||||||
--- Result: SUCCESS
|
--- Result: SUCCESS
|
||||||
----------------------------------------------------------------------------
|
----------------------------------------------------------------------------
|
||||||
--- Test Case 11.10 (Benchmark, virtual timers set/reset)
|
--- Test Case 11.10 (Benchmark, virtual timers set/reset)
|
||||||
--- Score : 818254 timers/S
|
--- Score : 802792 timers/S
|
||||||
--- Result: SUCCESS
|
--- Result: SUCCESS
|
||||||
----------------------------------------------------------------------------
|
----------------------------------------------------------------------------
|
||||||
--- Test Case 11.11 (Benchmark, semaphores wait/signal)
|
--- Test Case 11.11 (Benchmark, semaphores wait/signal)
|
||||||
--- Score : 818264 wait+signal/S
|
--- Score : 818236 wait+signal/S
|
||||||
--- Result: SUCCESS
|
--- Result: SUCCESS
|
||||||
----------------------------------------------------------------------------
|
----------------------------------------------------------------------------
|
||||||
--- Test Case 11.12 (Benchmark, mutexes lock/unlock)
|
--- Test Case 11.12 (Benchmark, mutexes lock/unlock)
|
||||||
--- Score : 643064 lock+unlock/S
|
--- Score : 643052 lock+unlock/S
|
||||||
--- Result: SUCCESS
|
--- Result: SUCCESS
|
||||||
----------------------------------------------------------------------------
|
----------------------------------------------------------------------------
|
||||||
--- Test Case 11.13 (Benchmark, RAM footprint)
|
--- Test Case 11.13 (Benchmark, RAM footprint)
|
||||||
|
|
|
||||||
|
|
@ -28,42 +28,15 @@
|
||||||
|
|
||||||
#if !defined(__DOXYGEN__)
|
#if !defined(__DOXYGEN__)
|
||||||
|
|
||||||
/* BAM info, SWT off, WTE off, VLE from settings.*/
|
/* BAM record.*/
|
||||||
.section .bam, "ax"
|
.section .bam, "ax"
|
||||||
.long 0x015A0000
|
.long 0x015A0000
|
||||||
.long .clear_ecc
|
.long .init
|
||||||
|
|
||||||
|
.init:
|
||||||
|
bl _coreinit
|
||||||
|
bl _ivinit
|
||||||
|
|
||||||
/* RAM clearing, this device requires a write to all RAM location in
|
|
||||||
order to initialize the ECC detection hardware, this is going to
|
|
||||||
slow down the startup but there is no way around.*/
|
|
||||||
.clear_ecc:
|
|
||||||
xor %r16, %r16, %r16
|
|
||||||
xor %r17, %r17, %r17
|
|
||||||
xor %r18, %r18, %r18
|
|
||||||
xor %r19, %r19, %r19
|
|
||||||
xor %r20, %r20, %r20
|
|
||||||
xor %r21, %r21, %r21
|
|
||||||
xor %r22, %r22, %r22
|
|
||||||
xor %r23, %r23, %r23
|
|
||||||
xor %r24, %r24, %r24
|
|
||||||
xor %r25, %r25, %r25
|
|
||||||
xor %r26, %r26, %r26
|
|
||||||
xor %r27, %r27, %r27
|
|
||||||
xor %r28, %r28, %r28
|
|
||||||
xor %r29, %r29, %r29
|
|
||||||
xor %r30, %r30, %r30
|
|
||||||
xor %r31, %r31, %r31
|
|
||||||
lis %r4, __ram_start__@h
|
|
||||||
ori %r4, %r4, __ram_start__@l
|
|
||||||
lis %r5, __ram_end__@h
|
|
||||||
ori %r5, %r5, __ram_end__@l
|
|
||||||
.cleareccloop:
|
|
||||||
cmpl cr0, %r4, %r5
|
|
||||||
bge cr0, .cleareccend
|
|
||||||
stmw %r16, 0(%r4)
|
|
||||||
addi %r4, %r4, 64
|
|
||||||
b .cleareccloop
|
|
||||||
.cleareccend:
|
|
||||||
b _boot_address
|
b _boot_address
|
||||||
|
|
||||||
#endif /* !defined(__DOXYGEN__) */
|
#endif /* !defined(__DOXYGEN__) */
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,216 @@
|
||||||
|
/*
|
||||||
|
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
|
||||||
|
2011,2012,2013 Giovanni Di Sirio.
|
||||||
|
|
||||||
|
This file is part of ChibiOS/RT.
|
||||||
|
|
||||||
|
ChibiOS/RT is free software; you can redistribute it and/or modify
|
||||||
|
it under the terms of the GNU General Public License as published by
|
||||||
|
the Free Software Foundation; either version 3 of the License, or
|
||||||
|
(at your option) any later version.
|
||||||
|
|
||||||
|
ChibiOS/RT is distributed in the hope that it will be useful,
|
||||||
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
GNU General Public License for more details.
|
||||||
|
|
||||||
|
You should have received a copy of the GNU General Public License
|
||||||
|
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file SPC560BCxx/core.s
|
||||||
|
* @brief e200z0 core configuration.
|
||||||
|
*
|
||||||
|
* @addtogroup PPC_CORE
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name BUCSR registers definitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define BUCSR_BPEN 0x00000001
|
||||||
|
#define BUCSR_BALLOC_BFI 0x00000200
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name BUCSR default settings
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name MSR register definitions
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define MSR_WE 0x00040000
|
||||||
|
#define MSR_CE 0x00020000
|
||||||
|
#define MSR_EE 0x00008000
|
||||||
|
#define MSR_PR 0x00004000
|
||||||
|
#define MSR_ME 0x00001000
|
||||||
|
#define MSR_DE 0x00000200
|
||||||
|
#define MSR_IS 0x00000020
|
||||||
|
#define MSR_DS 0x00000010
|
||||||
|
#define MSR_RI 0x00000002
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @name MSR default settings
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
#define MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME)
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
#if !defined(__DOXYGEN__)
|
||||||
|
|
||||||
|
.section .coreinit, "ax"
|
||||||
|
|
||||||
|
.align 2
|
||||||
|
.globl _coreinit
|
||||||
|
.type _coreinit, @function
|
||||||
|
_coreinit:
|
||||||
|
/*
|
||||||
|
* RAM clearing, this device requires a write to all RAM location in
|
||||||
|
* order to initialize the ECC detection hardware, this is going to
|
||||||
|
* slow down the startup but there is no way around.
|
||||||
|
*/
|
||||||
|
xor %r0, %r0, %r0
|
||||||
|
xor %r1, %r1, %r1
|
||||||
|
xor %r2, %r2, %r2
|
||||||
|
xor %r3, %r3, %r3
|
||||||
|
xor %r4, %r4, %r4
|
||||||
|
xor %r5, %r5, %r5
|
||||||
|
xor %r6, %r6, %r6
|
||||||
|
xor %r7, %r7, %r7
|
||||||
|
xor %r8, %r8, %r8
|
||||||
|
xor %r9, %r9, %r9
|
||||||
|
xor %r10, %r10, %r10
|
||||||
|
xor %r11, %r11, %r11
|
||||||
|
xor %r12, %r12, %r12
|
||||||
|
xor %r13, %r13, %r13
|
||||||
|
xor %r14, %r14, %r14
|
||||||
|
xor %r15, %r15, %r15
|
||||||
|
xor %r16, %r16, %r16
|
||||||
|
xor %r17, %r17, %r17
|
||||||
|
xor %r18, %r18, %r18
|
||||||
|
xor %r19, %r19, %r19
|
||||||
|
xor %r20, %r20, %r20
|
||||||
|
xor %r21, %r21, %r21
|
||||||
|
xor %r22, %r22, %r22
|
||||||
|
xor %r23, %r23, %r23
|
||||||
|
xor %r24, %r24, %r24
|
||||||
|
xor %r25, %r25, %r25
|
||||||
|
xor %r26, %r26, %r26
|
||||||
|
xor %r27, %r27, %r27
|
||||||
|
xor %r28, %r28, %r28
|
||||||
|
xor %r29, %r29, %r29
|
||||||
|
xor %r30, %r30, %r30
|
||||||
|
xor %r31, %r31, %r31
|
||||||
|
lis %r4, __ram_start__@h
|
||||||
|
ori %r4, %r4, __ram_start__@l
|
||||||
|
lis %r5, __ram_end__@h
|
||||||
|
ori %r5, %r5, __ram_end__@l
|
||||||
|
.cleareccloop:
|
||||||
|
cmpl %cr0, %r4, %r5
|
||||||
|
bge %cr0, .cleareccend
|
||||||
|
stmw %r16, 0(%r4)
|
||||||
|
addi %r4, %r4, 64
|
||||||
|
b .cleareccloop
|
||||||
|
.cleareccend:
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Branch prediction enabled.
|
||||||
|
*/
|
||||||
|
li %r3, BUCSR_DEFAULT
|
||||||
|
mtspr 1013, %r3 /* BUCSR */
|
||||||
|
|
||||||
|
blr
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Exception vectors initialization.
|
||||||
|
*/
|
||||||
|
.global _ivinit
|
||||||
|
.type _ivinit, @function
|
||||||
|
_ivinit:
|
||||||
|
/* MSR initialization.*/
|
||||||
|
lis %r3, MSR_DEFAULT@h
|
||||||
|
ori %r3, %r3, MSR_DEFAULT@l
|
||||||
|
mtMSR %r3
|
||||||
|
|
||||||
|
/* IVPR initialization.*/
|
||||||
|
lis %r3, __ivpr_base__@h
|
||||||
|
ori %r3, %r3, __ivpr_base__@l
|
||||||
|
mtIVPR %r3
|
||||||
|
|
||||||
|
blr
|
||||||
|
|
||||||
|
.section .handlers, "ax"
|
||||||
|
|
||||||
|
.globl IVORS
|
||||||
|
IVORS:
|
||||||
|
IVOR0: b IVOR0
|
||||||
|
.align 4
|
||||||
|
IVOR1: b _IVOR1
|
||||||
|
.align 4
|
||||||
|
IVOR2: b _IVOR2
|
||||||
|
.align 4
|
||||||
|
IVOR3: b _IVOR3
|
||||||
|
.align 4
|
||||||
|
IVOR4: b _IVOR4
|
||||||
|
.align 4
|
||||||
|
IVOR5: b _IVOR5
|
||||||
|
.align 4
|
||||||
|
IVOR6: b _IVOR6
|
||||||
|
.align 4
|
||||||
|
IVOR7: b _IVOR7
|
||||||
|
.align 4
|
||||||
|
IVOR8: b _IVOR8
|
||||||
|
.align 4
|
||||||
|
IVOR9: b _IVOR9
|
||||||
|
.align 4
|
||||||
|
IVOR10: b _IVOR10
|
||||||
|
.align 4
|
||||||
|
IVOR11: b _IVOR11
|
||||||
|
.align 4
|
||||||
|
IVOR12: b _IVOR12
|
||||||
|
.align 4
|
||||||
|
IVOR13: b _IVOR13
|
||||||
|
.align 4
|
||||||
|
IVOR14: b _IVOR14
|
||||||
|
.align 4
|
||||||
|
IVOR15: b _IVOR15
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Unhandled exceptions handler.
|
||||||
|
*/
|
||||||
|
.weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
|
||||||
|
.weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
|
||||||
|
.weak _IVOR12, _IVOR13, _IVOR14, _IVOR15, _IVOR32, _IVOR33
|
||||||
|
.weak _IVOR34
|
||||||
|
.weak _unhandled_exception
|
||||||
|
_IVOR0:
|
||||||
|
_IVOR1:
|
||||||
|
_IVOR2:
|
||||||
|
_IVOR3:
|
||||||
|
_IVOR5:
|
||||||
|
_IVOR6:
|
||||||
|
_IVOR7:
|
||||||
|
_IVOR8:
|
||||||
|
_IVOR9:
|
||||||
|
_IVOR11:
|
||||||
|
_IVOR12:
|
||||||
|
_IVOR13:
|
||||||
|
_IVOR14:
|
||||||
|
_IVOR15:
|
||||||
|
_IVOR32:
|
||||||
|
_IVOR33:
|
||||||
|
_IVOR34:
|
||||||
|
.type _unhandled_exception, @function
|
||||||
|
_unhandled_exception:
|
||||||
|
b _unhandled_exception
|
||||||
|
|
||||||
|
#endif /* !defined(__DOXYGEN__) */
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
@ -1,234 +0,0 @@
|
||||||
/*
|
|
||||||
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
|
|
||||||
2011,2012,2013 Giovanni Di Sirio.
|
|
||||||
|
|
||||||
This file is part of ChibiOS/RT.
|
|
||||||
|
|
||||||
ChibiOS/RT is free software; you can redistribute it and/or modify
|
|
||||||
it under the terms of the GNU General Public License as published by
|
|
||||||
the Free Software Foundation; either version 3 of the License, or
|
|
||||||
(at your option) any later version.
|
|
||||||
|
|
||||||
ChibiOS/RT is distributed in the hope that it will be useful,
|
|
||||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
GNU General Public License for more details.
|
|
||||||
|
|
||||||
You should have received a copy of the GNU General Public License
|
|
||||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
||||||
*/
|
|
||||||
|
|
||||||
/**
|
|
||||||
* @file SPC560BCxx/ivor.s
|
|
||||||
* @brief SPC560BCxx IVORx handlers.
|
|
||||||
*
|
|
||||||
* @addtogroup PPC_CORE
|
|
||||||
* @{
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Imports the PPC configuration headers.
|
|
||||||
*/
|
|
||||||
#define _FROM_ASM_
|
|
||||||
#include "chconf.h"
|
|
||||||
#include "chcore.h"
|
|
||||||
|
|
||||||
#if !defined(__DOXYGEN__)
|
|
||||||
/*
|
|
||||||
* INTC registers address.
|
|
||||||
*/
|
|
||||||
.equ INTC_IACKR, 0xfff48010
|
|
||||||
.equ INTC_EOIR, 0xfff48018
|
|
||||||
|
|
||||||
.section .handlers, "ax"
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Fixed IVOR offset table.
|
|
||||||
*/
|
|
||||||
.globl IVORS
|
|
||||||
IVORS:
|
|
||||||
IVOR0: b IVOR0
|
|
||||||
.align 4
|
|
||||||
IVOR1: b _IVOR1
|
|
||||||
.align 4
|
|
||||||
IVOR2: b _IVOR2
|
|
||||||
.align 4
|
|
||||||
IVOR3: b _IVOR3
|
|
||||||
.align 4
|
|
||||||
IVOR4: b _IVOR4
|
|
||||||
.align 4
|
|
||||||
IVOR5: b _IVOR5
|
|
||||||
.align 4
|
|
||||||
IVOR6: b _IVOR6
|
|
||||||
.align 4
|
|
||||||
IVOR7: b _IVOR7
|
|
||||||
.align 4
|
|
||||||
IVOR8: b _IVOR8
|
|
||||||
.align 4
|
|
||||||
IVOR9: b _IVOR9
|
|
||||||
.align 4
|
|
||||||
IVOR10: b _IVOR10
|
|
||||||
.align 4
|
|
||||||
IVOR11: b _IVOR11
|
|
||||||
.align 4
|
|
||||||
IVOR12: b _IVOR12
|
|
||||||
.align 4
|
|
||||||
IVOR13: b _IVOR13
|
|
||||||
.align 4
|
|
||||||
IVOR14: b _IVOR14
|
|
||||||
.align 4
|
|
||||||
IVOR15: b _IVOR15
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Unhandled exceptions handler.
|
|
||||||
*/
|
|
||||||
.weak _IVOR0
|
|
||||||
_IVOR0:
|
|
||||||
.weak _IVOR1
|
|
||||||
_IVOR1:
|
|
||||||
.weak _IVOR2
|
|
||||||
_IVOR2:
|
|
||||||
.weak _IVOR3
|
|
||||||
_IVOR3:
|
|
||||||
.weak _IVOR5
|
|
||||||
_IVOR5:
|
|
||||||
.weak _IVOR6
|
|
||||||
_IVOR6:
|
|
||||||
.weak _IVOR7
|
|
||||||
_IVOR7:
|
|
||||||
.weak _IVOR8
|
|
||||||
_IVOR8:
|
|
||||||
.weak _IVOR9
|
|
||||||
_IVOR9:
|
|
||||||
.weak _IVOR10
|
|
||||||
_IVOR10:
|
|
||||||
.weak _IVOR11
|
|
||||||
_IVOR11:
|
|
||||||
.weak _IVOR12
|
|
||||||
_IVOR12:
|
|
||||||
.weak _IVOR13
|
|
||||||
_IVOR13:
|
|
||||||
.weak _IVOR14
|
|
||||||
_IVOR14:
|
|
||||||
.weak _IVOR15
|
|
||||||
_IVOR15:
|
|
||||||
.weak _unhandled_exception
|
|
||||||
.type _unhandled_exception, @function
|
|
||||||
_unhandled_exception:
|
|
||||||
b _unhandled_exception
|
|
||||||
|
|
||||||
/*
|
|
||||||
* IVOR4 handler (Book-E external interrupt).
|
|
||||||
*/
|
|
||||||
.align 4
|
|
||||||
.globl _IVOR4
|
|
||||||
.type _IVOR4, @function
|
|
||||||
_IVOR4:
|
|
||||||
/* Creation of the external stack frame (extctx structure).*/
|
|
||||||
stwu %sp, -80(%sp) /* Size of the extctx structure.*/
|
|
||||||
#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI
|
|
||||||
e_stmvsrrw 8(%sp) /* Saves PC, MSR. */
|
|
||||||
e_stmvsprw 16(%sp) /* Saves CR, LR, CTR, XER. */
|
|
||||||
e_stmvgprw 32(%sp) /* Saves GPR0, GPR3...GPR12. */
|
|
||||||
#else /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
|
|
||||||
stw %r0, 32(%sp) /* Saves GPR0. */
|
|
||||||
mfSRR0 %r0
|
|
||||||
stw %r0, 8(%sp) /* Saves PC. */
|
|
||||||
mfSRR1 %r0
|
|
||||||
stw %r0, 12(%sp) /* Saves MSR. */
|
|
||||||
mfCR %r0
|
|
||||||
stw %r0, 16(%sp) /* Saves CR. */
|
|
||||||
mfLR %r0
|
|
||||||
stw %r0, 20(%sp) /* Saves LR. */
|
|
||||||
mfCTR %r0
|
|
||||||
stw %r0, 24(%sp) /* Saves CTR. */
|
|
||||||
mfXER %r0
|
|
||||||
stw %r0, 28(%sp) /* Saves XER. */
|
|
||||||
stw %r3, 36(%sp) /* Saves GPR3...GPR12. */
|
|
||||||
stw %r4, 40(%sp)
|
|
||||||
stw %r5, 44(%sp)
|
|
||||||
stw %r6, 48(%sp)
|
|
||||||
stw %r7, 52(%sp)
|
|
||||||
stw %r8, 56(%sp)
|
|
||||||
stw %r9, 60(%sp)
|
|
||||||
stw %r10, 64(%sp)
|
|
||||||
stw %r11, 68(%sp)
|
|
||||||
stw %r12, 72(%sp)
|
|
||||||
#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
|
|
||||||
|
|
||||||
/* Software vector address from the INTC register.*/
|
|
||||||
lis %r3, INTC_IACKR@h
|
|
||||||
ori %r3, %r3, INTC_IACKR@l /* IACKR register address. */
|
|
||||||
lwz %r3, 0(%r3) /* IACKR register value. */
|
|
||||||
lwz %r3, 0(%r3)
|
|
||||||
mtCTR %r3 /* Software handler address. */
|
|
||||||
|
|
||||||
#if PPC_USE_IRQ_PREEMPTION
|
|
||||||
/* Allows preemption while executing the software handler.*/
|
|
||||||
wrteei 1
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Exectes the software handler.*/
|
|
||||||
bctrl
|
|
||||||
|
|
||||||
#if PPC_USE_IRQ_PREEMPTION
|
|
||||||
/* Prevents preemption again.*/
|
|
||||||
wrteei 0
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Informs the INTC that the interrupt has been served.*/
|
|
||||||
mbar 0
|
|
||||||
lis %r3, INTC_EOIR@h
|
|
||||||
ori %r3, %r3, INTC_EOIR@l
|
|
||||||
stw %r3, 0(%r3) /* Writing any value should do. */
|
|
||||||
|
|
||||||
/* Verifies if a reschedule is required.*/
|
|
||||||
#if CH_DBG_SYSTEM_STATE_CHECK
|
|
||||||
bl dbg_check_lock
|
|
||||||
#endif
|
|
||||||
bl chSchIsPreemptionRequired
|
|
||||||
cmpli cr0, %r3, 0
|
|
||||||
beq cr0, _ivor_exit
|
|
||||||
bl chSchDoReschedule
|
|
||||||
|
|
||||||
/* Context restore.*/
|
|
||||||
.globl _ivor_exit
|
|
||||||
_ivor_exit:
|
|
||||||
#if CH_DBG_SYSTEM_STATE_CHECK
|
|
||||||
bl dbg_check_unlock
|
|
||||||
#endif
|
|
||||||
#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI
|
|
||||||
e_lmvgprw 32(%sp) /* Restores GPR0, GPR3...GPR12. */
|
|
||||||
e_lmvsprw 16(%sp) /* Restores CR, LR, CTR, XER. */
|
|
||||||
e_lmvsrrw 8(%sp) /* Restores PC, MSR. */
|
|
||||||
#else /*!(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
|
|
||||||
lwz %r3, 36(%sp) /* Restores GPR3...GPR12. */
|
|
||||||
lwz %r4, 40(%sp)
|
|
||||||
lwz %r5, 44(%sp)
|
|
||||||
lwz %r6, 48(%sp)
|
|
||||||
lwz %r7, 52(%sp)
|
|
||||||
lwz %r8, 56(%sp)
|
|
||||||
lwz %r9, 60(%sp)
|
|
||||||
lwz %r10, 64(%sp)
|
|
||||||
lwz %r11, 68(%sp)
|
|
||||||
lwz %r12, 72(%sp)
|
|
||||||
lwz %r0, 8(%sp)
|
|
||||||
mtSRR0 %r0 /* Restores PC. */
|
|
||||||
lwz %r0, 12(%sp)
|
|
||||||
mtSRR1 %r0 /* Restores MSR. */
|
|
||||||
lwz %r0, 16(%sp)
|
|
||||||
mtCR %r0 /* Restores CR. */
|
|
||||||
lwz %r0, 20(%sp)
|
|
||||||
mtLR %r0 /* Restores LR. */
|
|
||||||
lwz %r0, 24(%sp)
|
|
||||||
mtCTR %r0 /* Restores CTR. */
|
|
||||||
lwz %r0, 28(%sp)
|
|
||||||
mtXER %r0 /* Restores XER. */
|
|
||||||
lwz %r0, 32(%sp) /* Restores GPR0. */
|
|
||||||
#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
|
|
||||||
addi %sp, %sp, 80 /* Back to the previous frame. */
|
|
||||||
rfi
|
|
||||||
|
|
||||||
#endif /* !defined(__DOXYGEN__) */
|
|
||||||
|
|
||||||
/** @} */
|
|
||||||
|
|
@ -48,6 +48,7 @@ SECTIONS
|
||||||
.boot : ALIGN(16) SUBALIGN(16)
|
.boot : ALIGN(16) SUBALIGN(16)
|
||||||
{
|
{
|
||||||
KEEP(*(.bam))
|
KEEP(*(.bam))
|
||||||
|
KEEP(*(.coreinit))
|
||||||
KEEP(*(.crt0))
|
KEEP(*(.crt0))
|
||||||
. = ALIGN(0x00000800);
|
. = ALIGN(0x00000800);
|
||||||
KEEP(*(.vectors))
|
KEEP(*(.vectors))
|
||||||
|
|
|
||||||
|
|
@ -48,6 +48,7 @@ SECTIONS
|
||||||
.boot : ALIGN(16) SUBALIGN(16)
|
.boot : ALIGN(16) SUBALIGN(16)
|
||||||
{
|
{
|
||||||
KEEP(*(.bam))
|
KEEP(*(.bam))
|
||||||
|
KEEP(*(.coreinit))
|
||||||
KEEP(*(.crt0))
|
KEEP(*(.crt0))
|
||||||
. = ALIGN(0x00000800);
|
. = ALIGN(0x00000800);
|
||||||
KEEP(*(.vectors))
|
KEEP(*(.vectors))
|
||||||
|
|
|
||||||
|
|
@ -2,9 +2,10 @@
|
||||||
PORTSRC = ${CHIBIOS}/os/ports/GCC/PPC/chcore.c
|
PORTSRC = ${CHIBIOS}/os/ports/GCC/PPC/chcore.c
|
||||||
|
|
||||||
PORTASM = ${CHIBIOS}/os/ports/GCC/PPC/SPC560BCxx/bam.s \
|
PORTASM = ${CHIBIOS}/os/ports/GCC/PPC/SPC560BCxx/bam.s \
|
||||||
${CHIBIOS}/os/ports/GCC/PPC/crt0.s \
|
${CHIBIOS}/os/ports/GCC/PPC/SPC560BCxx/core.s \
|
||||||
${CHIBIOS}/os/ports/GCC/PPC/SPC560BCxx/ivor.s \
|
${CHIBIOS}/os/ports/GCC/PPC/SPC560BCxx/vectors.s \
|
||||||
${CHIBIOS}/os/ports/GCC/PPC/SPC560BCxx/vectors.s
|
${CHIBIOS}/os/ports/GCC/PPC/ivor.s \
|
||||||
|
${CHIBIOS}/os/ports/GCC/PPC/crt0.s
|
||||||
|
|
||||||
PORTINC = ${CHIBIOS}/os/ports/GCC/PPC \
|
PORTINC = ${CHIBIOS}/os/ports/GCC/PPC \
|
||||||
${CHIBIOS}/os/ports/GCC/PPC/SPC560BCxx
|
${CHIBIOS}/os/ports/GCC/PPC/SPC560BCxx
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue