diff --git a/os/common/ext/RP/RP2040/rp2040.h b/os/common/ext/RP/RP2040/rp2040.h index ca8652860..461077da9 100644 --- a/os/common/ext/RP/RP2040/rp2040.h +++ b/os/common/ext/RP/RP2040/rp2040.h @@ -281,503 +281,649 @@ typedef struct { * @name Base addresses * @{ */ -#define __APBPERIPH_BASE 0x40000000U -#define __AHBPERIPH_BASE 0x50000000U -#define __IOPORT_BASE 0xD0000000U -#define __DMA_BASE (__APBPERIPH_BASE + 0x00000000U) -#define __IOUSER0_BASE (__APBPERIPH_BASE + 0x00014000U) -#define __IOQSPI_BASE (__APBPERIPH_BASE + 0x00018000U) -#define __PADSUSER0_BASE (__APBPERIPH_BASE + 0x0001C000U) -#define __PADSQSPI_BASE (__APBPERIPH_BASE + 0x00020000U) -#define __RESETS_BASE (__APBPERIPH_BASE + 0x0000C000U) -#define __TIMER_BASE (__APBPERIPH_BASE + 0x00054000U) -#define __UART0_BASE (__APBPERIPH_BASE + 0x00034000U) -#define __UART1_BASE (__APBPERIPH_BASE + 0x00038000U) -#define __SIO_BASE (__IOPORT_BASE + 0x00000000U) -#define __RTC_BASE (__APBPERIPH_BASE + 0x0005c000U) +#define __APBPERIPH_BASE 0x40000000U +#define __AHBPERIPH_BASE 0x50000000U +#define __IOPORT_BASE 0xD0000000U +#define __DMA_BASE (__APBPERIPH_BASE + 0x00000000U) +#define __IOUSER0_BASE (__APBPERIPH_BASE + 0x00014000U) +#define __IOQSPI_BASE (__APBPERIPH_BASE + 0x00018000U) +#define __PADSUSER0_BASE (__APBPERIPH_BASE + 0x0001C000U) +#define __PADSQSPI_BASE (__APBPERIPH_BASE + 0x00020000U) +#define __RESETS_BASE (__APBPERIPH_BASE + 0x0000C000U) +#define __TIMER_BASE (__APBPERIPH_BASE + 0x00054000U) +#define __UART0_BASE (__APBPERIPH_BASE + 0x00034000U) +#define __UART1_BASE (__APBPERIPH_BASE + 0x00038000U) +#define __SIO_BASE (__IOPORT_BASE + 0x00000000U) +#define __RTC_BASE (__APBPERIPH_BASE + 0x0005C000U) /** @} */ /** * @name Peripherals * @{ */ -#define DMA ((DMA_TypeDef *) __DMA_BASE) -#define IO_BANK0 ((IOUSER_TypeDef *) __IOUSER0_BASE) -#define IO_QSPI ((IOUSER_TypeDef *) __IOQSPI_BASE) -#define PADS_BANK0 ((PADS_TypeDef *) __PADSUSER0_BASE) -#define PADS_QSPI ((PADS_TypeDef *) __PADSQSPI_BASE) -#define RESETS ((RESETS_TypeDef *) __RESETS_BASE) -#define SIO ((SIO_TypeDef *) __SIO_BASE) -#define TIMER ((TIMER_TypeDef *) __TIMER_BASE) -#define UART0 ((UART_TypeDef *) __UART0_BASE) -#define UART1 ((UART_TypeDef *) __UART1_BASE) -#define RTC ((RTC_TypeDef *) __RTC_BASE) +#define DMA ((DMA_TypeDef *) __DMA_BASE) +#define IO_BANK0 ((IOUSER_TypeDef *) __IOUSER0_BASE) +#define IO_QSPI ((IOUSER_TypeDef *) __IOQSPI_BASE) +#define PADS_BANK0 ((PADS_TypeDef *) __PADSUSER0_BASE) +#define PADS_QSPI ((PADS_TypeDef *) __PADSQSPI_BASE) +#define RESETS ((RESETS_TypeDef *) __RESETS_BASE) +#define SIO ((SIO_TypeDef *) __SIO_BASE) +#define TIMER ((TIMER_TypeDef *) __TIMER_BASE) +#define UART0 ((UART_TypeDef *) __UART0_BASE) +#define UART1 ((UART_TypeDef *) __UART1_BASE) +#define RTC ((RTC_TypeDef *) __RTC_BASE) /** @} */ /** * @name DMA bits definitions * @{ */ -#define DMA_CTRL_TRIG_AHB_ERROR (1U << 31) -#define DMA_CTRL_TRIG_READ_ERROR (1U << 30) -#define DMA_CTRL_TRIG_WRITE_ERROR (1U << 29) -#define DMA_CTRL_TRIG_BUSY (1U << 24) -#define DMA_CTRL_TRIG_SNIFF_EN (1U << 23) -#define DMA_CTRL_TRIG_BSWAP (1U << 22) -#define DMA_CTRL_TRIG_IRQ_QUIET (1U << 21) -#define DMA_CTRL_TRIG_TREQ_SEL_Pos 15U -#define DMA_CTRL_TRIG_TREQ_SEL_Msk (0x3FU << DMA_CTRL_TRIG_TREQ_SEL_Pos) -#define DMA_CTRL_TRIG_TREQ_SEL(n) ((n) << DMA_CTRL_TRIG_TREQ_SEL_Pos) -#define DMA_CTRL_TRIG_TREQ_TIMER0 DMA_CTRL_TRIG_TREQ_SEL(0x3BU) -#define DMA_CTRL_TRIG_TREQ_TIMER1 DMA_CTRL_TRIG_TREQ_SEL(0x3CU) -#define DMA_CTRL_TRIG_TREQ_TIMER2 DMA_CTRL_TRIG_TREQ_SEL(0x3DU) -#define DMA_CTRL_TRIG_TREQ_TIMER3 DMA_CTRL_TRIG_TREQ_SEL(0x3EU) -#define DMA_CTRL_TRIG_TREQ_PERMANENT DMA_CTRL_TRIG_TREQ_SEL(0x3FU) -#define DMA_CTRL_TRIG_CHAIN_TO_Pos 11U -#define DMA_CTRL_TRIG_CHAIN_TO_Msk (15U << DMA_CTRL_TRIG_CHAIN_TO_Pos) -#define DMA_CTRL_TRIG_CHAIN_TO(n) ((n) << DMA_CTRL_TRIG_CHAIN_TO_Pos) -#define DMA_CTRL_TRIG_RING_SEL (1U << 10) -#define DMA_CTRL_TRIG_RING_SIZE_Pos 6U -#define DMA_CTRL_TRIG_RING_SIZE_Msk (15U << DMA_CTRL_TRIG_RING_SIZE_Pos) -#define DMA_CTRL_TRIG_RING_SIZE(n) ((n) << DMA_CTRL_TRIG_RING_SIZE_Pos) -#define DMA_CTRL_TRIG_INCR_WRITE (1U << 5) -#define DMA_CTRL_TRIG_INCR_READ (1U << 4) -#define DMA_CTRL_TRIG_DATA_SIZE_Pos 2U -#define DMA_CTRL_TRIG_DATA_SIZE_Msk (3U << DMA_CTRL_TRIG_DATA_SIZE_Pos) -#define DMA_CTRL_TRIG_DATA_SIZE(n) ((n) << DMA_CTRL_TRIG_DATA_SIZE_Pos) -#define DMA_CTRL_TRIG_DATA_SIZE_BYTE DMA_CTRL_TRIG_DATA_SIZE(0U) -#define DMA_CTRL_TRIG_DATA_SIZE_HWORD DMA_CTRL_TRIG_DATA_SIZE(1U) -#define DMA_CTRL_TRIG_DATA_SIZE_WORD DMA_CTRL_TRIG_DATA_SIZE(2U) -#define DMA_CTRL_TRIG_HIGH_PRIORITY (1U << 1) -#define DMA_CTRL_TRIG_EN (1U << 0) +#define DMA_CTRL_TRIG_AHB_ERROR (1U << 31) +#define DMA_CTRL_TRIG_READ_ERROR (1U << 30) +#define DMA_CTRL_TRIG_WRITE_ERROR (1U << 29) +#define DMA_CTRL_TRIG_BUSY (1U << 24) +#define DMA_CTRL_TRIG_SNIFF_EN (1U << 23) +#define DMA_CTRL_TRIG_BSWAP (1U << 22) +#define DMA_CTRL_TRIG_IRQ_QUIET (1U << 21) +#define DMA_CTRL_TRIG_TREQ_SEL_Pos 15U +#define DMA_CTRL_TRIG_TREQ_SEL_Msk (0x3FU << DMA_CTRL_TRIG_TREQ_SEL_Pos) +#define DMA_CTRL_TRIG_TREQ_SEL(n) ((n) << DMA_CTRL_TRIG_TREQ_SEL_Pos) +#define DMA_CTRL_TRIG_TREQ_TIMER0 DMA_CTRL_TRIG_TREQ_SEL(0x3BU) +#define DMA_CTRL_TRIG_TREQ_TIMER1 DMA_CTRL_TRIG_TREQ_SEL(0x3CU) +#define DMA_CTRL_TRIG_TREQ_TIMER2 DMA_CTRL_TRIG_TREQ_SEL(0x3DU) +#define DMA_CTRL_TRIG_TREQ_TIMER3 DMA_CTRL_TRIG_TREQ_SEL(0x3EU) +#define DMA_CTRL_TRIG_TREQ_PERMANENT DMA_CTRL_TRIG_TREQ_SEL(0x3FU) +#define DMA_CTRL_TRIG_CHAIN_TO_Pos 11U +#define DMA_CTRL_TRIG_CHAIN_TO_Msk (15U << DMA_CTRL_TRIG_CHAIN_TO_Pos) +#define DMA_CTRL_TRIG_CHAIN_TO(n) ((n) << DMA_CTRL_TRIG_CHAIN_TO_Pos) +#define DMA_CTRL_TRIG_RING_SEL (1U << 10) +#define DMA_CTRL_TRIG_RING_SIZE_Pos 6U +#define DMA_CTRL_TRIG_RING_SIZE_Msk (15U << DMA_CTRL_TRIG_RING_SIZE_Pos) +#define DMA_CTRL_TRIG_RING_SIZE(n) ((n) << DMA_CTRL_TRIG_RING_SIZE_Pos) +#define DMA_CTRL_TRIG_INCR_WRITE (1U << 5) +#define DMA_CTRL_TRIG_INCR_READ (1U << 4) +#define DMA_CTRL_TRIG_DATA_SIZE_Pos 2U +#define DMA_CTRL_TRIG_DATA_SIZE_Msk (3U << DMA_CTRL_TRIG_DATA_SIZE_Pos) +#define DMA_CTRL_TRIG_DATA_SIZE(n) ((n) << DMA_CTRL_TRIG_DATA_SIZE_Pos) +#define DMA_CTRL_TRIG_DATA_SIZE_BYTE DMA_CTRL_TRIG_DATA_SIZE(0U) +#define DMA_CTRL_TRIG_DATA_SIZE_HWORD DMA_CTRL_TRIG_DATA_SIZE(1U) +#define DMA_CTRL_TRIG_DATA_SIZE_WORD DMA_CTRL_TRIG_DATA_SIZE(2U) +#define DMA_CTRL_TRIG_HIGH_PRIORITY (1U << 1) +#define DMA_CTRL_TRIG_EN (1U << 0) /** @} */ /** * @name RESETS bits definitions * @{ */ -#define RESETS_ALLREG_USBCTRL (1U << 24) -#define RESETS_ALLREG_UART1 (1U << 23) -#define RESETS_ALLREG_UART0 (1U << 22) -#define RESETS_ALLREG_TIMER (1U << 21) -#define RESETS_ALLREG_TBMAN (1U << 20) -#define RESETS_ALLREG_SYSINFO (1U << 19) -#define RESETS_ALLREG_SYSCFG (1U << 18) -#define RESETS_ALLREG_SPI1 (1U << 17) -#define RESETS_ALLREG_SPI0 (1U << 16) -#define RESETS_ALLREG_RTC (1U << 15) -#define RESETS_ALLREG_PWM (1U << 14) -#define RESETS_ALLREG_PLL_USB (1U << 13) -#define RESETS_ALLREG_PLL_SYS (1U << 12) -#define RESETS_ALLREG_PIO1 (1U << 11) -#define RESETS_ALLREG_PIO0 (1U << 10) -#define RESETS_ALLREG_PADS_QSPI (1U << 9) -#define RESETS_ALLREG_PADS_BANK0 (1U << 8) -#define RESETS_ALLREG_JTAG (1U << 7) -#define RESETS_ALLREG_IO_QSPI (1U << 6) -#define RESETS_ALLREG_IO_BANK0 (1U << 5) -#define RESETS_ALLREG_I2C1 (1U << 4) -#define RESETS_ALLREG_I2C0 (1U << 3) -#define RESETS_ALLREG_DMA (1U << 2) -#define RESETS_ALLREG_BUSCTRL (1U << 1) -#define RESETS_ALLREG_ADC (1U << 0) +#define RESETS_ALLREG_USBCTRL (1U << 24) +#define RESETS_ALLREG_UART1 (1U << 23) +#define RESETS_ALLREG_UART0 (1U << 22) +#define RESETS_ALLREG_TIMER (1U << 21) +#define RESETS_ALLREG_TBMAN (1U << 20) +#define RESETS_ALLREG_SYSINFO (1U << 19) +#define RESETS_ALLREG_SYSCFG (1U << 18) +#define RESETS_ALLREG_SPI1 (1U << 17) +#define RESETS_ALLREG_SPI0 (1U << 16) +#define RESETS_ALLREG_RTC (1U << 15) +#define RESETS_ALLREG_PWM (1U << 14) +#define RESETS_ALLREG_PLL_USB (1U << 13) +#define RESETS_ALLREG_PLL_SYS (1U << 12) +#define RESETS_ALLREG_PIO1 (1U << 11) +#define RESETS_ALLREG_PIO0 (1U << 10) +#define RESETS_ALLREG_PADS_QSPI (1U << 9) +#define RESETS_ALLREG_PADS_BANK0 (1U << 8) +#define RESETS_ALLREG_JTAG (1U << 7) +#define RESETS_ALLREG_IO_QSPI (1U << 6) +#define RESETS_ALLREG_IO_BANK0 (1U << 5) +#define RESETS_ALLREG_I2C1 (1U << 4) +#define RESETS_ALLREG_I2C0 (1U << 3) +#define RESETS_ALLREG_DMA (1U << 2) +#define RESETS_ALLREG_BUSCTRL (1U << 1) +#define RESETS_ALLREG_ADC (1U << 0) /** @} */ /** * @name SIO bits definitions * @{ */ -#define SIO_FIFO_ST_VLD_Pos 0U -#define SIO_FIFO_ST_VLD_Msk (1U << SIO_FIFO_ST_VLD_Pos) -#define SIO_FIFO_ST_VLD SIO_FIFO_ST_VLD_Msk -#define SIO_FIFO_ST_RDY_Pos 1U -#define SIO_FIFO_ST_RDY_Msk (1U << SIO_FIFO_ST_RDY_Pos) -#define SIO_FIFO_ST_RDY SIO_FIFO_ST_RDY_Msk -#define SIO_FIFO_ST_WOF_Pos 2U -#define SIO_FIFO_ST_WOF_Msk (1U << SIO_FIFO_ST_WOF_Pos) -#define SIO_FIFO_ST_WOF SIO_FIFO_ST_WOF_Msk -#define SIO_FIFO_ST_ROE_Pos 3U -#define SIO_FIFO_ST_ROE_Msk (1U << SIO_FIFO_ST_ROE_Pos) -#define SIO_FIFO_ST_ROE SIO_FIFO_ST_ROE_Msk +#define SIO_FIFO_ST_VLD_Pos 0U +#define SIO_FIFO_ST_VLD_Msk (1U << SIO_FIFO_ST_VLD_Pos) +#define SIO_FIFO_ST_VLD SIO_FIFO_ST_VLD_Msk +#define SIO_FIFO_ST_RDY_Pos 1U +#define SIO_FIFO_ST_RDY_Msk (1U << SIO_FIFO_ST_RDY_Pos) +#define SIO_FIFO_ST_RDY SIO_FIFO_ST_RDY_Msk +#define SIO_FIFO_ST_WOF_Pos 2U +#define SIO_FIFO_ST_WOF_Msk (1U << SIO_FIFO_ST_WOF_Pos) +#define SIO_FIFO_ST_WOF SIO_FIFO_ST_WOF_Msk +#define SIO_FIFO_ST_ROE_Pos 3U +#define SIO_FIFO_ST_ROE_Msk (1U << SIO_FIFO_ST_ROE_Pos) +#define SIO_FIFO_ST_ROE SIO_FIFO_ST_ROE_Msk /** @} */ /** * @name TIMER bits definitions * @{ */ -#define TIMER_ARMED_ALARM0_Pos 0U -#define TIMER_ARMED_ALARM0_Msk (1U << TIMER_ARMED_ALARM0_Pos) -#define TIMER_ARMED_ALARM0 TIMER_ARMED_ALARM0_Msk -#define TIMER_ARMED_ALARM1_Pos 1U -#define TIMER_ARMED_ALARM1_Msk (1U << TIMER_ARMED_ALARM1_Pos) -#define TIMER_ARMED_ALARM1 TIMER_ARMED_ALARM1_Msk -#define TIMER_ARMED_ALARM2_Pos 2U -#define TIMER_ARMED_ALARM2_Msk (1U << TIMER_ARMED_ALARM2_Pos) -#define TIMER_ARMED_ALARM2 TIMER_ARMED_ALARM2_Msk -#define TIMER_ARMED_ALARM3_Pos 3U -#define TIMER_ARMED_ALARM3_Msk (1U << TIMER_ARMED_ALARM3_Pos) -#define TIMER_ARMED_ALARM3 TIMER_ARMED_ALARM3_Msk +#define TIMER_ARMED_ALARM0_Pos 0U +#define TIMER_ARMED_ALARM0_Msk (1U << TIMER_ARMED_ALARM0_Pos) +#define TIMER_ARMED_ALARM0 TIMER_ARMED_ALARM0_Msk +#define TIMER_ARMED_ALARM1_Pos 1U +#define TIMER_ARMED_ALARM1_Msk (1U << TIMER_ARMED_ALARM1_Pos) +#define TIMER_ARMED_ALARM1 TIMER_ARMED_ALARM1_Msk +#define TIMER_ARMED_ALARM2_Pos 2U +#define TIMER_ARMED_ALARM2_Msk (1U << TIMER_ARMED_ALARM2_Pos) +#define TIMER_ARMED_ALARM2 TIMER_ARMED_ALARM2_Msk +#define TIMER_ARMED_ALARM3_Pos 3U +#define TIMER_ARMED_ALARM3_Msk (1U << TIMER_ARMED_ALARM3_Pos) +#define TIMER_ARMED_ALARM3 TIMER_ARMED_ALARM3_Msk -#define TIMER_DBGPAUSE_DBG0_Pos 1U -#define TIMER_DBGPAUSE_DBG0_Msk (1U << TIMER_DBGPAUSE_DBG0_Pos) -#define TIMER_DBGPAUSE_DBG0 TIMER_DBGPAUSE_DBG0_Msk -#define TIMER_DBGPAUSE_DBG1_Pos 2U -#define TIMER_DBGPAUSE_DBG1_Msk (1U << TIMER_DBGPAUSE_DBG1_Pos) -#define TIMER_DBGPAUSE_DBG1 TIMER_DBGPAUSE_DBG1_Msk +#define TIMER_DBGPAUSE_DBG0_Pos 1U +#define TIMER_DBGPAUSE_DBG0_Msk (1U << TIMER_DBGPAUSE_DBG0_Pos) +#define TIMER_DBGPAUSE_DBG0 TIMER_DBGPAUSE_DBG0_Msk +#define TIMER_DBGPAUSE_DBG1_Pos 2U +#define TIMER_DBGPAUSE_DBG1_Msk (1U << TIMER_DBGPAUSE_DBG1_Pos) +#define TIMER_DBGPAUSE_DBG1 TIMER_DBGPAUSE_DBG1_Msk -#define TIMER_PAUSE_PAUSE_Pos 0U -#define TIMER_PAUSE_PAUSE_Msk (1U << TIMER_PAUSE_PAUSE_Pos) -#define TIMER_PAUSE_PAUSE TIMER_PAUSE_PAUSE_Msk +#define TIMER_PAUSE_PAUSE_Pos 0U +#define TIMER_PAUSE_PAUSE_Msk (1U << TIMER_PAUSE_PAUSE_Pos) +#define TIMER_PAUSE_PAUSE TIMER_PAUSE_PAUSE_Msk -#define TIMER_INTR_ALARM0_Pos 0U -#define TIMER_INTR_ALARM0_Msk (1U << TIMER_INTR_ALARM0_Pos) -#define TIMER_INTR_ALARM0 TIMER_INTR_ALARM0_Msk -#define TIMER_INTR_ALARM1_Pos 1U -#define TIMER_INTR_ALARM1_Msk (1U << TIMER_INTR_ALARM1_Pos) -#define TIMER_INTR_ALARM1 TIMER_INTR_ALARM1_Msk -#define TIMER_INTR_ALARM2_Pos 2U -#define TIMER_INTR_ALARM2_Msk (1U << TIMER_INTR_ALARM2_Pos) -#define TIMER_INTR_ALARM2 TIMER_INTR_ALARM2_Msk -#define TIMER_INTR_ALARM3_Pos 3U -#define TIMER_INTR_ALARM3_Msk (1U << TIMER_INTR_ALARM3_Pos) -#define TIMER_INTR_ALARM3 TIMER_INTR_ALARM3_Msk +#define TIMER_INTR_ALARM0_Pos 0U +#define TIMER_INTR_ALARM0_Msk (1U << TIMER_INTR_ALARM0_Pos) +#define TIMER_INTR_ALARM0 TIMER_INTR_ALARM0_Msk +#define TIMER_INTR_ALARM1_Pos 1U +#define TIMER_INTR_ALARM1_Msk (1U << TIMER_INTR_ALARM1_Pos) +#define TIMER_INTR_ALARM1 TIMER_INTR_ALARM1_Msk +#define TIMER_INTR_ALARM2_Pos 2U +#define TIMER_INTR_ALARM2_Msk (1U << TIMER_INTR_ALARM2_Pos) +#define TIMER_INTR_ALARM2 TIMER_INTR_ALARM2_Msk +#define TIMER_INTR_ALARM3_Pos 3U +#define TIMER_INTR_ALARM3_Msk (1U << TIMER_INTR_ALARM3_Pos) +#define TIMER_INTR_ALARM3 TIMER_INTR_ALARM3_Msk -#define TIMER_INTE_ALARM0_Pos 0U -#define TIMER_INTE_ALARM0_Msk (1U << TIMER_INTE_ALARM0_Pos) -#define TIMER_INTE_ALARM0 TIMER_INTE_ALARM0_Msk -#define TIMER_INTE_ALARM1_Pos 1U -#define TIMER_INTE_ALARM1_Msk (1U << TIMER_INTE_ALARM1_Pos) -#define TIMER_INTE_ALARM1 TIMER_INTE_ALARM1_Msk -#define TIMER_INTE_ALARM2_Pos 2U -#define TIMER_INTE_ALARM2_Msk (1U << TIMER_INTE_ALARM2_Pos) -#define TIMER_INTE_ALARM2 TIMER_INTE_ALARM2_Msk -#define TIMER_INTE_ALARM3_Pos 3U -#define TIMER_INTE_ALARM3_Msk (1U << TIMER_INTE_ALARM3_Pos) -#define TIMER_INTE_ALARM3 TIMER_INTE_ALARM3_Msk +#define TIMER_INTE_ALARM0_Pos 0U +#define TIMER_INTE_ALARM0_Msk (1U << TIMER_INTE_ALARM0_Pos) +#define TIMER_INTE_ALARM0 TIMER_INTE_ALARM0_Msk +#define TIMER_INTE_ALARM1_Pos 1U +#define TIMER_INTE_ALARM1_Msk (1U << TIMER_INTE_ALARM1_Pos) +#define TIMER_INTE_ALARM1 TIMER_INTE_ALARM1_Msk +#define TIMER_INTE_ALARM2_Pos 2U +#define TIMER_INTE_ALARM2_Msk (1U << TIMER_INTE_ALARM2_Pos) +#define TIMER_INTE_ALARM2 TIMER_INTE_ALARM2_Msk +#define TIMER_INTE_ALARM3_Pos 3U +#define TIMER_INTE_ALARM3_Msk (1U << TIMER_INTE_ALARM3_Pos) +#define TIMER_INTE_ALARM3 TIMER_INTE_ALARM3_Msk -#define TIMER_INTF_ALARM0_Pos 0U -#define TIMER_INTF_ALARM0_Msk (1U << TIMER_INTF_ALARM0_Pos) -#define TIMER_INTF_ALARM0 TIMER_INTF_ALARM0_Msk -#define TIMER_INTF_ALARM1_Pos 1U -#define TIMER_INTF_ALARM1_Msk (1U << TIMER_INTF_ALARM1_Pos) -#define TIMER_INTF_ALARM1 TIMER_INTF_ALARM1_Msk -#define TIMER_INTF_ALARM2_Pos 2U -#define TIMER_INTF_ALARM2_Msk (1U << TIMER_INTF_ALARM2_Pos) -#define TIMER_INTF_ALARM2 TIMER_INTF_ALARM2_Msk -#define TIMER_INTF_ALARM3_Pos 3U -#define TIMER_INTF_ALARM3_Msk (1U << TIMER_INTF_ALARM3_Pos) -#define TIMER_INTF_ALARM3 TIMER_INTF_ALARM3_Msk +#define TIMER_INTF_ALARM0_Pos 0U +#define TIMER_INTF_ALARM0_Msk (1U << TIMER_INTF_ALARM0_Pos) +#define TIMER_INTF_ALARM0 TIMER_INTF_ALARM0_Msk +#define TIMER_INTF_ALARM1_Pos 1U +#define TIMER_INTF_ALARM1_Msk (1U << TIMER_INTF_ALARM1_Pos) +#define TIMER_INTF_ALARM1 TIMER_INTF_ALARM1_Msk +#define TIMER_INTF_ALARM2_Pos 2U +#define TIMER_INTF_ALARM2_Msk (1U << TIMER_INTF_ALARM2_Pos) +#define TIMER_INTF_ALARM2 TIMER_INTF_ALARM2_Msk +#define TIMER_INTF_ALARM3_Pos 3U +#define TIMER_INTF_ALARM3_Msk (1U << TIMER_INTF_ALARM3_Pos) +#define TIMER_INTF_ALARM3 TIMER_INTF_ALARM3_Msk -#define TIMER_INTS_ALARM0_Pos 0U -#define TIMER_INTS_ALARM0_Msk (1U << TIMER_INTS_ALARM0_Pos) -#define TIMER_INTS_ALARM0 TIMER_INTS_ALARM0_Msk -#define TIMER_INTS_ALARM1_Pos 1U -#define TIMER_INTS_ALARM1_Msk (1U << TIMER_INTS_ALARM1_Pos) -#define TIMER_INTS_ALARM1 TIMER_INTS_ALARM1_Msk -#define TIMER_INTS_ALARM2_Pos 2U -#define TIMER_INTS_ALARM2_Msk (1U << TIMER_INTS_ALARM2_Pos) -#define TIMER_INTS_ALARM2 TIMER_INTS_ALARM2_Msk -#define TIMER_INTS_ALARM3_Pos 3U -#define TIMER_INTS_ALARM3_Msk (1U << TIMER_INTS_ALARM3_Pos) -#define TIMER_INTS_ALARM3 TIMER_INTS_ALARM3_Msk +#define TIMER_INTS_ALARM0_Pos 0U +#define TIMER_INTS_ALARM0_Msk (1U << TIMER_INTS_ALARM0_Pos) +#define TIMER_INTS_ALARM0 TIMER_INTS_ALARM0_Msk +#define TIMER_INTS_ALARM1_Pos 1U +#define TIMER_INTS_ALARM1_Msk (1U << TIMER_INTS_ALARM1_Pos) +#define TIMER_INTS_ALARM1 TIMER_INTS_ALARM1_Msk +#define TIMER_INTS_ALARM2_Pos 2U +#define TIMER_INTS_ALARM2_Msk (1U << TIMER_INTS_ALARM2_Pos) +#define TIMER_INTS_ALARM2 TIMER_INTS_ALARM2_Msk +#define TIMER_INTS_ALARM3_Pos 3U +#define TIMER_INTS_ALARM3_Msk (1U << TIMER_INTS_ALARM3_Pos) +#define TIMER_INTS_ALARM3 TIMER_INTS_ALARM3_Msk /** @} */ /** * @name UART bits definitions * @{ */ -#define UART_UARTDR_OE_Pos 11U -#define UART_UARTDR_OE_Msk (1U << UART_UARTDR_OE_Pos) -#define UART_UARTDR_OE UART_UARTDR_OE_Msk -#define UART_UARTDR_BE_Pos 10U -#define UART_UARTDR_BE_Msk (1U << UART_UARTDR_BE_Pos) -#define UART_UARTDR_BE UART_UARTDR_BE_Msk -#define UART_UARTDR_PE_Pos 9U -#define UART_UARTDR_PE_Msk (1U << UART_UARTDR_PE_Pos) -#define UART_UARTDR_PE UART_UARTDR_PE_Msk -#define UART_UARTDR_FE_Pos 8U -#define UART_UARTDR_FE_Msk (1U << UART_UARTDR_FE_Pos) -#define UART_UARTDR_FE UART_UARTDR_FE_Msk +#define UART_UARTDR_OE_Pos 11U +#define UART_UARTDR_OE_Msk (1U << UART_UARTDR_OE_Pos) +#define UART_UARTDR_OE UART_UARTDR_OE_Msk +#define UART_UARTDR_BE_Pos 10U +#define UART_UARTDR_BE_Msk (1U << UART_UARTDR_BE_Pos) +#define UART_UARTDR_BE UART_UARTDR_BE_Msk +#define UART_UARTDR_PE_Pos 9U +#define UART_UARTDR_PE_Msk (1U << UART_UARTDR_PE_Pos) +#define UART_UARTDR_PE UART_UARTDR_PE_Msk +#define UART_UARTDR_FE_Pos 8U +#define UART_UARTDR_FE_Msk (1U << UART_UARTDR_FE_Pos) +#define UART_UARTDR_FE UART_UARTDR_FE_Msk -#define UART_UARTRSR_OE_Pos 3U -#define UART_UARTRSR_OE_Msk (1U << UART_UARTRSR_OE_Pos) -#define UART_UARTRSR_OE UART_UARTRSR_OE_Msk -#define UART_UARTRSR_BE_Pos 2U -#define UART_UARTRSR_BE_Msk (1U << UART_UARTRSR_BE_Pos) -#define UART_UARTRSR_BE UART_UARTRSR_BE_Msk -#define UART_UARTRSR_PE_Pos 1U -#define UART_UARTRSR_PE_Msk (1U << UART_UARTRSR_PE_Pos) -#define UART_UARTRSR_PE UART_UARTRSR_PE_Msk -#define UART_UARTRSR_FE_Pos 0U -#define UART_UARTRSR_FE_Msk (1U << UART_UARTRSR_FE_Pos) -#define UART_UARTRSR_FE UART_UARTRSR_FE_Msk +#define UART_UARTRSR_OE_Pos 3U +#define UART_UARTRSR_OE_Msk (1U << UART_UARTRSR_OE_Pos) +#define UART_UARTRSR_OE UART_UARTRSR_OE_Msk +#define UART_UARTRSR_BE_Pos 2U +#define UART_UARTRSR_BE_Msk (1U << UART_UARTRSR_BE_Pos) +#define UART_UARTRSR_BE UART_UARTRSR_BE_Msk +#define UART_UARTRSR_PE_Pos 1U +#define UART_UARTRSR_PE_Msk (1U << UART_UARTRSR_PE_Pos) +#define UART_UARTRSR_PE UART_UARTRSR_PE_Msk +#define UART_UARTRSR_FE_Pos 0U +#define UART_UARTRSR_FE_Msk (1U << UART_UARTRSR_FE_Pos) +#define UART_UARTRSR_FE UART_UARTRSR_FE_Msk -#define UART_UARTFR_RI_Pos 8U -#define UART_UARTFR_RI_Msk (1U << UART_UARTFR_RI_Pos) -#define UART_UARTFR_RI UART_UARTFR_RI_Msk -#define UART_UARTFR_TXFE_Pos 7U -#define UART_UARTFR_TXFE_Msk (1U << UART_UARTFR_TXFE_Pos) -#define UART_UARTFR_TXFE UART_UARTFR_TXFE_Msk -#define UART_UARTFR_RXFF_Pos 6U -#define UART_UARTFR_RXFF_Msk (1U << UART_UARTFR_RXFF_Pos) -#define UART_UARTFR_RXFF UART_UARTFR_RXFF_Msk -#define UART_UARTFR_TXFF_Pos 5U -#define UART_UARTFR_TXFF_Msk (1U << UART_UARTFR_TXFF_Pos) -#define UART_UARTFR_TXFF UART_UARTFR_TXFF_Msk -#define UART_UARTFR_RXFE_Pos 4U -#define UART_UARTFR_RXFE_Msk (1U << UART_UARTFR_RXFE_Pos) -#define UART_UARTFR_RXFE UART_UARTFR_RXFE_Msk -#define UART_UARTFR_BUSY_Pos 3U -#define UART_UARTFR_BUSY_Msk (1U << UART_UARTFR_BUSY_Pos) -#define UART_UARTFR_BUSY UART_UARTFR_BUSY_Msk -#define UART_UARTFR_DCD_Pos 2U -#define UART_UARTFR_DCD_Msk (1U << UART_UARTFR_DCD_Pos) -#define UART_UARTFR_DCD UART_UARTFR_DCD_Msk -#define UART_UARTFR_DSR_Pos 1U -#define UART_UARTFR_DSR_Msk (1U << UART_UARTFR_DSR_Pos) -#define UART_UARTFR_DSR UART_UARTFR_DSR_Msk -#define UART_UARTFR_CTS_Pos 0U -#define UART_UARTFR_CTS_Msk (1U << UART_UARTFR_CTS_Pos) -#define UART_UARTFR_CTS UART_UARTFR_CTS_Msk +#define UART_UARTFR_RI_Pos 8U +#define UART_UARTFR_RI_Msk (1U << UART_UARTFR_RI_Pos) +#define UART_UARTFR_RI UART_UARTFR_RI_Msk +#define UART_UARTFR_TXFE_Pos 7U +#define UART_UARTFR_TXFE_Msk (1U << UART_UARTFR_TXFE_Pos) +#define UART_UARTFR_TXFE UART_UARTFR_TXFE_Msk +#define UART_UARTFR_RXFF_Pos 6U +#define UART_UARTFR_RXFF_Msk (1U << UART_UARTFR_RXFF_Pos) +#define UART_UARTFR_RXFF UART_UARTFR_RXFF_Msk +#define UART_UARTFR_TXFF_Pos 5U +#define UART_UARTFR_TXFF_Msk (1U << UART_UARTFR_TXFF_Pos) +#define UART_UARTFR_TXFF UART_UARTFR_TXFF_Msk +#define UART_UARTFR_RXFE_Pos 4U +#define UART_UARTFR_RXFE_Msk (1U << UART_UARTFR_RXFE_Pos) +#define UART_UARTFR_RXFE UART_UARTFR_RXFE_Msk +#define UART_UARTFR_BUSY_Pos 3U +#define UART_UARTFR_BUSY_Msk (1U << UART_UARTFR_BUSY_Pos) +#define UART_UARTFR_BUSY UART_UARTFR_BUSY_Msk +#define UART_UARTFR_DCD_Pos 2U +#define UART_UARTFR_DCD_Msk (1U << UART_UARTFR_DCD_Pos) +#define UART_UARTFR_DCD UART_UARTFR_DCD_Msk +#define UART_UARTFR_DSR_Pos 1U +#define UART_UARTFR_DSR_Msk (1U << UART_UARTFR_DSR_Pos) +#define UART_UARTFR_DSR UART_UARTFR_DSR_Msk +#define UART_UARTFR_CTS_Pos 0U +#define UART_UARTFR_CTS_Msk (1U << UART_UARTFR_CTS_Pos) +#define UART_UARTFR_CTS UART_UARTFR_CTS_Msk -#define UART_UARTILPR_ILPDVSR_Pos 0U -#define UART_UARTILPR_ILPDVSR_Msk (255U << UART_UARTILPR_ILPDVSR_Pos) -#define UART_UARTILPR_ILPDVSR(n) ((n) << UART_UARTILPR_ILPDVSR_Pos) +#define UART_UARTILPR_ILPDVSR_Pos 0U +#define UART_UARTILPR_ILPDVSR_Msk (255U << UART_UARTILPR_ILPDVSR_Pos) +#define UART_UARTILPR_ILPDVSR(n) ((n) << UART_UARTILPR_ILPDVSR_Pos) -#define UART_UARTIBRD_BAUD_DIVINT_Pos 0U -#define UART_UARTIBRD_BAUD_DIVINT_Msk (0xFFFFU << UART_UARTIBRD_BAUD_DIVINT_Pos) -#define UART_UARTIBRD_BAUD_DIVINT(n) ((n) << UART_UARTIBRD_BAUD_DIVINT_Pos) +#define UART_UARTIBRD_BAUD_DIVINT_Pos 0U +#define UART_UARTIBRD_BAUD_DIVINT_Msk (0xFFFFU << UART_UARTIBRD_BAUD_DIVINT_Pos) +#define UART_UARTIBRD_BAUD_DIVINT(n) ((n) << UART_UARTIBRD_BAUD_DIVINT_Pos) -#define UART_UARTFBRD_BAUD_DIVFRAC_Pos 0U -#define UART_UARTFBRD_BAUD_DIVFRAC_Msk (63U << UART_UARTFBRD_BAUD_DIVFRAC_Pos) -#define UART_UARTFBRD_BAUD_DIVFRAC(n) ((n) << UART_UARTFBRD_BAUD_DIVFRAC_Pos) +#define UART_UARTFBRD_BAUD_DIVFRAC_Pos 0U +#define UART_UARTFBRD_BAUD_DIVFRAC_Msk (63U << UART_UARTFBRD_BAUD_DIVFRAC_Pos) +#define UART_UARTFBRD_BAUD_DIVFRAC(n) ((n) << UART_UARTFBRD_BAUD_DIVFRAC_Pos) -#define UART_UARTLCR_H_SPS_Pos 7U -#define UART_UARTLCR_H_SPS_Msk (1U << UART_UARTLCR_H_SPS_Pos) -#define UART_UARTLCR_H_SPS UART_UARTLCR_H_SPS_Msk -#define UART_UARTLCR_H_WLEN_Pos 5U -#define UART_UARTLCR_H_WLEN_Msk (1U << UART_UARTLCR_H_WLEN_Pos) -#define UART_UARTLCR_H_WLEN(n) ((n) << UART_UARTLCR_H_WLEN_Pos) -#define UART_UARTLCR_H_WLEN_5BITS UART_UARTLCR_H_WLEN(0U) -#define UART_UARTLCR_H_WLEN_6BITS UART_UARTLCR_H_WLEN(1U) -#define UART_UARTLCR_H_WLEN_7BITS UART_UARTLCR_H_WLEN(2U) -#define UART_UARTLCR_H_WLEN_8BITS UART_UARTLCR_H_WLEN(3U) -#define UART_UARTLCR_H_FEN_Pos 4U -#define UART_UARTLCR_H_FEN_Msk (1U << UART_UARTLCR_H_FEN_Pos) -#define UART_UARTLCR_H_FEN UART_UARTLCR_H_FEN_Msk -#define UART_UARTLCR_H_STP2_Pos 3U -#define UART_UARTLCR_H_STP2_Msk (1U << UART_UARTLCR_H_STP2_Pos) -#define UART_UARTLCR_H_STP2 UART_UARTLCR_H_STP2_Msk -#define UART_UARTLCR_H_EPS_Pos 2U -#define UART_UARTLCR_H_EPS_Msk (1U << UART_UARTLCR_H_EPS_Pos) -#define UART_UARTLCR_H_EPS UART_UARTLCR_H_EPS_Msk -#define UART_UARTLCR_H_PEN_Pos 1U -#define UART_UARTLCR_H_PEN_Msk (1U << UART_UARTLCR_H_PEN_Pos) -#define UART_UARTLCR_H_PEN UART_UARTLCR_H_PEN_Msk -#define UART_UARTLCR_H_BRK_Pos 0U -#define UART_UARTLCR_H_BRK_Msk (1U << UART_UARTLCR_H_BRK_Pos) -#define UART_UARTLCR_H_BRK UART_UARTLCR_H_BRK_Msk +#define UART_UARTLCR_H_SPS_Pos 7U +#define UART_UARTLCR_H_SPS_Msk (1U << UART_UARTLCR_H_SPS_Pos) +#define UART_UARTLCR_H_SPS UART_UARTLCR_H_SPS_Msk +#define UART_UARTLCR_H_WLEN_Pos 5U +#define UART_UARTLCR_H_WLEN_Msk (1U << UART_UARTLCR_H_WLEN_Pos) +#define UART_UARTLCR_H_WLEN(n) ((n) << UART_UARTLCR_H_WLEN_Pos) +#define UART_UARTLCR_H_WLEN_5BITS UART_UARTLCR_H_WLEN(0U) +#define UART_UARTLCR_H_WLEN_6BITS UART_UARTLCR_H_WLEN(1U) +#define UART_UARTLCR_H_WLEN_7BITS UART_UARTLCR_H_WLEN(2U) +#define UART_UARTLCR_H_WLEN_8BITS UART_UARTLCR_H_WLEN(3U) +#define UART_UARTLCR_H_FEN_Pos 4U +#define UART_UARTLCR_H_FEN_Msk (1U << UART_UARTLCR_H_FEN_Pos) +#define UART_UARTLCR_H_FEN UART_UARTLCR_H_FEN_Msk +#define UART_UARTLCR_H_STP2_Pos 3U +#define UART_UARTLCR_H_STP2_Msk (1U << UART_UARTLCR_H_STP2_Pos) +#define UART_UARTLCR_H_STP2 UART_UARTLCR_H_STP2_Msk +#define UART_UARTLCR_H_EPS_Pos 2U +#define UART_UARTLCR_H_EPS_Msk (1U << UART_UARTLCR_H_EPS_Pos) +#define UART_UARTLCR_H_EPS UART_UARTLCR_H_EPS_Msk +#define UART_UARTLCR_H_PEN_Pos 1U +#define UART_UARTLCR_H_PEN_Msk (1U << UART_UARTLCR_H_PEN_Pos) +#define UART_UARTLCR_H_PEN UART_UARTLCR_H_PEN_Msk +#define UART_UARTLCR_H_BRK_Pos 0U +#define UART_UARTLCR_H_BRK_Msk (1U << UART_UARTLCR_H_BRK_Pos) +#define UART_UARTLCR_H_BRK UART_UARTLCR_H_BRK_Msk -#define UART_UARTCR_CTSEN_Pos 15U -#define UART_UARTCR_CTSEN_Msk (1U << UART_UARTCR_CTSEN_Pos) -#define UART_UARTCR_CTSEN UART_UARTCR_CTSEN_Msk -#define UART_UARTCR_RTSEN_Pos 14U -#define UART_UARTCR_RTSEN_Msk (1U << UART_UARTCR_RTSEN_Pos) -#define UART_UARTCR_RTSEN UART_UARTCR_RTSEN_Msk -#define UART_UARTCR_OUT2_Pos 13U -#define UART_UARTCR_OUT2_Msk (1U << UART_UARTCR_OUT2_Pos) -#define UART_UARTCR_OUT2 UART_UARTCR_OUT2_Msk -#define UART_UARTCR_OUT1_Pos 12U -#define UART_UARTCR_OUT1_Msk (1U << UART_UARTCR_OUT1_Pos) -#define UART_UARTCR_OUT1 UART_UARTCR_OUT1_Msk -#define UART_UARTCR_RTS_Pos 11U -#define UART_UARTCR_RTS_Msk (1U << UART_UARTCR_RTS_Pos) -#define UART_UARTCR_RTS UART_UARTCR_RTS_Msk -#define UART_UARTCR_DTR_Pos 10U -#define UART_UARTCR_DTR_Msk (1U << UART_UARTCR_DTR_Pos) -#define UART_UARTCR_DTR UART_UARTCR_DTR_Msk -#define UART_UARTCR_RXE_Pos 9U -#define UART_UARTCR_RXE_Msk (1U << UART_UARTCR_RXE_Pos) -#define UART_UARTCR_RXE UART_UARTCR_RXE_Msk -#define UART_UARTCR_TXE_Pos 8U -#define UART_UARTCR_TXE_Msk (1U << UART_UARTCR_TXE_Pos) -#define UART_UARTCR_TXE UART_UARTCR_TXE_Msk -#define UART_UARTCR_LBE_Pos 7U -#define UART_UARTCR_LBE_Msk (1U << UART_UARTCR_LBE_Pos) -#define UART_UARTCR_LBE UART_UARTCR_LBE_Msk -#define UART_UARTCR_SIRLP_Pos 2U -#define UART_UARTCR_SIRLP_Msk (1U << UART_UARTCR_SIRLP_Pos) -#define UART_UARTCR_SIRLP UART_UARTCR_SIRLP_Msk -#define UART_UARTCR_SIREN_Pos 1U -#define UART_UARTCR_SIREN_Msk (1U << UART_UARTCR_SIREN_Pos) -#define UART_UARTCR_SIREN UART_UARTCR_SIREN_Msk -#define UART_UARTCR_UARTEN_Pos 0U -#define UART_UARTCR_UARTEN_Msk (1U << UART_UARTCR_UARTEN_Pos) -#define UART_UARTCR_UARTEN UART_UARTCR_UARTEN_Msk +#define UART_UARTCR_CTSEN_Pos 15U +#define UART_UARTCR_CTSEN_Msk (1U << UART_UARTCR_CTSEN_Pos) +#define UART_UARTCR_CTSEN UART_UARTCR_CTSEN_Msk +#define UART_UARTCR_RTSEN_Pos 14U +#define UART_UARTCR_RTSEN_Msk (1U << UART_UARTCR_RTSEN_Pos) +#define UART_UARTCR_RTSEN UART_UARTCR_RTSEN_Msk +#define UART_UARTCR_OUT2_Pos 13U +#define UART_UARTCR_OUT2_Msk (1U << UART_UARTCR_OUT2_Pos) +#define UART_UARTCR_OUT2 UART_UARTCR_OUT2_Msk +#define UART_UARTCR_OUT1_Pos 12U +#define UART_UARTCR_OUT1_Msk (1U << UART_UARTCR_OUT1_Pos) +#define UART_UARTCR_OUT1 UART_UARTCR_OUT1_Msk +#define UART_UARTCR_RTS_Pos 11U +#define UART_UARTCR_RTS_Msk (1U << UART_UARTCR_RTS_Pos) +#define UART_UARTCR_RTS UART_UARTCR_RTS_Msk +#define UART_UARTCR_DTR_Pos 10U +#define UART_UARTCR_DTR_Msk (1U << UART_UARTCR_DTR_Pos) +#define UART_UARTCR_DTR UART_UARTCR_DTR_Msk +#define UART_UARTCR_RXE_Pos 9U +#define UART_UARTCR_RXE_Msk (1U << UART_UARTCR_RXE_Pos) +#define UART_UARTCR_RXE UART_UARTCR_RXE_Msk +#define UART_UARTCR_TXE_Pos 8U +#define UART_UARTCR_TXE_Msk (1U << UART_UARTCR_TXE_Pos) +#define UART_UARTCR_TXE UART_UARTCR_TXE_Msk +#define UART_UARTCR_LBE_Pos 7U +#define UART_UARTCR_LBE_Msk (1U << UART_UARTCR_LBE_Pos) +#define UART_UARTCR_LBE UART_UARTCR_LBE_Msk +#define UART_UARTCR_SIRLP_Pos 2U +#define UART_UARTCR_SIRLP_Msk (1U << UART_UARTCR_SIRLP_Pos) +#define UART_UARTCR_SIRLP UART_UARTCR_SIRLP_Msk +#define UART_UARTCR_SIREN_Pos 1U +#define UART_UARTCR_SIREN_Msk (1U << UART_UARTCR_SIREN_Pos) +#define UART_UARTCR_SIREN UART_UARTCR_SIREN_Msk +#define UART_UARTCR_UARTEN_Pos 0U +#define UART_UARTCR_UARTEN_Msk (1U << UART_UARTCR_UARTEN_Pos) +#define UART_UARTCR_UARTEN UART_UARTCR_UARTEN_Msk -#define UART_UARTIFLS_RXIFLSEL_Pos 3U -#define UART_UARTIFLS_RXIFLSEL_Msk (1U << UART_UARTIFLS_RXIFLSEL_Pos) -#define UART_UARTIFLS_RXIFLSEL(n) ((n) << UART_UARTIFLS_RXIFLSEL_Pos) -#define UART_UARTIFLS_RXIFLSEL_1_8F UART_UARTIFLS_RXIFLSEL(0U) -#define UART_UARTIFLS_RXIFLSEL_1_4F UART_UARTIFLS_RXIFLSEL(1U) -#define UART_UARTIFLS_RXIFLSEL_1_2F UART_UARTIFLS_RXIFLSEL(2U) -#define UART_UARTIFLS_RXIFLSEL_3_4F UART_UARTIFLS_RXIFLSEL(3U) -#define UART_UARTIFLS_RXIFLSEL_7_8F UART_UARTIFLS_RXIFLSEL(4U) +#define UART_UARTIFLS_RXIFLSEL_Pos 3U +#define UART_UARTIFLS_RXIFLSEL_Msk (1U << UART_UARTIFLS_RXIFLSEL_Pos) +#define UART_UARTIFLS_RXIFLSEL(n) ((n) << UART_UARTIFLS_RXIFLSEL_Pos) +#define UART_UARTIFLS_RXIFLSEL_1_8F UART_UARTIFLS_RXIFLSEL(0U) +#define UART_UARTIFLS_RXIFLSEL_1_4F UART_UARTIFLS_RXIFLSEL(1U) +#define UART_UARTIFLS_RXIFLSEL_1_2F UART_UARTIFLS_RXIFLSEL(2U) +#define UART_UARTIFLS_RXIFLSEL_3_4F UART_UARTIFLS_RXIFLSEL(3U) +#define UART_UARTIFLS_RXIFLSEL_7_8F UART_UARTIFLS_RXIFLSEL(4U) -#define UART_UARTIFLS_TXIFLSEL_Pos 3U -#define UART_UARTIFLS_TXIFLSEL_Msk (1U << UART_UARTIFLS_TXIFLSEL_Pos) -#define UART_UARTIFLS_TXIFLSEL(n) ((n) << UART_UARTIFLS_TXIFLSEL_Pos) -#define UART_UARTIFLS_TXIFLSEL_1_8E UART_UARTIFLS_TXIFLSEL(0U) -#define UART_UARTIFLS_TXIFLSEL_1_4E UART_UARTIFLS_TXIFLSEL(1U) -#define UART_UARTIFLS_TXIFLSEL_1_2E UART_UARTIFLS_TXIFLSEL(2U) -#define UART_UARTIFLS_TXIFLSEL_3_4E UART_UARTIFLS_TXIFLSEL(3U) -#define UART_UARTIFLS_TXIFLSEL_7_8E UART_UARTIFLS_TXIFLSEL(4U) +#define UART_UARTIFLS_TXIFLSEL_Pos 3U +#define UART_UARTIFLS_TXIFLSEL_Msk (1U << UART_UARTIFLS_TXIFLSEL_Pos) +#define UART_UARTIFLS_TXIFLSEL(n) ((n) << UART_UARTIFLS_TXIFLSEL_Pos) +#define UART_UARTIFLS_TXIFLSEL_1_8E UART_UARTIFLS_TXIFLSEL(0U) +#define UART_UARTIFLS_TXIFLSEL_1_4E UART_UARTIFLS_TXIFLSEL(1U) +#define UART_UARTIFLS_TXIFLSEL_1_2E UART_UARTIFLS_TXIFLSEL(2U) +#define UART_UARTIFLS_TXIFLSEL_3_4E UART_UARTIFLS_TXIFLSEL(3U) +#define UART_UARTIFLS_TXIFLSEL_7_8E UART_UARTIFLS_TXIFLSEL(4U) -#define UART_UARTIMSC_OEIM_Pos 10U -#define UART_UARTIMSC_OEIM_Msk (1U << UART_UARTIMSC_OEIM_Pos) -#define UART_UARTIMSC_OEIM UART_UARTIMSC_OEIM_Msk -#define UART_UARTIMSC_BEIM_Pos 9U -#define UART_UARTIMSC_BEIM_Msk (1U << UART_UARTIMSC_BEIM_Pos) -#define UART_UARTIMSC_BEIM UART_UARTIMSC_BEIM_Msk -#define UART_UARTIMSC_PEIM_Pos 8U -#define UART_UARTIMSC_PEIM_Msk (1U << UART_UARTIMSC_PEIM_Pos) -#define UART_UARTIMSC_PEIM UART_UARTIMSC_PEIM_Msk -#define UART_UARTIMSC_FEIM_Pos 7U -#define UART_UARTIMSC_FEIM_Msk (1U << UART_UARTIMSC_FEIM_Pos) -#define UART_UARTIMSC_FEIM UART_UARTIMSC_FEIM_Msk -#define UART_UARTIMSC_RTIM_Pos 6U -#define UART_UARTIMSC_RTIM_Msk (1U << UART_UARTIMSC_RTIM_Pos) -#define UART_UARTIMSC_RTIM UART_UARTIMSC_RTIM_Msk -#define UART_UARTIMSC_TXIM_Pos 5U -#define UART_UARTIMSC_TXIM_Msk (1U << UART_UARTIMSC_TXIM_Pos) -#define UART_UARTIMSC_TXIM UART_UARTIMSC_TXIM_Msk -#define UART_UARTIMSC_RXIM_Pos 4U -#define UART_UARTIMSC_RXIM_Msk (1U << UART_UARTIMSC_RXIM_Pos) -#define UART_UARTIMSC_RXIM UART_UARTIMSC_RXIM_Msk -#define UART_UARTIMSC_DSRMIM_Pos 3U -#define UART_UARTIMSC_DSRMIM_Msk (1U << UART_UARTIMSC_DSRMIM_Pos) -#define UART_UARTIMSC_DSRMIM UART_UARTIMSC_DSRMIM_Msk -#define UART_UARTIMSC_DCDMIM_Pos 2U -#define UART_UARTIMSC_DCDMIM_Msk (1U << UART_UARTIMSC_DCDMIM_Pos) -#define UART_UARTIMSC_DCDMIM UART_UARTIMSC_DCDMIM_Msk -#define UART_UARTIMSC_CTSMIM_Pos 1U -#define UART_UARTIMSC_CTSMIM_Msk (1U << UART_UARTIMSC_CTSMIM_Pos) -#define UART_UARTIMSC_CTSMIM UART_UARTIMSC_CTSMIM_Msk -#define UART_UARTIMSC_RIMIM_Pos 0U -#define UART_UARTIMSC_RIMIM_Msk (1U << UART_UARTIMSC_RIMIM_Pos) -#define UART_UARTIMSC_RIMIM UART_UARTIMSC_RIMIM_Msk +#define UART_UARTIMSC_OEIM_Pos 10U +#define UART_UARTIMSC_OEIM_Msk (1U << UART_UARTIMSC_OEIM_Pos) +#define UART_UARTIMSC_OEIM UART_UARTIMSC_OEIM_Msk +#define UART_UARTIMSC_BEIM_Pos 9U +#define UART_UARTIMSC_BEIM_Msk (1U << UART_UARTIMSC_BEIM_Pos) +#define UART_UARTIMSC_BEIM UART_UARTIMSC_BEIM_Msk +#define UART_UARTIMSC_PEIM_Pos 8U +#define UART_UARTIMSC_PEIM_Msk (1U << UART_UARTIMSC_PEIM_Pos) +#define UART_UARTIMSC_PEIM UART_UARTIMSC_PEIM_Msk +#define UART_UARTIMSC_FEIM_Pos 7U +#define UART_UARTIMSC_FEIM_Msk (1U << UART_UARTIMSC_FEIM_Pos) +#define UART_UARTIMSC_FEIM UART_UARTIMSC_FEIM_Msk +#define UART_UARTIMSC_RTIM_Pos 6U +#define UART_UARTIMSC_RTIM_Msk (1U << UART_UARTIMSC_RTIM_Pos) +#define UART_UARTIMSC_RTIM UART_UARTIMSC_RTIM_Msk +#define UART_UARTIMSC_TXIM_Pos 5U +#define UART_UARTIMSC_TXIM_Msk (1U << UART_UARTIMSC_TXIM_Pos) +#define UART_UARTIMSC_TXIM UART_UARTIMSC_TXIM_Msk +#define UART_UARTIMSC_RXIM_Pos 4U +#define UART_UARTIMSC_RXIM_Msk (1U << UART_UARTIMSC_RXIM_Pos) +#define UART_UARTIMSC_RXIM UART_UARTIMSC_RXIM_Msk +#define UART_UARTIMSC_DSRMIM_Pos 3U +#define UART_UARTIMSC_DSRMIM_Msk (1U << UART_UARTIMSC_DSRMIM_Pos) +#define UART_UARTIMSC_DSRMIM UART_UARTIMSC_DSRMIM_Msk +#define UART_UARTIMSC_DCDMIM_Pos 2U +#define UART_UARTIMSC_DCDMIM_Msk (1U << UART_UARTIMSC_DCDMIM_Pos) +#define UART_UARTIMSC_DCDMIM UART_UARTIMSC_DCDMIM_Msk +#define UART_UARTIMSC_CTSMIM_Pos 1U +#define UART_UARTIMSC_CTSMIM_Msk (1U << UART_UARTIMSC_CTSMIM_Pos) +#define UART_UARTIMSC_CTSMIM UART_UARTIMSC_CTSMIM_Msk +#define UART_UARTIMSC_RIMIM_Pos 0U +#define UART_UARTIMSC_RIMIM_Msk (1U << UART_UARTIMSC_RIMIM_Pos) +#define UART_UARTIMSC_RIMIM UART_UARTIMSC_RIMIM_Msk -#define UART_UARTRIS_OERIS_Pos 10U -#define UART_UARTRIS_OERIS_Msk (1U << UART_UARTRIS_OERIS_Pos) -#define UART_UARTRIS_OERIS UART_UARTRIS_OERIS_Msk -#define UART_UARTRIS_BERIS_Pos 9U -#define UART_UARTRIS_BERIS_Msk (1U << UART_UARTRIS_BERIS_Pos) -#define UART_UARTRIS_BERIS UART_UARTRIS_BERIS_Msk -#define UART_UARTRIS_PERIS_Pos 8U -#define UART_UARTRIS_PERIS_Msk (1U << UART_UARTRIS_PERIS_Pos) -#define UART_UARTRIS_PERIS UART_UARTRIS_PERIS_Msk -#define UART_UARTRIS_FERIS_Pos 7U -#define UART_UARTRIS_FERIS_Msk (1U << UART_UARTRIS_FERIS_Pos) -#define UART_UARTRIS_FERIS UART_UARTRIS_FERIS_Msk -#define UART_UARTRIS_RTRIS_Pos 6U -#define UART_UARTRIS_RTRIS_Msk (1U << UART_UARTRIS_RTRIS_Pos) -#define UART_UARTRIS_RTRIS UART_UARTRIS_RTRIS_Msk -#define UART_UARTRIS_TXRIS_Pos 5U -#define UART_UARTRIS_TXRIS_Msk (1U << UART_UARTRIS_TXRIS_Pos) -#define UART_UARTRIS_TXRIS UART_UARTRIS_TXRIS_Msk -#define UART_UARTRIS_RXRIS_Pos 4U -#define UART_UARTRIS_RXRIS_Msk (1U << UART_UARTRIS_RXRIS_Pos) -#define UART_UARTRIS_RXRIS UART_UARTRIS_RXRIS_Msk -#define UART_UARTRIS_DSRRMIS_Pos 3U -#define UART_UARTRIS_DSRRMIS_Msk (1U << UART_UARTRIS_DSRRMIS_Pos) -#define UART_UARTRIS_DSRRMIS UART_UARTRIS_DSRRMIS_Msk -#define UART_UARTRIS_DCDRMIS_Pos 2U -#define UART_UARTRIS_DCDRMIS_Msk (1U << UART_UARTRIS_DCDRMIS_Pos) -#define UART_UARTRIS_DCDRMIS UART_UARTRIS_DCDRMIS_Msk -#define UART_UARTRIS_CTSRMIS_Pos 1U -#define UART_UARTRIS_CTSRMIS_Msk (1U << UART_UARTRIS_CTSRMIS_Pos) -#define UART_UARTRIS_CTSRMIS UART_UARTRIS_CTSRMIS_Msk -#define UART_UARTRIS_RIRMIS_Pos 0U -#define UART_UARTRIS_RIRMIS_Msk (1U << UART_UARTRIS_RIRMIS_Pos) -#define UART_UARTRIS_RIRMIS UART_UARTIMSC_RIRMIS_Msk +#define UART_UARTRIS_OERIS_Pos 10U +#define UART_UARTRIS_OERIS_Msk (1U << UART_UARTRIS_OERIS_Pos) +#define UART_UARTRIS_OERIS UART_UARTRIS_OERIS_Msk +#define UART_UARTRIS_BERIS_Pos 9U +#define UART_UARTRIS_BERIS_Msk (1U << UART_UARTRIS_BERIS_Pos) +#define UART_UARTRIS_BERIS UART_UARTRIS_BERIS_Msk +#define UART_UARTRIS_PERIS_Pos 8U +#define UART_UARTRIS_PERIS_Msk (1U << UART_UARTRIS_PERIS_Pos) +#define UART_UARTRIS_PERIS UART_UARTRIS_PERIS_Msk +#define UART_UARTRIS_FERIS_Pos 7U +#define UART_UARTRIS_FERIS_Msk (1U << UART_UARTRIS_FERIS_Pos) +#define UART_UARTRIS_FERIS UART_UARTRIS_FERIS_Msk +#define UART_UARTRIS_RTRIS_Pos 6U +#define UART_UARTRIS_RTRIS_Msk (1U << UART_UARTRIS_RTRIS_Pos) +#define UART_UARTRIS_RTRIS UART_UARTRIS_RTRIS_Msk +#define UART_UARTRIS_TXRIS_Pos 5U +#define UART_UARTRIS_TXRIS_Msk (1U << UART_UARTRIS_TXRIS_Pos) +#define UART_UARTRIS_TXRIS UART_UARTRIS_TXRIS_Msk +#define UART_UARTRIS_RXRIS_Pos 4U +#define UART_UARTRIS_RXRIS_Msk (1U << UART_UARTRIS_RXRIS_Pos) +#define UART_UARTRIS_RXRIS UART_UARTRIS_RXRIS_Msk +#define UART_UARTRIS_DSRRMIS_Pos 3U +#define UART_UARTRIS_DSRRMIS_Msk (1U << UART_UARTRIS_DSRRMIS_Pos) +#define UART_UARTRIS_DSRRMIS UART_UARTRIS_DSRRMIS_Msk +#define UART_UARTRIS_DCDRMIS_Pos 2U +#define UART_UARTRIS_DCDRMIS_Msk (1U << UART_UARTRIS_DCDRMIS_Pos) +#define UART_UARTRIS_DCDRMIS UART_UARTRIS_DCDRMIS_Msk +#define UART_UARTRIS_CTSRMIS_Pos 1U +#define UART_UARTRIS_CTSRMIS_Msk (1U << UART_UARTRIS_CTSRMIS_Pos) +#define UART_UARTRIS_CTSRMIS UART_UARTRIS_CTSRMIS_Msk +#define UART_UARTRIS_RIRMIS_Pos 0U +#define UART_UARTRIS_RIRMIS_Msk (1U << UART_UARTRIS_RIRMIS_Pos) +#define UART_UARTRIS_RIRMIS UART_UARTIMSC_RIRMIS_Msk -#define UART_UARTMIS_OEMIS_Pos 10U -#define UART_UARTMIS_OEMIS_Msk (1U << UART_UARTMIS_OEMIS_Pos) -#define UART_UARTMIS_OEMIS UART_UARTMIS_OEMIS_Msk -#define UART_UARTMIS_BEMIS_Pos 9U -#define UART_UARTMIS_BEMIS_Msk (1U << UART_UARTMIS_BEMIS_Pos) -#define UART_UARTMIS_BEMIS UART_UARTMIS_BEMIS_Msk -#define UART_UARTMIS_PEMIS_Pos 8U -#define UART_UARTMIS_PEMIS_Msk (1U << UART_UARTMIS_PEMIS_Pos) -#define UART_UARTMIS_PEMIS UART_UARTMIS_PEMIS_Msk -#define UART_UARTMIS_FEMIS_Pos 7U -#define UART_UARTMIS_FEMIS_Msk (1U << UART_UARTMIS_FEMIS_Pos) -#define UART_UARTMIS_FEMIS UART_UARTMIS_FEMIS_Msk -#define UART_UARTMIS_RTMIS_Pos 6U -#define UART_UARTMIS_RTMIS_Msk (1U << UART_UARTMIS_RTMIS_Pos) -#define UART_UARTMIS_RTMIS UART_UARTMIS_RTMIS_Msk -#define UART_UARTMIS_TXMIS_Pos 5U -#define UART_UARTMIS_TXMIS_Msk (1U << UART_UARTMIS_TXMIS_Pos) -#define UART_UARTMIS_TXMIS UART_UARTMIS_TXMIS_Msk -#define UART_UARTMIS_RXMIS_Pos 4U -#define UART_UARTMIS_RXMIS_Msk (1U << UART_UARTMIS_RXMIS_Pos) -#define UART_UARTMIS_RXMIS UART_UARTMIS_RXMIS_Msk -#define UART_UARTMIS_DSRMMIS_Pos 3U -#define UART_UARTMIS_DSRMMIS_Msk (1U << UART_UARTMIS_DSRMMIS_Pos) -#define UART_UARTMIS_DSRRMIS UART_UARTMIS_DSRMMIS_Msk -#define UART_UARTMIS_DCDMMIS_Pos 2U -#define UART_UARTMIS_DCDMMIS_Msk (1U << UART_UARTMIS_DCDMMIS_Pos) -#define UART_UARTMIS_DCDMMIS UART_UARTMIS_DCDMMIS_Msk -#define UART_UARTMIS_CTSMMIS_Pos 1U -#define UART_UARTMIS_CTSMMIS_Msk (1U << UART_UARTMIS_CTSMMIS_Pos) -#define UART_UARTMIS_CTSMMIS UART_UARTMIS_CTSMMIS_Msk -#define UART_UARTMIS_RIMMIS_Pos 0U -#define UART_UARTMIS_RIMMIS_Msk (1U << UART_UARTMIS_RIMMIS_Pos) -#define UART_UARTMIS_RIMMIS UART_UARTIMSC_RIMMIS_Msk +#define UART_UARTMIS_OEMIS_Pos 10U +#define UART_UARTMIS_OEMIS_Msk (1U << UART_UARTMIS_OEMIS_Pos) +#define UART_UARTMIS_OEMIS UART_UARTMIS_OEMIS_Msk +#define UART_UARTMIS_BEMIS_Pos 9U +#define UART_UARTMIS_BEMIS_Msk (1U << UART_UARTMIS_BEMIS_Pos) +#define UART_UARTMIS_BEMIS UART_UARTMIS_BEMIS_Msk +#define UART_UARTMIS_PEMIS_Pos 8U +#define UART_UARTMIS_PEMIS_Msk (1U << UART_UARTMIS_PEMIS_Pos) +#define UART_UARTMIS_PEMIS UART_UARTMIS_PEMIS_Msk +#define UART_UARTMIS_FEMIS_Pos 7U +#define UART_UARTMIS_FEMIS_Msk (1U << UART_UARTMIS_FEMIS_Pos) +#define UART_UARTMIS_FEMIS UART_UARTMIS_FEMIS_Msk +#define UART_UARTMIS_RTMIS_Pos 6U +#define UART_UARTMIS_RTMIS_Msk (1U << UART_UARTMIS_RTMIS_Pos) +#define UART_UARTMIS_RTMIS UART_UARTMIS_RTMIS_Msk +#define UART_UARTMIS_TXMIS_Pos 5U +#define UART_UARTMIS_TXMIS_Msk (1U << UART_UARTMIS_TXMIS_Pos) +#define UART_UARTMIS_TXMIS UART_UARTMIS_TXMIS_Msk +#define UART_UARTMIS_RXMIS_Pos 4U +#define UART_UARTMIS_RXMIS_Msk (1U << UART_UARTMIS_RXMIS_Pos) +#define UART_UARTMIS_RXMIS UART_UARTMIS_RXMIS_Msk +#define UART_UARTMIS_DSRMMIS_Pos 3U +#define UART_UARTMIS_DSRMMIS_Msk (1U << UART_UARTMIS_DSRMMIS_Pos) +#define UART_UARTMIS_DSRRMIS UART_UARTMIS_DSRMMIS_Msk +#define UART_UARTMIS_DCDMMIS_Pos 2U +#define UART_UARTMIS_DCDMMIS_Msk (1U << UART_UARTMIS_DCDMMIS_Pos) +#define UART_UARTMIS_DCDMMIS UART_UARTMIS_DCDMMIS_Msk +#define UART_UARTMIS_CTSMMIS_Pos 1U +#define UART_UARTMIS_CTSMMIS_Msk (1U << UART_UARTMIS_CTSMMIS_Pos) +#define UART_UARTMIS_CTSMMIS UART_UARTMIS_CTSMMIS_Msk +#define UART_UARTMIS_RIMMIS_Pos 0U +#define UART_UARTMIS_RIMMIS_Msk (1U << UART_UARTMIS_RIMMIS_Pos) +#define UART_UARTMIS_RIMMIS UART_UARTIMSC_RIMMIS_Msk -#define UART_UARTICR_OEIC_Pos 10U -#define UART_UARTICR_OEIC_Msk (1U << UART_UARTICR_OEIC_Pos) -#define UART_UARTICR_OEIC UART_UARTICR_OEIC_Msk -#define UART_UARTICR_BEIC_Pos 9U -#define UART_UARTICR_BEIC_Msk (1U << UART_UARTICR_BEIC_Pos) -#define UART_UARTICR_BEIC UART_UARTICR_BEIC_Msk -#define UART_UARTICR_PEIC_Pos 8U -#define UART_UARTICR_PEIC_Msk (1U << UART_UARTICR_PEIC_Pos) -#define UART_UARTICR_PEIC UART_UARTICR_PEIC_Msk -#define UART_UARTICR_FEIC_Pos 7U -#define UART_UARTICR_FEIC_Msk (1U << UART_UARTICR_FEIC_Pos) -#define UART_UARTICR_FEIC UART_UARTICR_FEIC_Msk -#define UART_UARTICR_RTIC_Pos 6U -#define UART_UARTICR_RTIC_Msk (1U << UART_UARTICR_RTIC_Pos) -#define UART_UARTICR_RTIC UART_UARTICR_RTIC_Msk -#define UART_UARTICR_TXIC_Pos 5U -#define UART_UARTICR_TXIC_Msk (1U << UART_UARTICR_TXIC_Pos) -#define UART_UARTICR_TXIC UART_UARTICR_TXIC_Msk -#define UART_UARTICR_RXIC_Pos 4U -#define UART_UARTICR_RXIC_Msk (1U << UART_UARTICR_RXIC_Pos) -#define UART_UARTICR_RXIC UART_UARTICR_RXIC_Msk -#define UART_UARTICR_DSRMIC_Pos 3U -#define UART_UARTICR_DSRMIC_Msk (1U << UART_UARTICR_DSRMIC_Pos) -#define UART_UARTICR_DSRMIC UART_UARTICR_DSRMIC_Msk -#define UART_UARTICR_DCDMIC_Pos 2U -#define UART_UARTICR_DCDMIC_Msk (1U << UART_UARTICR_DCDMIC_Pos) -#define UART_UARTICR_DCDMIC UART_UARTICR_DCDMIC_Msk -#define UART_UARTICR_CTSMIC_Pos 1U -#define UART_UARTICR_CTSMIC_Msk (1U << UART_UARTICR_CTSMIC_Pos) -#define UART_UARTICR_CTSMIC UART_UARTICR_CTSMIC_Msk -#define UART_UARTICR_RIMIC_Pos 0U -#define UART_UARTICR_RIMIC_Msk (1U << UART_UARTICR_RIMIC_Pos) -#define UART_UARTICR_RIMIC UART_UARTICR_RIMIC_Msk +#define UART_UARTICR_OEIC_Pos 10U +#define UART_UARTICR_OEIC_Msk (1U << UART_UARTICR_OEIC_Pos) +#define UART_UARTICR_OEIC UART_UARTICR_OEIC_Msk +#define UART_UARTICR_BEIC_Pos 9U +#define UART_UARTICR_BEIC_Msk (1U << UART_UARTICR_BEIC_Pos) +#define UART_UARTICR_BEIC UART_UARTICR_BEIC_Msk +#define UART_UARTICR_PEIC_Pos 8U +#define UART_UARTICR_PEIC_Msk (1U << UART_UARTICR_PEIC_Pos) +#define UART_UARTICR_PEIC UART_UARTICR_PEIC_Msk +#define UART_UARTICR_FEIC_Pos 7U +#define UART_UARTICR_FEIC_Msk (1U << UART_UARTICR_FEIC_Pos) +#define UART_UARTICR_FEIC UART_UARTICR_FEIC_Msk +#define UART_UARTICR_RTIC_Pos 6U +#define UART_UARTICR_RTIC_Msk (1U << UART_UARTICR_RTIC_Pos) +#define UART_UARTICR_RTIC UART_UARTICR_RTIC_Msk +#define UART_UARTICR_TXIC_Pos 5U +#define UART_UARTICR_TXIC_Msk (1U << UART_UARTICR_TXIC_Pos) +#define UART_UARTICR_TXIC UART_UARTICR_TXIC_Msk +#define UART_UARTICR_RXIC_Pos 4U +#define UART_UARTICR_RXIC_Msk (1U << UART_UARTICR_RXIC_Pos) +#define UART_UARTICR_RXIC UART_UARTICR_RXIC_Msk +#define UART_UARTICR_DSRMIC_Pos 3U +#define UART_UARTICR_DSRMIC_Msk (1U << UART_UARTICR_DSRMIC_Pos) +#define UART_UARTICR_DSRMIC UART_UARTICR_DSRMIC_Msk +#define UART_UARTICR_DCDMIC_Pos 2U +#define UART_UARTICR_DCDMIC_Msk (1U << UART_UARTICR_DCDMIC_Pos) +#define UART_UARTICR_DCDMIC UART_UARTICR_DCDMIC_Msk +#define UART_UARTICR_CTSMIC_Pos 1U +#define UART_UARTICR_CTSMIC_Msk (1U << UART_UARTICR_CTSMIC_Pos) +#define UART_UARTICR_CTSMIC UART_UARTICR_CTSMIC_Msk +#define UART_UARTICR_RIMIC_Pos 0U +#define UART_UARTICR_RIMIC_Msk (1U << UART_UARTICR_RIMIC_Pos) +#define UART_UARTICR_RIMIC UART_UARTICR_RIMIC_Msk -#define UART_UARTDMACR_DMAONERR_Pos 2U -#define UART_UARTDMACR_DMAONERR_Msk (1U << UART_UARTDMACR_DMAONERR_Pos) -#define UART_UARTDMACR_DMAONERR UART_UARTDMACR_DMAONERR_Msk -#define UART_UARTDMACR_TXDMAE_Pos 1U -#define UART_UARTDMACR_TXDMAE_Msk (1U << UART_UARTDMACR_TXDMAE_Pos) -#define UART_UARTDMACR_TXDMAE UART_UARTDMACR_TXDMAE_Msk -#define UART_UARTDMACR_RXDMAE_Pos 0U -#define UART_UARTDMACR_RXDMAE_Msk (1U << UART_UARTDMACR_RXDMAE_Pos) -#define UART_UARTDMACR_RXDMAE UART_UARTDMACR_RXDMAE_Msk +#define UART_UARTDMACR_DMAONERR_Pos 2U +#define UART_UARTDMACR_DMAONERR_Msk (1U << UART_UARTDMACR_DMAONERR_Pos) +#define UART_UARTDMACR_DMAONERR UART_UARTDMACR_DMAONERR_Msk +#define UART_UARTDMACR_TXDMAE_Pos 1U +#define UART_UARTDMACR_TXDMAE_Msk (1U << UART_UARTDMACR_TXDMAE_Pos) +#define UART_UARTDMACR_TXDMAE UART_UARTDMACR_TXDMAE_Msk +#define UART_UARTDMACR_RXDMAE_Pos 0U +#define UART_UARTDMACR_RXDMAE_Msk (1U << UART_UARTDMACR_RXDMAE_Pos) +#define UART_UARTDMACR_RXDMAE UART_UARTDMACR_RXDMAE_Msk +/** @} */ + +/** + * @name RTC bits definitions + * @{ + */ +#define RTC_CLKDIV_M1_Pos 0U +#define RTC_CLKDIV_M1_Msk (0xFFFFU << RTC_CLKDIV_M1_Pos) +#define RTC_CLKDIV_M1 RTC_CLKDIV_M1_Msk + +#define RTC_SETUP_0_YEAR_Pos 12U +#define RTC_SETUP_0_YEAR_Msk (0xFFFU << RTC_SETUP_0_YEAR_Pos) +#define RTC_SETUP_0_YEAR(n) ((n) << RTC_SETUP_0_YEAR_Pos) +#define RTC_SETUP_0_MONTH_Pos 8U +#define RTC_SETUP_0_MONTH_Msk (0xFU << RTC_SETUP_0_MONTH_Pos) +#define RTC_SETUP_0_MONTH(n) ((n) << RTC_SETUP_0_MONTH_Pos) +#define RTC_SETUP_0_DAY_Pos 4U +#define RTC_SETUP_0_DAY_Msk (0x1FU << RTC_SETUP_0_DAY_Pos) +#define RTC_SETUP_0_DAY(n) ((n) << RTC_SETUP_0_DAY_Pos) + +#define RTC_SETUP_1_DOTW_Pos 24U +#define RTC_SETUP_1_DOTW_Msk (0x7U << RTC_SETUP_1_DOTW_Pos) +#define RTC_SETUP_1_DOTW(n) ((n) << RTC_SETUP_1_DOTW_Pos) +#define RTC_SETUP_1_HOUR_Pos 16U +#define RTC_SETUP_1_HOUR_Msk (0x1FU << RTC_SETUP_1_HOUR_Pos) +#define RTC_SETUP_1_HOUR(n) ((n) << RTC_SETUP_1_HOUR_Pos) +#define RTC_SETUP_1_MIN_Pos 8U +#define RTC_SETUP_1_MIN_Msk (0x3FU << RTC_SETUP_1_MIN_Pos) +#define RTC_SETUP_1_MIN(n) ((n) << RTC_SETUP_1_MIN_Pos) +#define RTC_SETUP_1_SEC_Pos 0U +#define RTC_SETUP_1_SEC_Msk (0x3FU << RTC_SETUP_1_SEC_Pos) +#define RTC_SETUP_1_SEC(n) ((n) << RTC_SETUP_1_SEC_Pos) + +#define RTC_CTRL_FORCE_NOTLEAPYEAR_Pos 8U +#define RTC_CTRL_FORCE_NOTLEAPYEAR_Msk (1U << RTC_CTRL_FORCE_NOTLEAPYEAR_Pos) +#define RTC_CTRL_FORCE_NOTLEAPYEAR RTC_CTRL_FORCE_NOTLEAPYEAR_Msk + +#define RTC_CTRL_LOAD_Pos 4U +#define RTC_CTRL_LOAD_Msk (1U << RTC_CTRL_LOAD_Pos) +#define RTC_CTRL_LOAD RTC_CTRL_LOAD_Msk + +#define RTC_CTRL_RTC_ACTIVE_Pos 1U +#define RTC_CTRL_RTC_ACTIVE_Msk (1U << RTC_CTRL_RTC_ACTIVE_Pos) +#define RTC_CTRL_RTC_ACTIVE RTC_CTRL_RTC_ACTIVE_Msk + +#define RTC_CTRL_RTC_ENABLE_Pos 0U +#define RTC_CTRL_RTC_ENABLE_Msk (1U << RTC_CTRL_RTC_ENABLE_Pos) +#define RTC_CTRL_RTC_ENABLE RTC_CTRL_RTC_ENABLE_Msk + +#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_Pos 29U +#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_Msk (1U << RTC_IRQ_SETUP_0_MATCH_ACTIVE_Pos) +#define RTC_IRQ_SETUP_0_MATCH_ACTIVE RTC_IRQ_SETUP_0_MATCH_ACTIVE_Msk +#define RTC_IRQ_SETUP_0_MATCH_ENA_Pos 28U +#define RTC_IRQ_SETUP_0_MATCH_ENA_Msk (1U << RTC_IRQ_SETUP_0_MATCH_ENA_Pos) +#define RTC_IRQ_SETUP_0_MATCH_ENA RTC_IRQ_SETUP_0_MATCH_ENA_Msk +#define RTC_IRQ_SETUP_0_YEAR_ENA_Pos 26U +#define RTC_IRQ_SETUP_0_YEAR_ENA_Msk (1U << RTC_IRQ_SETUP_0_YEAR_ENA_Pos) +#define RTC_IRQ_SETUP_0_YEAR_ENA RTC_IRQ_SETUP_0_YEAR_ENA_Msk +#define RTC_IRQ_SETUP_0_MONTH_ENA_Pos 25U +#define RTC_IRQ_SETUP_0_MONTH_ENA_Msk (1U << RTC_IRQ_SETUP_0_MONTH_ENA_Pos) +#define RTC_IRQ_SETUP_0_MONTH_ENA RTC_IRQ_SETUP_0_MONTH_ENA_Msk +#define RTC_IRQ_SETUP_0_DAY_ENA_Pos 24U +#define RTC_IRQ_SETUP_0_DAY_ENA_Msk (1U << RTC_IRQ_SETUP_0_DAY_ENA_Pos) +#define RTC_IRQ_SETUP_0_DAY_ENA RTC_IRQ_SETUP_0_DAY_ENA_Msk + +#define RTC_IRQ_SETUP_0_YEAR_Pos 12U +#define RTC_IRQ_SETUP_0_YEAR_Msk (0xFFFU << RTC_IRQ_SETUP_0_YEAR_Pos) +#define RTC_IRQ_SETUP_0_YEAR(n) ((n) << RTC_IRQ_SETUP_0_YEAR_Pos) +#define RTC_IRQ_SETUP_0_MONTH_Pos 8U +#define RTC_IRQ_SETUP_0_MONTH_Msk (0xFU << RTC_IRQ_SETUP_0_MONTH_Pos) +#define RTC_IRQ_SETUP_0_MONTH(n) ((n) << RTC_IRQ_SETUP_0_MONTH_Pos) +#define RTC_IRQ_SETUP_0_DAY_Pos 4U +#define RTC_IRQ_SETUP_0_DAY_Msk (0x1FU << RTC_IRQ_SETUP_0_DAY_Pos) +#define RTC_IRQ_SETUP_0_DAY(n) ((n) << RTC_IRQ_SETUP_0_DAY_Pos) + +#define RTC_IRQ_SETUP_1_DOTW_ENA_Pos 31U +#define RTC_IRQ_SETUP_1_DOTW_ENA_Msk (1U << RTC_IRQ_SETUP_1_DOTW_ENA_Pos) +#define RTC_IRQ_SETUP_1_DOTW_ENA RTC_IRQ_SETUP_1_DOTW_ENA_Msk +#define RTC_IRQ_SETUP_1_HOUR_ENA_Pos 30U +#define RTC_IRQ_SETUP_1_HOUR_ENA_Msk (1U << RTC_IRQ_SETUP_1_HOUR_ENA_Pos) +#define RTC_IRQ_SETUP_1_HOUR_ENA RTC_IRQ_SETUP_1_HOUR_ENA_Msk +#define RTC_IRQ_SETUP_1_MIN_ENA_Pos 29U +#define RTC_IRQ_SETUP_1_MIN_ENA_Msk (1U << RTC_IRQ_SETUP_1_MIN_ENA_Pos) +#define RTC_IRQ_SETUP_1_MIN_ENA RTC_IRQ_SETUP_1_MIN_ENA_Msk +#define RTC_IRQ_SETUP_1_SEC_ENA_Pos 28U +#define RTC_IRQ_SETUP_1_SEC_ENA_Msk (1U << RTC_IRQ_SETUP_1_SEC_ENA_Pos) +#define RTC_IRQ_SETUP_1_SEC_ENA RTC_IRQ_SETUP_1_SEC_ENA_Msk + +#define RTC_IRQ_SETUP_1_DOTW_Pos 24U +#define RTC_IRQ_SETUP_1_DOTW_Msk (0x7U << RTC_IRQ_SETUP_1_DOTW_Pos) +#define RTC_IRQ_SETUP_1_DOTW(n) ((n) << RTC_IRQ_SETUP_1_DOTW_Pos) +#define RTC_IRQ_SETUP_1_HOUR_Pos 16U +#define RTC_IRQ_SETUP_1_HOUR_Msk (0x1FU << RTC_IRQ_SETUP_1_HOUR_Pos) +#define RTC_IRQ_SETUP_1_HOUR(n) ((n) << RTC_IRQ_SETUP_1_HOUR_Pos) +#define RTC_IRQ_SETUP_1_MIN_Pos 8U +#define RTC_IRQ_SETUP_1_MIN_Msk (0x3FU << RTC_IRQ_SETUP_1_MIN_Pos) +#define RTC_IRQ_SETUP_1_MIN(n) ((n) << RTC_IRQ_SETUP_1_MIN_Pos) +#define RTC_IRQ_SETUP_1_SEC_Pos 0U +#define RTC_IRQ_SETUP_1_SEC_Msk (0x3FU << RTC_IRQ_SETUP_1_SEC_Pos) +#define RTC_IRQ_SETUP_1_SEC(n) ((n) << RTC_IRQ_SETUP_1_SEC_Pos) + +#define RTC_INTR_RTC_Pos 0U +#define RTC_INTR_RTC_Msk (1U << RTC_INTR_RTC_Pos) +#define RTC_INTR_RTC RTC_INTR_RTC_Msk + +#define RTC_INTE_RTC_Pos 0U +#define RTC_INTE_RTC_Msk (1U << RTC_INTE_RTC_Pos) +#define RTC_INTE_RTC RTC_INTE_RTC_Msk + +#define RTC_INTF_RTC_Pos 0U +#define RTC_INTF_RTC_Msk (1U << RTC_INTF_RTC_Pos) +#define RTC_INTF_RTC RTC_INTF_RTC_Msk + +#define RTC_INTS_RTC_Pos 0U +#define RTC_INTS_RTC_Msk (1U << RTC_INTS_RTC_Pos) +#define RTC_INTS_RTC RTC_INTS_RTC_Msk + +/* Normalisation of RTC0 & RTC1 fields read from RTC. */ +#define RTC_RTC_1_YEAR_Pos 12U +#define RTC_RTC_1_YEAR_Msk (0xFFFU << RTC_RTC_1_YEAR_Pos) +#define RTC_RTC_1_YEAR(n) ((n & RTC_RTC_1_YEAR_Msk) >> \ + RTC_RTC_1_YEAR_Pos) +#define RTC_RTC_1_MONTH_Pos 8U +#define RTC_RTC_1_MONTH_Msk (0xFU << RTC_RTC_1_MONTH_Pos) +#define RTC_RTC_1_MONTH(n) ((n & RTC_RTC_1_MONTH_Msk) >> \ + RTC_RTC_1_DAY_Pos) +#define RTC_RTC_1_DAY_Pos 0U +#define RTC_RTC_1_DAY_Msk (0x1FU << RTC_RTC_1_DAY_Pos) +#define RTC_RTC_1_DAY(n) ((n & RTC_RTC_1_DAY_Msk) >> \ + RTC_RTC_1_DAY_Pos) +#define RTC_RTC_0_DOTW_Pos 24U +#define RTC_RTC_0_DOTW_Msk (0x7U << RTC_RTC_0_DOTW_Pos) +#define RTC_RTC_0_DOTW(n) ((n & RTC_RTC_0_DOTW_Msk) >> \ + RTC_RTC_0_DOTW_Pos) +#define RTC_RTC_0_HOUR_Pos 16U +#define RTC_RTC_0_HOUR_Msk (0x1FU << RTC_RTC_0_HOUR_Pos) +#define RTC_RTC_0_HOUR(n) ((n & RTC_RTC_0_HOUR_Msk) >> \ + RTC_RTC_0_HOUR_Pos) +#define RTC_RTC_0_MIN_Pos 8U +#define RTC_RTC_0_MIN_Msk (0x3FU << RTC_RTC_0_MIN_Pos) +#define RTC_RTC_0_MIN(n) ((n & RTC_RTC_0_MIN_Msk) >> \ + RTC_RTC_0_MIN_Pos) +#define RTC_RTC_0_SEC_Pos 0U +#define RTC_RTC_0_SEC_Msk (0x3FU << RTC_RTC_0_SEC_Pos) +#define RTC_RTC_0_SEC(n) ((n & RTC_RTC_0_SEC_Msk) >> \ + RTC_RTC_0_SEC_Pos) /** @} */ #ifdef __cplusplus diff --git a/os/hal/ports/RP/LLD/RTCv1/hal_rtc_lld.c b/os/hal/ports/RP/LLD/RTCv1/hal_rtc_lld.c index 780ba877b..3b986c42b 100644 --- a/os/hal/ports/RP/LLD/RTCv1/hal_rtc_lld.c +++ b/os/hal/ports/RP/LLD/RTCv1/hal_rtc_lld.c @@ -48,6 +48,20 @@ RTCDriver RTCD1; /* Driver local functions. */ /*===========================================================================*/ +static void rtc_enable_alarm(RTCDriver *rtcp) { + /* Enable matching and wait for it to be activated. */ + rtcp->rtc->IRQSETUP0 |= RTC_IRQ_SETUP_0_MATCH_ENA; + while (!(rtcp->rtc->IRQSETUP0 & RTC_IRQ_SETUP_0_MATCH_ACTIVE)) + ; +} + +static void rtc_disable_alarm(RTCDriver *rtcp) { + /* Disable alarm matching and wait until deactivated. */ + rtcp->rtc->IRQSETUP0 &= ~RTC_IRQ_SETUP_0_MATCH_ENA; + while (rtcp->rtc->IRQSETUP0 & RTC_IRQ_SETUP_0_MATCH_ACTIVE) + ; +} + /*===========================================================================*/ /* Driver interrupt handlers. */ /*===========================================================================*/ @@ -107,33 +121,31 @@ void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec) { rtcp->rtc->CTRL = 0; /* Wait for RTC to go inactive. */ - while ((rtcp->rtc->CTRL & RTC_CTRL_RTC_ACTIVE_BITS) != 0) + while ((rtcp->rtc->CTRL & RTC_CTRL_RTC_ACTIVE) != 0) ; /* Entering a reentrant critical zone.*/ syssts_t sts = osalSysGetStatusAndLockX(); /* Write setup to pre-load registers. */ - rtcp->rtc->SETUP0 = - ((timespec->year + 1980) << RTC_SETUP_0_YEAR_LSB) | - (timespec->month << RTC_SETUP_0_MONTH_LSB) | - (timespec->day << RTC_SETUP_0_DAY_LSB); - rtcp->rtc->SETUP1 = - ((timespec->dayofweek - 1) << RTC_SETUP_1_DOTW_LSB) | - (hour << RTC_SETUP_1_HOUR_LSB) | - (min << RTC_SETUP_1_MIN_LSB) | - (sec << RTC_SETUP_1_SEC_LSB); + rtcp->rtc->SETUP0 = (RTC_SETUP_0_YEAR(timespec->year + 1980)) | + (RTC_SETUP_0_MONTH(timespec->month)) | + (RTC_SETUP_0_DAY(timespec->day)); + rtcp->rtc->SETUP1 = (RTC_SETUP_1_DOTW(timespec->dayofweek - 1)) | + (RTC_SETUP_1_HOUR(hour)) | + (RTC_SETUP_1_MIN(min)) | + (RTC_SETUP_1_SEC(sec); /* Move setup values into RTC clock domain. */ - rtcp->rtc->CTRL = RTC_CTRL_LOAD_BITS; + rtcp->rtc->CTRL = RTC_CTRL_LOAD; /* Enable RTC and wait for active. */ - rtcp->rtc->CTRL = RTC_CTRL_RTC_ENABLE_BITS; + rtcp->rtc->CTRL = RTC_CTRL_RTC_ENABLE; /* Leaving a reentrant critical zone.*/ osalSysRestoreStatusX(sts); - while ((rtcp->rtc->CTRL & RTC_CTRL_RTC_ACTIVE_BITS) == 0) + while ((rtcp->rtc->CTRL & RTC_CTRL_RTC_ACTIVE) == 0) ; } @@ -159,20 +171,15 @@ void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec) { osalSysRestoreStatusX(sts); /* Calculate and set milliseconds since midnight field. */ - timespec->millisecond = - ((((rtc_0 & RTC_RTC_0_HOUR_BITS) >> RTC_RTC_0_HOUR_LSB) * 3600) - + (((rtc_0 & RTC_RTC_0_MIN_BITS) >> RTC_RTC_0_MIN_LSB) * 60) - + (((rtc_0 & RTC_RTC_0_SEC_BITS) >> RTC_RTC_0_SEC_LSB))) * 1000; + timespec->millisecond = (RTC_RTC_0_HOUR(rtc_0) * 3600) + + (RTC_RTC_0_MIN(rtc_0) * 60) + + (RTC_RTC_0_SEC(rtc_0) * 1000); - /* Set fields with adjustments. */ - timespec->dayofweek = - ((rtc_0 & RTC_RTC_0_DOTW_BITS) >> RTC_RTC_0_DOTW_LSB) + 1; - timespec->year = - ((rtc_1 & RTC_RTC_1_YEAR_BITS) >> RTC_RTC_1_YEAR_LSB) - 1980; - timespec->month = - ((rtc_1 & RTC_RTC_1_MONTH_BITS) >> RTC_RTC_1_MONTH_LSB); - timespec->day = - ((rtc_1 & RTC_RTC_1_DAY_BITS) >> RTC_RTC_1_DAY_LSB); + /* Set RTCDateTime fields with adjustments from RTC data. */ + timespec->dayofweek = RTC_RTC_0_DOTW(rtc_0) + 1; + timespec->year = RTC_RTC_1_YEAR(rtc_1) - 1980; + timespec->month = RTC_RTC_1_MONTH(rtc_1); + timespec->day = RTC_RTC_1_DAY(rtc_1); } #if (RTC_ALARMS > 0) || defined(__DOXYGEN__) @@ -183,7 +190,7 @@ void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec) { * @note The function can be called from any context. * * @param[in] rtcp pointer to RTC driver structure. - * @param[in] alarm alarm identifier. Can be 1 or 2. + * @param[in] alarm alarm identifier. Can be 1. * @param[in] alarmspec pointer to a @p RTCAlarm structure. * * @notapi @@ -193,48 +200,63 @@ void rtc_lld_set_alarm(RTCDriver *rtcp, const RTCAlarm *alarmspec) { (void)alarm; - RTCDateTime *t = &alarmspec->alarm; - uint32_t sec = (uint32_t)t->millisecond / 1000; - uint32_t hour = sec / 3600; + uint32_t sec, min, hour, day, month, year, dotw, setup0, setup1; + RTCDateTime *timespec = &alarmspec->alarm; + sec = (uint32_t)timespec->millisecond / 1000; + hour = sec / 3600; sec %= 3600; - uint32_t min = sec / 60; + min = sec / 60; sec %= 60; + day = timespec->day; + month = timespec->month; - rtc_disable_alarm(); + /* Normalise and setup for non-zero checking. */ + year = timespec->year == 0 ? 0 : timespec->year + 1980; + dotw = timespec->dayofweek; - // Only add to setup if it isn't -1 - rtcp->rtc->IRQSETUP0 = ((t->year < 0) ? 0 : (((uint)t->year) << RTC_IRQ_SETUP_0_YEAR_LSB )) | - ((t->month < 0) ? 0 : (((uint)t->month) << RTC_IRQ_SETUP_0_MONTH_LSB)) | - ((t->day < 0) ? 0 : (((uint)t->day) << RTC_IRQ_SETUP_0_DAY_LSB )); - rtcp->rtc->IRQSETUP1 = ((t->dotw == 0) ? 0 : (((uint)t->dotw) << RTC_IRQ_SETUP_1_DOTW_LSB)) | - (t->hour << RTC_IRQ_SETUP_1_HOUR_LSB)) | - (t->min << RTC_IRQ_SETUP_1_MIN_LSB )) | - (t->sec << RTC_IRQ_SETUP_1_SEC_LSB )); + /* Write all registers regardless. */ + setup0 = (RTC_IRQ_SETUP_0_YEAR(year)) | + (RTC_IRQ_SETUP_0_MONTH(month)) | + (RTC_IRQ_SETUP_0_DAY(day)); + setup1 = (RTC_IRQ_SETUP_1_DOTW(dotw - 1)) | + (RTC_IRQ_SETUP_1_HOUR(hour)) | + (RTC_IRQ_SETUP_1_MIN(min)) | + (RTC_IRQ_SETUP_1_SEC(sec); - // Set the match enable bits for things we care about - if (t->year >= 0) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_YEAR_ENA_BITS); - if (t->month >= 0) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_MONTH_ENA_BITS); - if (t->day >= 0) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_DAY_ENA_BITS); - if (t->dotw >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_DOTW_ENA_BITS); - if (t->hour >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_HOUR_ENA_BITS); - if (t->min >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_MIN_ENA_BITS); - if (t->sec >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_SEC_ENA_BITS); + /* Check and set match enable bits for non-zero */ + if (year > 0) setup0 |= RTC_IRQ_SETUP_0_YEAR_ENA; + if (month > 0) setup0 |= RTC_IRQ_SETUP_0_MONTH_ENA; + if (day > 0) setup0 |= RTC_IRQ_SETUP_0_DAY_ENA; + if (dotw > 0) setup1 |= RTC_IRQ_SETUP_1_DOTW_ENA; + if (hour > 0) setup1 |= RTC_IRQ_SETUP_1_HOUR_ENA; + if (min > 0) setup1 |= RTC_IRQ_SETUP_1_MIN_ENA; + if (sec > 0) setup1 |= RTC_IRQ_SETUP_1_SEC_ENA; + + /* Entering a reentrant critical zone.*/ + syssts_t sts = osalSysGetStatusAndLockX(); + + rtc_disable_alarm(rtcp); + rtcp->rtc->IRQSETUP0 = setup0; + rtcp->rtc->IRQSETUP1 = setup1; // Does it repeat? I.e. do we not match on any of the bits - _alarm_repeats = rtc_alarm_repeats(t); + //_alarm_repeats = rtc_alarm_repeats(t); // Store function pointer we can call later - _callback = user_callback; + //_callback = user_callback; - irq_set_exclusive_handler(RTC_IRQ, rtc_irq_handler); + //irq_set_exclusive_handler(RTC_IRQ, rtc_irq_handler); // Enable the IRQ at the peri - rtc_hw->inte = RTC_INTE_RTC_BITS; + //rtc_hw->inte = RTC_INTE_RTC_BITS; // Enable the IRQ at the proc - irq_set_enabled(RTC_IRQ, true); + //irq_set_enabled(RTC_IRQ, true); - rtc_enable_alarm(); + rtc_enable_alarm(rtcp); + + /* Leaving a reentrant critical zone.*/ + osalSysRestoreStatusX(sts); } /** @@ -257,6 +279,22 @@ void rtc_lld_get_alarm(RTCDriver *rtcp, } #endif /* RTC_ALARMS > 0 */ +/** + * @brief Enables or disables RTC callbacks. + * @details This function enables or disables callbacks, use a @p NULL pointer + * in order to disable a callback. + * @note The function can be called from any context. + * + * @param[in] rtcp pointer to RTC driver structure + * @param[in] callback callback function pointer or @p NULL + * + * @notapi + */ +void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback) { + + rtcp->callback = callback; +} + #endif /* HAL_USE_RTC */ /** @} */ diff --git a/os/hal/ports/RP/LLD/RTCv1/hal_rtc_lld.h b/os/hal/ports/RP/LLD/RTCv1/hal_rtc_lld.h index 9ae2b17f6..6ade6f971 100644 --- a/os/hal/ports/RP/LLD/RTCv1/hal_rtc_lld.h +++ b/os/hal/ports/RP/LLD/RTCv1/hal_rtc_lld.h @@ -89,7 +89,6 @@ typedef enum { */ typedef void (*rtccb_t)(RTCDriver *rtcp, rtcevent_t event); - /** * @brief Type of a structure representing an RTC alarm time stamp. */