git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5182 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
gdisirio
parent
353219b389
commit
2211987fdb
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@ -100,51 +100,51 @@ Settings: SYSCLK=120
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.1 (Benchmark, messages #1)
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--- Score : 378081 msgs/S, 756162 ctxswc/S
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--- Score : 378087 msgs/S, 756174 ctxswc/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.2 (Benchmark, messages #2)
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--- Score : 312112 msgs/S, 624224 ctxswc/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.3 (Benchmark, messages #3)
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--- Score : 312115 msgs/S, 624230 ctxswc/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.3 (Benchmark, messages #3)
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--- Score : 312112 msgs/S, 624224 ctxswc/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.4 (Benchmark, context switch)
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--- Score : 1099584 ctxswc/S
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--- Score : 1088328 ctxswc/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.5 (Benchmark, threads, full cycle)
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--- Score : 244343 threads/S
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--- Score : 250733 threads/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.6 (Benchmark, threads, create only)
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--- Score : 369918 threads/S
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--- Score : 369919 threads/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads)
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--- Score : 94519 reschedules/S, 567114 ctxswc/S
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--- Score : 92909 reschedules/S, 557454 ctxswc/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.8 (Benchmark, round robin context switching)
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--- Score : 633460 ctxswc/S
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--- Score : 617000 ctxswc/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.9 (Benchmark, I/O Queues throughput)
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--- Score : 1104628 bytes/S
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--- Score : 1084644 bytes/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.10 (Benchmark, virtual timers set/reset)
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--- Score : 1295758 timers/S
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--- Score : 1325758 timers/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.11 (Benchmark, semaphores wait/signal)
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--- Score : 1762552 wait+signal/S
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--- Score : 1743316 wait+signal/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.12 (Benchmark, mutexes lock/unlock)
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--- Score : 1227172 lock+unlock/S
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--- Score : 1210644 lock+unlock/S
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--- Result: SUCCESS
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----------------------------------------------------------------------------
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--- Test Case 11.13 (Benchmark, RAM footprint)
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@ -109,11 +109,6 @@ void spc_early_init(void) {
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#if !SPC5_NO_INIT
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/* Enables the branch prediction, clears and enables the BTB into the
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BUCSR special register (1013).*/
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asm volatile ("li %%r3, 0x0201 \t\n"
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"mtspr 1013, %%r3": : : "r3");
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/* SSCM initialization. Setting up the most restrictive handling of
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invalid accesses to peripherals.*/
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SSCM.ERROR.R = 3; /* PAE and RAE bits. */
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@ -87,11 +87,31 @@
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#define MAS3_SR 0x00000001
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/** @} */
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/**
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* @name BUCSR registers definitions
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* @{
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*/
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#define BUCSR_BPEN 0x00000001
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#define BUCSR_BPRED_MASK 0x00000006
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#define BUCSR_BPRED_0 0x00000000
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#define BUCSR_BPRED_1 0x00000002
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#define BUCSR_BPRED_2 0x00000004
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#define BUCSR_BPRED_3 0x00000006
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#define BUCSR_BALLOC_MASK 0x00000030
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#define BUCSR_BALLOC_0 0x00000030
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#define BUCSR_BALLOC_1 0x00000010
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#define BUCSR_BALLOC_2 0x00000020
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#define BUCSR_BALLOC_3 0x00000030
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#define BUCSR_BALLOC_BFI 0x00000200
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/** @} */
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/**
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* @name LICSR1 registers definitions
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* @{
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*/
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#define LICSR1_ICE 0x00000001
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#define LICSR1_ICINV 0x00000002
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#define LICSR1_ICORG 0x00000010
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/** @} */
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/**
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@ -119,20 +139,39 @@
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MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
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#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3))
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#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_2M)
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#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
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#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I)
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#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \
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MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
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#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4))
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#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
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#define TLB4_MAS2 (MAS2_EPN(0x8FF00000) | MAS2_I)
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#define TLB4_MAS3 (MAS3_RPN(0x8FF00000) | \
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MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
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#define TLB5_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(5))
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#define TLB5_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
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#define TLB5_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I)
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#define TLB5_MAS3 (MAS3_RPN(0xFFF00000) | \
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MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
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/** @} */
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/**
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* @name BUCSR default settings
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* @{
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*/
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#define BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \
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BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI)
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/** @} */
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/**
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* @name LICSR1 default settings
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* @{
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*/
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#define LICSR1_DEFAULT (LICSR1_ICE)
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#define LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG)
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/** @} */
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/**
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* @name MSR register definitions
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* @{
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@ -157,33 +196,23 @@
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* @name MSR default settings
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* @{
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*/
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#define MSR_DEFAULT (MSR_ME)
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#define MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_ME)
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/** @} */
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#if !defined(__DOXYGEN__)
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.section .coreinit, "ax"
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.align 2
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_ramcode:
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tlbwe
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isync
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blr
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.align 2
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.globl _coreinit
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.type _coreinit, @function
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_coreinit:
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/*
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* TLB0 allocated to flash.
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*/
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lis %r3, TLB0_MAS0@h
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mtspr 624, %r3 /* MAS0 */
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lis %r3, TLB0_MAS1@h
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ori %r3, %r3, TLB0_MAS1@l
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mtspr 625, %r3 /* MAS1 */
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lis %r3, TLB0_MAS2@h
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ori %r3, %r3, TLB0_MAS2@l
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mtspr 626, %r3 /* MAS2 */
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lis %r3, TLB0_MAS3@h
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ori %r3, %r3, TLB0_MAS3@l
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mtspr 627, %r3 /* MAS3 */
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tlbwe
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/*
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* TLB1 allocated to internal RAM.
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*/
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@ -232,6 +261,38 @@ _coreinit:
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mtspr 627, %r3 /* MAS3 */
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tlbwe
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/*
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* TLB4 allocated to on-platform peripherals.
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*/
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lis %r3, TLB4_MAS0@h
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mtspr 624, %r3 /* MAS0 */
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lis %r3, TLB4_MAS1@h
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ori %r3, %r3, TLB4_MAS1@l
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mtspr 625, %r3 /* MAS1 */
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lis %r3, TLB4_MAS2@h
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ori %r3, %r3, TLB4_MAS2@l
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mtspr 626, %r3 /* MAS2 */
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lis %r3, TLB4_MAS3@h
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ori %r3, %r3, TLB4_MAS3@l
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mtspr 627, %r3 /* MAS3 */
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tlbwe
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/*
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* TLB5 allocated to on-platform peripherals.
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*/
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lis %r3, TLB5_MAS0@h
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mtspr 624, %r3 /* MAS0 */
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lis %r3, TLB5_MAS1@h
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ori %r3, %r3, TLB5_MAS1@l
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mtspr 625, %r3 /* MAS1 */
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lis %r3, TLB5_MAS2@h
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ori %r3, %r3, TLB5_MAS2@l
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mtspr 626, %r3 /* MAS2 */
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lis %r3, TLB5_MAS3@h
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ori %r3, %r3, TLB5_MAS3@l
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mtspr 627, %r3 /* MAS3 */
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tlbwe
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/*
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* Invalidating the remaining TLBs (because debuggers).
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*/
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@ -239,12 +300,6 @@ _coreinit:
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mtspr 625, %r3 /* MAS1 */
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mtspr 626, %r3 /* MAS2 */
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mtspr 627, %r3 /* MAS3 */
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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@ -277,9 +332,7 @@ _coreinit:
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tlbwe
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/*
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* Enabling peripheral bridges to allow all operations from all
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* masters. Required in order to enable the following accesses to
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* peripherals.
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* PBRIDGE programmed to allow all accesses from user mode.
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*/
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lis %r7, 0xFFF0
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lis %r3, 0x7777
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@ -303,6 +356,19 @@ _coreinit:
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stw %r3, 104(%r7)
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stw %r3, 108(%r7)
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e_lis r6,0xfff3
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e_or2i r6,0x8010
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e_li r7,0xC520
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se_stw r7,0x0(r6)
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e_li r7,0xD928
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se_stw r7,0x0(r6)
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e_lis r6,0xfff3
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e_or2i r6,0x8000
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e_lis r7,0xff00
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e_or2i r7,0x10A
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se_stw r7,0x0(r6) /* # WEN = 0 */
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/*
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* RAM clearing, this device requires a write to all RAM location in
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* order to initialize the ECC detection hardware, this is going to
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@ -376,8 +442,8 @@ _coreinit:
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mtspr 279, %r31
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mtspr 285, %r31 /* TBU */
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mtspr 284, %r31 /* TBL */
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mtspr 318, %r31 /* DVC1-2 */
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mtspr 319, %r31
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// mtspr 318, %r31 /* DVC1-2 */
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// mtspr 319, %r31
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mtspr 562, %r31 /* DBCNT */
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mtspr 570, %r31 /* MCSRR0 */
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mtspr 571, %r31 /* MCSRR1 */
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@ -385,10 +451,50 @@ _coreinit:
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mtspr 605, %r31
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/*
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* Cache enabled.
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* *Finally* the TLB0 is re-allocated to flash, note, the final phase
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* is executed from RAM.
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*/
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mfspr %r3, 1011 /* LICSR1 */
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ori %r3, %r3, LICSR1_DEFAULT
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lis %r3, TLB0_MAS0@h
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mtspr 624, %r3 /* MAS0 */
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lis %r3, TLB0_MAS1@h
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ori %r3, %r3, TLB0_MAS1@l
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mtspr 625, %r3 /* MAS1 */
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lis %r3, TLB0_MAS2@h
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ori %r3, %r3, TLB0_MAS2@l
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mtspr 626, %r3 /* MAS2 */
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lis %r3, TLB0_MAS3@h
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ori %r3, %r3, TLB0_MAS3@l
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mtspr 627, %r3 /* MAS3 */
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mflr %r4
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lis %r6, _ramcode@h
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ori %r6, %r6, _ramcode@l
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lis %r7, 0x40010000@h
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mtctr %r7
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lwz %r3, 0(%r6)
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stw %r3, 0(%r7)
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lwz %r3, 4(%r6)
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stw %r3, 4(%r7)
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lwz %r3, 8(%r6)
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stw %r3, 8(%r7)
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bctrl
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mtlr %r4
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/*
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* Branch prediction enabled.
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*/
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li %r3, BUCSR_DEFAULT
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mtspr 1013, %r3 /* BUCSR */
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/*
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* Cache invalidated and then enabled.
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*/
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li %r3, LICSR1_ICINV
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mtspr 1011, %r3 /* LICSR1 */
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.inv: mfspr %r3, 1011 /* LICSR1 */
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andi. %r3, %r3, LICSR1_ICINV
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bne .inv
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lis %r3, LICSR1_DEFAULT@h
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ori %r3, %r3, LICSR1_DEFAULT@l
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mtspr 1011, %r3 /* LICSR1 */
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blr
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/* IVORs initialization.*/
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lis %r3, _unhandled_exception@h
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ori %r3, %r3, _unhandled_exception@l
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mtspr 400, %r3 /* IVOR0-15 */
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mtspr 401, %r3
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mtspr 402, %r3
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mtspr 528, %r3 /* IVOR32-34 */
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mtspr 529, %r3
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mtspr 530, %r3
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blr
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/*
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