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ChibiOS
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Various minor errors. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13320 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2020-02-04 14:48:22 +00:00
parent 5dc0db3f1f
commit 22d0d06a3e
2 changed files with 24 additions and 24 deletions
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2
os/hal/ports/STM32/STM32G4xx/hal_lld.c
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@ -34,7 +34,7 @@
/**
* @brief CMSIS system core clock variable.
* @note It is declared in system_stm32l4xx.h.
* @note It is declared in system_stm32g4xx.h.
*/
uint32_t SystemCoreClock = STM32_HCLK;

28
os/hal/ports/STM32/STM32G4xx/hal_lld.h
View File

@ -160,11 +160,11 @@
#define STM32_PPRE2_MASK (7U << 11U) /**< PPRE2 field mask. */
#define STM32_PPRE2_FIELD(n) ((n) << 11U) /**< PPRE2 field value. */
#define STM32_PPRE2_DIV1 STM32_PPRE1_FIELD(0U)
#define STM32_PPRE2_DIV2 STM32_PPRE1_FIELD(4U)
#define STM32_PPRE2_DIV4 STM32_PPRE1_FIELD(5U)
#define STM32_PPRE2_DIV8 STM32_PPRE1_FIELD(6U)
#define STM32_PPRE2_DIV16 STM32_PPRE1_FIELD(7U)
#define STM32_PPRE2_DIV1 STM32_PPRE2_FIELD(0U)
#define STM32_PPRE2_DIV2 STM32_PPRE2_FIELD(4U)
#define STM32_PPRE2_DIV4 STM32_PPRE2_FIELD(5U)
#define STM32_PPRE2_DIV8 STM32_PPRE2_FIELD(6U)
#define STM32_PPRE2_DIV16 STM32_PPRE2_FIELD(7U)
#define STM32_MCOSEL_MASK (15U << 24U)/**< MCOSEL field mask. */
#define STM32_MCOSEL_NOCLOCK (0U << 24U) /**< No clock on MCO pin. */
@ -1160,7 +1160,7 @@
#endif
/**
* @brief STM32_PLLPDIV field. (Only for STM32L496xx/4A6xx)
* @brief STM32_PLLPDIV field.
*/
#if (STM32_PLLPDIV_VALUE == 0) || \
((STM32_PLLPDIV_VALUE >= 2) && (STM32_PLLPDIV_VALUE <= 31)) || \
@ -1329,27 +1329,27 @@
#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
#endif
/**
/**
* @brief APB1 frequency.
*/
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
#define STM32_PCLK1 (STM32_HCLK / 1)
#elif STM32_PPRE1 == STM32_PPRE1_DIV2
#elif STM32_PPRE1 == STM32_PPRE1_DIV2
#define STM32_PCLK1 (STM32_HCLK / 2)
#elif STM32_PPRE1 == STM32_PPRE1_DIV4
#elif STM32_PPRE1 == STM32_PPRE1_DIV4
#define STM32_PCLK1 (STM32_HCLK / 4)
#elif STM32_PPRE1 == STM32_PPRE1_DIV8
#elif STM32_PPRE1 == STM32_PPRE1_DIV8
#define STM32_PCLK1 (STM32_HCLK / 8)
#elif STM32_PPRE1 == STM32_PPRE1_DIV16
#elif STM32_PPRE1 == STM32_PPRE1_DIV16
#define STM32_PCLK1 (STM32_HCLK / 16)
#else
#else
#error "invalid STM32_PPRE1 value specified"
#endif
#endif
/*
* APB1 frequency check.