git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10308 35acf78f-673a-0410-8e92-d51de3d6d3f4
This commit is contained in:
Rocco Marco Guglielmi 2017-07-08 08:39:08 +00:00
parent b6fa231be6
commit 22dadf76b5
3 changed files with 41 additions and 5 deletions

View File

@ -172,7 +172,7 @@ void hal_lld_init(void) {
}
/**
* @brief STM32L1xx voltage, clocks and PLL initialization.
* @brief STM32L0xx voltage, clocks and PLL initialization.
* @note All the involved constants come from the file @p board.h.
* @note This function should be invoked just after the system reset.
*
@ -260,6 +260,23 @@ void stm32_clock_init(void) {
; /* Waits until PLL is stable. */
#endif
#if STM32_ACTIVATE_HSI48
/* Enabling SYSCFG clock. */
rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, FALSE);
/* Configuring SYSCFG to enable VREFINT and HSI48 VREFINT buffer. */
SYSCFG->CFGR3 = STM32_VREFINT_EN | SYSCFG_CFGR3_ENREF_HSI48;
while (!(SYSCFG->CFGR3 & SYSCFG_CFGR3_VREFINT_RDYF))
; /* Waits until VREFINT is stable. */
/* Disabling SYSCFG clock. */
rccDisableAPB2(RCC_APB2ENR_SYSCFGEN, FALSE);
/* Enabling HSI48. */
RCC->CRRCR |= RCC_CRRCR_HSI48ON;
while (!(RCC->CRRCR & RCC_CRRCR_HSI48RDY))
; /* Waits until HSI48 is stable. */
#endif
/* Other clock-related settings (dividers, MCO etc).*/
RCC->CR |= STM32_RTCPRE;
RCC->CFGR |= STM32_MCOPRE | STM32_MCOSEL |
@ -271,7 +288,7 @@ void stm32_clock_init(void) {
FLASH->ACR = STM32_FLASHBITS;
#endif
/* Switching to the configured clock source if it is different from MSI.*/
/* Switching to the configured clock source if it is different from MSI. */
#if (STM32_SW != STM32_SW_MSI)
RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */
while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))

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@ -278,6 +278,13 @@
#define STM32_HSI48SEL_HSI48 (1 << 26) /**< USB48 clock is HSI48. */
/** @} */
/**
* @name SYSCFG_CFGR3_ register bits definitions
* @{
*/
#define STM32_VREFINT_EN (1 << 0) /**< VREFINT enable switch. */
/** @} */
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@ -758,9 +765,8 @@
#endif /* !STM32_LSE_ENABLED */
/* PLL related checks.*/
#if STM32_USB_CLOCK_ENABLED || \
(STM32_SW == STM32_SW_PLL) || \
(STM32_MCOSEL == STM32_MCOSEL_PLL) || \
#if (STM32_SW == STM32_SW_PLL) || (STM32_MCOSEL == STM32_MCOSEL_PLL) || \
(STM32_USB_CLOCK_ENABLED && (STM32_HSI48SEL == STM32_HSI48SEL_USBPLL)) || \
defined(__DOXYGEN__)
/**
* @brief PLL activation flag.
@ -770,6 +776,17 @@
#define STM32_ACTIVATE_PLL FALSE
#endif
/* HSI48 related checks.*/
#if (STM32_USB_CLOCK_ENABLED && (STM32_HSI48SEL == STM32_HSI48SEL_HSI48)) || \
defined(__DOXYGEN__)
/**
* @brief HSI48 activation flag.
*/
#define STM32_ACTIVATE_HSI48 TRUE
#else
#define STM32_ACTIVATE_HSI48 FALSE
#endif
/**
* @brief PLLMUL field.
*/

View File

@ -93,6 +93,8 @@
to 17.6.1).
- VAR: Fixed STM32L053 Discovery demo which is unaligned to standard demos (bug
#857)(backported to 17.6.1).
- HAL: Fixed HSI48 which is not correctly enabled in STM32L0xx port (bug #856)
(backported to 17.6.1).
- HAL: Fixed unaligned STM32F0xx mcuconf.h files (bug #855)(backported
to 17.6.1).
- HAL: Fixed invalid handling of DST flag in STM32 RTCv2 (bug #854)(backported