From 2376c38058a5a96e89c393c5db16681fe192876a Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Fri, 26 Apr 2019 17:26:46 +0000 Subject: [PATCH] debugging... git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12771 27425a3e-05d8-49a3-a47f-9c15f0e5edd8 --- .../RT-STM32G071RB-NUCLEO64/cfg/chconf.h | 2 +- os/hal/ports/STM32/STM32G0xx/hal_lld.h | 119 ++++++----- os/hal/ports/STM32/STM32G0xx/stm32_isr.h | 2 - os/hal/ports/STM32/STM32G0xx/stm32_registry.h | 198 ++++++++++++++++++ 4 files changed, 260 insertions(+), 61 deletions(-) diff --git a/demos/STM32/RT-STM32G071RB-NUCLEO64/cfg/chconf.h b/demos/STM32/RT-STM32G071RB-NUCLEO64/cfg/chconf.h index e50f15cce..24691d739 100644 --- a/demos/STM32/RT-STM32G071RB-NUCLEO64/cfg/chconf.h +++ b/demos/STM32/RT-STM32G071RB-NUCLEO64/cfg/chconf.h @@ -172,7 +172,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_CFG_USE_TM) -#define CH_CFG_USE_TM TRUE +#define CH_CFG_USE_TM FALSE #endif /** diff --git a/os/hal/ports/STM32/STM32G0xx/hal_lld.h b/os/hal/ports/STM32/STM32G0xx/hal_lld.h index 117352c3b..48463c1cd 100644 --- a/os/hal/ports/STM32/STM32G0xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32G0xx/hal_lld.h @@ -120,15 +120,15 @@ * @{ */ #define STM32_HSIDIV_MASK (7U << 11U) /**< HSIDIV field mask. */ -#define STM32_HSIDIV(n) ((n) << 11U) /**< HSIDIV field value. */ -#define STM32_HSIDIV_1 STM32_HSIDIV(0U) -#define STM32_HSIDIV_2 STM32_HSIDIV(1U) -#define STM32_HSIDIV_4 STM32_HSIDIV(2U) -#define STM32_HSIDIV_8 STM32_HSIDIV(3U) -#define STM32_HSIDIV_16 STM32_HSIDIV(4U) -#define STM32_HSIDIV_32 STM32_HSIDIV(5U) -#define STM32_HSIDIV_64 STM32_HSIDIV(6U) -#define STM32_HSIDIV_128 STM32_HSIDIV(7U) +#define STM32_HSIDIV_FIELD(n) ((n) << 11U) /**< HSIDIV field value. */ +#define STM32_HSIDIV_1 STM32_HSIDIV_FIELD(0U) +#define STM32_HSIDIV_2 STM32_HSIDIV_FIELD(1U) +#define STM32_HSIDIV_4 STM32_HSIDIV_FIELD(2U) +#define STM32_HSIDIV_8 STM32_HSIDIV_FIELD(3U) +#define STM32_HSIDIV_16 STM32_HSIDIV_FIELD(4U) +#define STM32_HSIDIV_32 STM32_HSIDIV_FIELD(5U) +#define STM32_HSIDIV_64 STM32_HSIDIV_FIELD(6U) +#define STM32_HSIDIV_128 STM32_HSIDIV_FIELD(7U) /** @} */ /** @@ -143,24 +143,24 @@ #define STM32_SW_LSE (4U << 0U) /**< SYSCLK source is LSE. */ #define STM32_HPRE_MASK (15U << 8U) /**< HPRE field mask. */ -#define STM32_HPRE(n) ((n) << 8U) /**< HPRE field value. */ -#define STM32_HPRE_DIV1 STM32_HPRE(0U) -#define STM32_HPRE_DIV2 STM32_HPRE(8U) -#define STM32_HPRE_DIV4 STM32_HPRE(9U) -#define STM32_HPRE_DIV8 STM32_HPRE(10U) -#define STM32_HPRE_DIV16 STM32_HPRE(11U) -#define STM32_HPRE_DIV64 STM32_HPRE(12U) -#define STM32_HPRE_DIV128 STM32_HPRE(13U) -#define STM32_HPRE_DIV256 STM32_HPRE(14U) -#define STM32_HPRE_DIV512 STM32_HPRE(15U) +#define STM32_HPRE_FIELD(n) ((n) << 8U) /**< HPRE field value. */ +#define STM32_HPRE_DIV1 STM32_HPRE_FIELD(0U) +#define STM32_HPRE_DIV2 STM32_HPRE_FIELD(8U) +#define STM32_HPRE_DIV4 STM32_HPRE_FIELD(9U) +#define STM32_HPRE_DIV8 STM32_HPRE_FIELD(10U) +#define STM32_HPRE_DIV16 STM32_HPRE_FIELD(11U) +#define STM32_HPRE_DIV64 STM32_HPRE_FIELD(12U) +#define STM32_HPRE_DIV128 STM32_HPRE_FIELD(13U) +#define STM32_HPRE_DIV256 STM32_HPRE_FIELD(14U) +#define STM32_HPRE_DIV512 STM32_HPRE_FIELD(15U) #define STM32_PPRE_MASK (7U << 12U) /**< PPRE field mask. */ -#define STM32_PPRE(n) (7U << 12U) /**< PPRE field value. */ -#define STM32_PPRE_DIV1 STM32_PPRE(0U) -#define STM32_PPRE_DIV2 STM32_PPRE(4U) -#define STM32_PPRE_DIV4 STM32_PPRE(5U) -#define STM32_PPRE_DIV8 STM32_PPRE(6U) -#define STM32_PPRE_DIV16 STM32_PPRE(7U) +#define STM32_PPRE_FIELD(n) (7U << 12U) /**< PPRE field value. */ +#define STM32_PPRE_DIV1 STM32_PPRE_FIELD(0U) +#define STM32_PPRE_DIV2 STM32_PPRE_FIELD(4U) +#define STM32_PPRE_DIV4 STM32_PPRE_FIELD(5U) +#define STM32_PPRE_DIV8 STM32_PPRE_FIELD(6U) +#define STM32_PPRE_DIV16 STM32_PPRE_FIELD(7U) #define STM32_MCOSEL_MASK (7U << 24U) /**< MCOSEL field mask. */ #define STM32_MCOSEL_NOCLOCK (0U << 24U) /**< No clock on MCO pin. */ @@ -172,15 +172,15 @@ #define STM32_MCOSEL_LSE (7U << 24U) /**< LSE clock on MCO pin. */ #define STM32_MCOPRE_MASK (7U << 28U) /**< MCOPRE field mask. */ -#define STM32_MCOPRE(n) ((n) << 28U)/**< MCOPRE field value */ -#define STM32_MCOPRE_DIV1 STM32_MCOPRE(0U) -#define STM32_MCOPRE_DIV2 STM32_MCOPRE(1U) -#define STM32_MCOPRE_DIV4 STM32_MCOPRE(2U) -#define STM32_MCOPRE_DIV8 STM32_MCOPRE(3U) -#define STM32_MCOPRE_DIV16 STM32_MCOPRE(4U) -#define STM32_MCOPRE_DIV32 STM32_MCOPRE(5U) -#define STM32_MCOPRE_DIV64 STM32_MCOPRE(6U) -#define STM32_MCOPRE_DIV128 STM32_MCOPRE(7U) +#define STM32_MCOPRE_FIELD(n) ((n) << 28U)/**< MCOPRE field value */ +#define STM32_MCOPRE_DIV1 STM32_MCOPRE_FIELD(0U) +#define STM32_MCOPRE_DIV2 STM32_MCOPRE_FIELD(1U) +#define STM32_MCOPRE_DIV4 STM32_MCOPRE_FIELD(2U) +#define STM32_MCOPRE_DIV8 STM32_MCOPRE_FIELD(3U) +#define STM32_MCOPRE_DIV16 STM32_MCOPRE_FIELD(4U) +#define STM32_MCOPRE_DIV32 STM32_MCOPRE_FIELD(5U) +#define STM32_MCOPRE_DIV64 STM32_MCOPRE_FIELD(6U) +#define STM32_MCOPRE_DIV128 STM32_MCOPRE_FIELD(7U) /** @} */ /** @@ -257,11 +257,11 @@ #define STM32_RNGSEL_PLLQCLK (3U << 26U) /**< RNG source is PLLQCLK. */ #define STM32_RNGDIV_MASK (3U << 28U) /**< RNGDIV field mask. */ -#define STM32_RNGDIV(n) ((n) << 28U)/**< RNGDIV field value */ -#define STM32_RNGDIV_1 STM32_RNGDIV(0U) -#define STM32_RNGDIV_2 STM32_RNGDIV(1U) -#define STM32_RNGDIV_4 STM32_RNGDIV(2U) -#define STM32_RNGDIV_8 STM32_RNGDIV(3U) +#define STM32_RNGDIV_FIELD(n) ((n) << 28U)/**< RNGDIV field value */ +#define STM32_RNGDIV_1 STM32_RNGDIV_FIELD(0U) +#define STM32_RNGDIV_2 STM32_RNGDIV_FIELD(1U) +#define STM32_RNGDIV_4 STM32_RNGDIV_FIELD(2U) +#define STM32_RNGDIV_8 STM32_RNGDIV_FIELD(3U) #define STM32_ADCSEL_MASK (3U << 30U) /**< ADCSEL mask. */ #define STM32_ADCSEL_NOCLK (0U << 30U) /**< ADC source is SYSCLK. */ @@ -341,6 +341,13 @@ #define STM32_HSE_ENABLED FALSE #endif +/** + * @brief Enables or disables the LSI clock source. + */ +#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSI_ENABLED FALSE +#endif + /** * @brief Enables or disables the LSE clock source. */ @@ -492,7 +499,7 @@ * @brief I2S1 clock source. */ #if !defined(STM32_I2S1SEL) || defined(__DOXYGEN__) -#define STM32_I2S1SEL STM32_I2S1SEL_PCLK +#define STM32_I2S1SEL STM32_I2S1SEL_SYSCLK #endif /** @@ -753,11 +760,11 @@ #if STM32_HSI16_ENABLED #else /* !STM32_HSI16_ENABLED */ -#if STM32_SW == STM32_SW_HSI16 +#if STM32_SW == STM32_SW_HSISYS #error "HSI16 not enabled, required by STM32_SW" #endif -#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI16) +#if (STM32_SW == STM32_SW_PLLRCLK) && (STM32_PLLSRC == STM32_PLLSRC_HSI16) #error "HSI16 not enabled, required by STM32_SW and STM32_PLLSRC" #endif @@ -833,12 +840,12 @@ #error "HSE not enabled, required by STM32_SW" #endif - #if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE) + #if (STM32_SW == STM32_SW_PLLRCLK) && (STM32_PLLSRC == STM32_PLLSRC_HSE) #error "HSE not enabled, required by STM32_SW and STM32_PLLSRC" #endif #if (STM32_MCOSEL == STM32_MCOSEL_HSE) || \ - ((STM32_MCOSEL == STM32_MCOSEL_PLL) && \ + ((STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) && \ (STM32_PLLSRC == STM32_PLLSRC_HSE)) #error "HSE not enabled, required by STM32_MCOSEL" #endif @@ -958,8 +965,8 @@ /* * PLL enable check. */ -#if (STM32_SW == STM32_SW_PLL) || \ - (STM32_MCOSEL == STM32_MCOSEL_PLL) || \ +#if (STM32_SW == STM32_SW_PLLRCLK) || \ + (STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) || \ (STM32_TIM1SEL == STM32_TIM1SEL_PLLQCLK) || \ (STM32_TIM15SEL == STM32_TIM15SEL_PLLQCLK) || \ (STM32_RNGSEL == STM32_RNGSEL_PLLQCLK) || \ @@ -1022,8 +1029,8 @@ /** * @brief STM32_PLLREN field. */ -#if (STM32_SW == STM32_SW_PLL) || \ - (STM32_MCOSEL == STM32_MCOSEL_PLL) || \ +#if (STM32_SW == STM32_SW_PLLRCLK) || \ + (STM32_MCOSEL == STM32_MCOSEL_PLLRCLK) || \ defined(__DOXYGEN__) #define STM32_PLLREN (1 << 28) #else @@ -1079,11 +1086,7 @@ /** * @brief PLL P output clock frequency. */ -#if (STM32_PLLPDIV_VALUE == 0) || defined(__DOXYGEN__) #define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE) -#else -#define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLPDIV_VALUE) -#endif /* * PLL-R output frequency range check. @@ -1295,7 +1298,7 @@ /** * @brief USART1 clock frequency. */ -#if (STM32_USART1SEL == STM32_USART1SEL_PCLK2) || defined(__DOXYGEN__) +#if (STM32_USART1SEL == STM32_USART1SEL_PCLK) || defined(__DOXYGEN__) #define STM32_USART1CLK STM32_PCLK #elif STM32_USART1SEL == STM32_USART1SEL_SYSCLK #define STM32_USART1CLK STM32_SYSCLK @@ -1310,7 +1313,7 @@ /** * @brief USART2 clock frequency. */ -#if (STM32_USART2SEL == STM32_USART2SEL_PCLK1) || defined(__DOXYGEN__) +#if (STM32_USART2SEL == STM32_USART2SEL_PCLK) || defined(__DOXYGEN__) #define STM32_USART2CLK STM32_PCLK #elif STM32_USART2SEL == STM32_USART2SEL_SYSCLK #define STM32_USART2CLK STM32_SYSCLK @@ -1325,7 +1328,7 @@ /** * @brief LPUART1 clock frequency. */ -#if (STM32_LPUART1SEL == STM32_LPUART1SEL_PCLK1) || defined(__DOXYGEN__) +#if (STM32_LPUART1SEL == STM32_LPUART1SEL_PCLK) || defined(__DOXYGEN__) #define STM32_LPUART1CLK STM32_PCLK #elif STM32_LPUART1SEL == STM32_LPUART1SEL_SYSCLK #define STM32_LPUART1CLK STM32_SYSCLK @@ -1351,7 +1354,7 @@ /** * @brief I2C1 clock frequency. */ -#if (STM32_I2C1SEL == STM32_I2C1SEL_PCLK1) || defined(__DOXYGEN__) +#if (STM32_I2C1SEL == STM32_I2C1SEL_PCLK) || defined(__DOXYGEN__) #define STM32_I2C1CLK STM32_PCLK #elif STM32_I2C1SEL == STM32_I2C1SEL_SYSCLK #define STM32_I2C1CLK STM32_SYSCLK @@ -1379,7 +1382,7 @@ /** * @brief LPTIM1 clock frequency. */ -#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PCLK1) || defined(__DOXYGEN__) +#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PCLK) || defined(__DOXYGEN__) #define STM32_LPTIM1CLK STM32_PCLK #elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSI #define STM32_LPTIM1CLK STM32_LSICLK @@ -1394,7 +1397,7 @@ /** * @brief LPTIM2 clock frequency. */ -#if (STM32_LPTIM2SEL == STM32_LPTIM2SEL_PCLK1) || defined(__DOXYGEN__) +#if (STM32_LPTIM2SEL == STM32_LPTIM2SEL_PCLK) || defined(__DOXYGEN__) #define STM32_LPTIM2CLK STM32_PCLK #elif STM32_LPTIM2SEL == STM32_LPTIM2SEL_LSI #define STM32_LPTIM2CLK STM32_LSICLK diff --git a/os/hal/ports/STM32/STM32G0xx/stm32_isr.h b/os/hal/ports/STM32/STM32G0xx/stm32_isr.h index e617c4a58..a87826cfb 100644 --- a/os/hal/ports/STM32/STM32G0xx/stm32_isr.h +++ b/os/hal/ports/STM32/STM32G0xx/stm32_isr.h @@ -33,8 +33,6 @@ * @name ISR names and numbers remapping * @{ */ -/* - /* * I2C units. */ diff --git a/os/hal/ports/STM32/STM32G0xx/stm32_registry.h b/os/hal/ports/STM32/STM32G0xx/stm32_registry.h index 3ce1545d2..091ecb6d6 100644 --- a/os/hal/ports/STM32/STM32G0xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32G0xx/stm32_registry.h @@ -258,6 +258,204 @@ #endif /* defined(STM32G070xx) */ +/*===========================================================================*/ +/* STM32G070xx. */ +/*===========================================================================*/ + +#if defined(STM32G071xx) || defined(STM32G081xx) + +/* ADC attributes.*/ +#define STM32_HAS_ADC1 TRUE +#define STM32_ADC1_HANDLER Vector70 +#define STM32_ADC1_NUMBER 12 + +#define STM32_HAS_ADC2 FALSE +#define STM32_HAS_ADC3 FALSE +#define STM32_HAS_ADC4 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 FALSE +#define STM32_HAS_CAN2 FALSE +#define STM32_HAS_CAN3 FALSE + +/* DAC attributes.*/ +#define STM32_HAS_DAC1_CH1 TRUE +#define STM32_HAS_DAC1_CH2 TRUE +#define STM32_HAS_DAC2_CH1 FALSE +#define STM32_HAS_DAC2_CH2 FALSE + +/* DMA attributes.*/ +#define STM32_ADVANCED_DMA TRUE +#define STM32_DMA_SUPPORTS_DMAMUX TRUE +#define STM32_DMA_SUPPORTS_CSELR FALSE + +#define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA1_CH1_HANDLER Vector64 +#define STM32_DMA1_CH23_HANDLER Vector68 +#define STM32_DMA1_CH4567_HANDLER Vector6C +#define STM32_DMA1_CH1_NUMBER 9 +#define STM32_DMA1_CH23_NUMBER 10 +#define STM32_DMA1_CH4567_NUMBER 11 + +#define STM32_DMA2_NUM_CHANNELS 0 + +/* ETH attributes.*/ +#define STM32_HAS_ETH FALSE + +/* EXTI attributes.*/ +#define STM32_EXTI_NUM_LINES 33 +#define STM32_EXTI_IMR1_MASK 0xFFF80000U +#define STM32_EXTI_IMR2_MASK 0xFFFFFFFFU + +#define STM32_EXTI_LINE01_HANDLER Vector54 +#define STM32_EXTI_LINE23_HANDLER Vector58 +#define STM32_EXTI_LINE4_15_HANDLER Vector5C +#define STM32_EXTI_LINE16_HANDLER Vector44 +#define STM32_EXTI_LINE1921_HANDLER Vector48 + +#define STM32_EXTI_LINE01_NUMBER 5 +#define STM32_EXTI_LINE23_NUMBER 6 +#define STM32_EXTI_LINE4_15_NUMBER 7 +#define STM32_EXTI_LINE16_NUMBER 1 +#define STM32_EXTI_LINE1921_NUMBER 2 + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE FALSE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG FALSE +#define STM32_HAS_GPIOH FALSE +#define STM32_HAS_GPIOI FALSE +#define STM32_HAS_GPIOJ FALSE +#define STM32_HAS_GPIOK FALSE +#define STM32_GPIO_EN_MASK (RCC_IOPENR_GPIOAEN | \ + RCC_IOPENR_GPIOBEN | \ + RCC_IOPENR_GPIOCEN | \ + RCC_IOPENR_GPIODEN | \ + RCC_IOPENR_GPIOFEN) + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 TRUE +#define STM32_HAS_I2C2 TRUE +#define STM32_HAS_I2C3 FALSE +#define STM32_HAS_I2C4 FALSE + +/* OCTOSPI attributes.*/ +#define STM32_HAS_OCTOSPI1 FALSE +#define STM32_HAS_OCTOSPI2 FALSE + +/* QUADSPI attributes.*/ +#define STM32_HAS_QUADSPI1 FALSE + +/* SDMMC attributes.*/ +#define STM32_HAS_SDMMC1 FALSE +#define STM32_HAS_SDMMC2 FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 TRUE +#define STM32_SPI1_SUPPORTS_I2S TRUE + +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_SUPPORTS_I2S FALSE + +#define STM32_HAS_SPI3 FALSE +#define STM32_HAS_SPI4 FALSE +#define STM32_HAS_SPI5 FALSE +#define STM32_HAS_SPI6 FALSE + +/* TIM attributes.*/ +#define STM32_TIM_MAX_CHANNELS 6 + +#define STM32_HAS_TIM1 TRUE +#define STM32_TIM1_IS_32BITS FALSE +#define STM32_TIM1_CHANNELS 6 + +#define STM32_HAS_TIM2 TRUE +#define STM32_TIM2_IS_32BITS TRUE +#define STM32_TIM2_CHANNELS 4 + +#define STM32_HAS_TIM3 TRUE +#define STM32_TIM3_IS_32BITS FALSE +#define STM32_TIM3_CHANNELS 4 + +#define STM32_HAS_TIM6 TRUE +#define STM32_TIM6_IS_32BITS FALSE +#define STM32_TIM6_CHANNELS 0 + +#define STM32_HAS_TIM7 TRUE +#define STM32_TIM7_IS_32BITS FALSE +#define STM32_TIM7_CHANNELS 0 + +#define STM32_HAS_TIM14 TRUE +#define STM32_TIM14_IS_32BITS FALSE +#define STM32_TIM14_CHANNELS 1 + +#define STM32_HAS_TIM15 TRUE +#define STM32_TIM15_IS_32BITS FALSE +#define STM32_TIM15_CHANNELS 2 + +#define STM32_HAS_TIM16 TRUE +#define STM32_TIM16_IS_32BITS FALSE +#define STM32_TIM16_CHANNELS 1 + +#define STM32_HAS_TIM17 TRUE +#define STM32_TIM17_IS_32BITS FALSE +#define STM32_TIM17_CHANNELS 1 + +#define STM32_HAS_TIM4 FALSE +#define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM12 FALSE +#define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE +#define STM32_HAS_TIM20 FALSE +#define STM32_HAS_TIM21 FALSE +#define STM32_HAS_TIM22 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_HAS_USART2 TRUE +#define STM32_HAS_USART3 TRUE +#define STM32_HAS_UART4 TRUE +#define STM32_HAS_LPUART1 TRUE +#define STM32_HAS_UART5 FALSE +#define STM32_HAS_USART6 FALSE +#define STM32_HAS_UART7 FALSE +#define STM32_HAS_UART8 FALSE + +/* USB attributes.*/ +#define STM32_HAS_OTG1 FALSE +#define STM32_HAS_OTG2 FALSE +#define STM32_HAS_USB FALSE + +/* IWDG attributes.*/ +#define STM32_HAS_IWDG TRUE +#define STM32_IWDG_IS_WINDOWED TRUE + +/* LTDC attributes.*/ +#define STM32_HAS_LTDC FALSE + +/* DMA2D attributes.*/ +#define STM32_HAS_DMA2D FALSE + +/* FSMC attributes.*/ +#define STM32_HAS_FSMC FALSE + +/* CRC attributes.*/ +#define STM32_HAS_CRC FALSE + +/* DCMI attributes.*/ +#define STM32_HAS_DCMI FALSE + +#endif /* defined(STM32G070xx) */ + /** @} */ #endif /* STM32_REGISTRY_H */