From 2601494a039e74e33e6b54da515249172c0991b3 Mon Sep 17 00:00:00 2001 From: Andrey Gusakov Date: Tue, 30 May 2023 00:57:54 +0300 Subject: [PATCH] Scripts: helpers for OpenOCD and GDB --- demos/STM32/RT-AT32F435-ARTERY144/.gdbinit | 7 + demos/STM32/RT-AT32F435-ARTERY144/at32f4x.cfg | 149 ++++++++++++++++++ demos/STM32/RT-AT32F435-ARTERY144/gdb.sh | 5 + .../RT-AT32F435-ARTERY144/openocd_artery.sh | 3 + 4 files changed, 164 insertions(+) create mode 100644 demos/STM32/RT-AT32F435-ARTERY144/.gdbinit create mode 100644 demos/STM32/RT-AT32F435-ARTERY144/at32f4x.cfg create mode 100755 demos/STM32/RT-AT32F435-ARTERY144/gdb.sh create mode 100755 demos/STM32/RT-AT32F435-ARTERY144/openocd_artery.sh diff --git a/demos/STM32/RT-AT32F435-ARTERY144/.gdbinit b/demos/STM32/RT-AT32F435-ARTERY144/.gdbinit new file mode 100644 index 000000000..43297efd4 --- /dev/null +++ b/demos/STM32/RT-AT32F435-ARTERY144/.gdbinit @@ -0,0 +1,7 @@ +target extended-remote localhost:3333 +file build/ch.elf +#file build-openblt/openblt_microrusefi.elf +load +set breakpoint auto-hw on +set remote hardware-breakpoint-limit 8 +set remote hardware-watchpoint-limit 4 diff --git a/demos/STM32/RT-AT32F435-ARTERY144/at32f4x.cfg b/demos/STM32/RT-AT32F435-ARTERY144/at32f4x.cfg new file mode 100644 index 000000000..e8cd07a6d --- /dev/null +++ b/demos/STM32/RT-AT32F435-ARTERY144/at32f4x.cfg @@ -0,0 +1,149 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# script for at32f4x family + +# +# stm32f4 devices support both JTAG and SWD transports. +# +source [find target/swj-dp.tcl] +source [find mem_helper.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME at32f4x +} + +set _ENDIAN little + +# Work-area is a space in RAM used for flash programming +# By default use 32kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x8000 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + if { [using_jtag] } { + # See STM Document RM0090 + # Section 38.6.3 - corresponds to Cortex-M4 r0p1 + set _CPUTAPID 0x4ba00477 + } { + set _CPUTAPID 0x2ba01477 + } +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu + +if {[using_jtag]} { + jtag newtap $_CHIPNAME bs -irlen 5 +} + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +set _FLASHNAME $_CHIPNAME.flash +# flash bank $_FLASHNAME artery 0 0 0 0 $_TARGETNAME +flash bank $_FLASHNAME artery 0x080000000 0 0 0 $_TARGETNAME + +#flash bank $_CHIPNAME.otp artery 0x1fff7800 0 0 0 $_TARGETNAME + +if { [info exists QUADSPI] && $QUADSPI } { + set a [llength [flash list]] + set _QSPINAME $_CHIPNAME.qspi + flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000 +} + +# JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz +# +# Since we may be running of an RC oscilator, we crank down the speed a +# bit more to be on the safe side. Perhaps superstition, but if are +# running off a crystal, we can run closer to the limit. Note +# that there can be a pretty wide band where things are more or less stable. +adapter speed 2000 + +adapter srst delay 100 +if {[using_jtag]} { + jtag_ntrst_delay 100 +} + +reset_config srst_nogate + +if {![using_hla]} { + # if srst is not fitted use SYSRESETREQ to + # perform a soft reset + cortex_m reset_config sysresetreq +} + +$_TARGETNAME configure -event examine-end { + # Enable debug during low power modes (uses more power) + # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP + mmw 0xE0042004 0x00000007 0 + + # Stop watchdog counters during halt + # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP + mmw 0xE0042008 0x00001800 0 +} + +tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000 + +lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu +proc _proc_pre_enable_$_CHIPNAME.tpiu {_chipname} { + targets $_chipname.cpu + + if { [$_chipname.tpiu cget -protocol] eq "sync" } { + switch [$_chipname.tpiu cget -port-width] { + 1 { + # Set TRACE_IOEN; TRACE_MODE to sync 1 bit; GPIOE[2-3] to AF0 + mmw 0xE0042004 0x00000060 0x000000c0 + mmw 0x40021020 0x00000000 0x0000ff00 + mmw 0x40021000 0x000000a0 0x000000f0 + mmw 0x40021008 0x000000f0 0x00000000 + } + 2 { + # Set TRACE_IOEN; TRACE_MODE to sync 2 bit; GPIOE[2-4] to AF0 + mmw 0xE0042004 0x000000a0 0x000000c0 + mmw 0x40021020 0x00000000 0x000fff00 + mmw 0x40021000 0x000002a0 0x000003f0 + mmw 0x40021008 0x000003f0 0x00000000 + } + 4 { + # Set TRACE_IOEN; TRACE_MODE to sync 4 bit; GPIOE[2-6] to AF0 + mmw 0xE0042004 0x000000e0 0x000000c0 + mmw 0x40021020 0x00000000 0x0fffff00 + mmw 0x40021000 0x00002aa0 0x00003ff0 + mmw 0x40021008 0x00003ff0 0x00000000 + } + } + } else { + # Set TRACE_IOEN; TRACE_MODE to async + mmw 0xE0042004 0x00000020 0x000000c0 + } +} + +$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_CHIPNAME" + +$_TARGETNAME configure -event reset-init { + # Configure PLL to boost clock to HSI x 4 (64 MHz) + mww 0x40023804 0x08012008 ;# RCC_PLLCFGR 16 Mhz /8 (M) * 128 (N) /4(P) + mww 0x40023C00 0x00000102 ;# FLASH_ACR = PRFTBE | 2(Latency) + mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON + sleep 10 ;# Wait for PLL to lock + mmw 0x40023808 0x00001000 0 ;# RCC_CFGR |= RCC_CFGR_PPRE1_DIV2 + mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL + + # Boost JTAG frequency + adapter speed 8000 +} + +$_TARGETNAME configure -event reset-start { + # Reduce speed since CPU speed will slow down to 16MHz with the reset + adapter speed 2000 +} diff --git a/demos/STM32/RT-AT32F435-ARTERY144/gdb.sh b/demos/STM32/RT-AT32F435-ARTERY144/gdb.sh new file mode 100755 index 000000000..d6f6f2b18 --- /dev/null +++ b/demos/STM32/RT-AT32F435-ARTERY144/gdb.sh @@ -0,0 +1,5 @@ +#!/bin/sh +#../../toolchain/gcc-arm-none-eabi-8-2018-q4-major/bin/arm-none-eabi-gdb $* +#../../toolchain/gcc-arm-none-eabi-9-2019-q4-major/bin/arm-none-eabi-gdb $* + +arm-none-eabi-gdb $* diff --git a/demos/STM32/RT-AT32F435-ARTERY144/openocd_artery.sh b/demos/STM32/RT-AT32F435-ARTERY144/openocd_artery.sh new file mode 100755 index 000000000..083b787bc --- /dev/null +++ b/demos/STM32/RT-AT32F435-ARTERY144/openocd_artery.sh @@ -0,0 +1,3 @@ +#!/bin/sh +openocd -f interface/cmsis-dap.cfg -f ./at32f4x.cfg -c '$_TARGETNAME configure -rtos auto' $* +