diff --git a/os/hal/ports/STM32/LLD/USARTv1/hal_serial_lld.c b/os/hal/ports/STM32/LLD/USARTv1/hal_serial_lld.c
index bfc804a38..cc6dc7ec1 100644
--- a/os/hal/ports/STM32/LLD/USARTv1/hal_serial_lld.c
+++ b/os/hal/ports/STM32/LLD/USARTv1/hal_serial_lld.c
@@ -112,7 +112,7 @@ static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
   uint32_t brr;
   USART_TypeDef *u = sdp->usart;
 
-  brr = (uint32_t)(sdp->clock / config->speed);
+  brr = (uint32_t)((sdp->clock + config->speed/2) / config->speed);
 
 #if defined(USART_CR1_OVER8)
   /* Correcting BRR value when oversampling by 8 instead of 16.
diff --git a/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c b/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c
index deadc1453..db9d1daaa 100644
--- a/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c
+++ b/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.c
@@ -256,7 +256,7 @@ static void usart_start(UARTDriver *uartp) {
   usart_stop(uartp);
 
   /* Baud rate setting.*/
-  fck = (uint32_t)(uartp->clock / uartp->config->speed);
+  fck = (uint32_t)((uartp->clock + uartp->config->speed/2) / uartp->config->speed);
 
   /* Correcting USARTDIV when oversampling by 8 instead of 16.
      Fraction is still 4 bits wide, but only lower 3 bits used.
diff --git a/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c b/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c
index 849a3ba89..8039140a1 100644
--- a/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c
+++ b/os/hal/ports/STM32/LLD/USARTv2/hal_serial_lld.c
@@ -243,14 +243,14 @@ static void usart_init(SerialDriver *sdp,
                   (clock <= config->speed * 4096U),
                   "invalid baud rate vs input clock");
 
-    brr = (uint32_t)(((uint64_t)clock * 256) / config->speed);
+    brr = (uint32_t)(((uint64_t)clock * 256 + config->speed/2) / config->speed);
 
     osalDbgAssert((brr >= 0x300) && (brr < 0x100000), "invalid BRR value");
   }
   else
 #endif
   {
-    brr = (uint32_t)(clock / config->speed);
+    brr = (uint32_t)((clock + config->speed/2) / config->speed);
 
     /* Correcting BRR value when oversampling by 8 instead of 16.
        Fraction is still 4 bits wide, but only lower 3 bits used.
diff --git a/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c b/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c
index 0effbd132..6c7df17de 100644
--- a/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c
+++ b/os/hal/ports/STM32/LLD/USARTv2/hal_uart_lld.c
@@ -262,7 +262,7 @@ static void usart_start(UARTDriver *uartp, uint32_t clock) {
   usart_stop(uartp);
 
   /* Baud rate setting.*/
-  fck = (uint32_t)(clock / uartp->config->speed);
+  fck = (uint32_t)((clock + uartp->config->speed/2) / uartp->config->speed);
 
   /* Correcting USARTDIV when oversampling by 8 instead of 16.
      Fraction is still 4 bits wide, but only lower 3 bits used.
diff --git a/os/hal/ports/STM32/LLD/USARTv3/hal_serial_lld.c b/os/hal/ports/STM32/LLD/USARTv3/hal_serial_lld.c
index 43bc57127..39026cc78 100644
--- a/os/hal/ports/STM32/LLD/USARTv3/hal_serial_lld.c
+++ b/os/hal/ports/STM32/LLD/USARTv3/hal_serial_lld.c
@@ -243,14 +243,14 @@ static void usart_init(SerialDriver *sdp,
                   (clock <= config->speed * 4096U),
                   "invalid baud rate vs input clock");
 
-    brr = (uint32_t)(((uint64_t)clock * 256) / config->speed);
+    brr = (uint32_t)(((uint64_t)clock * 256 + config->speed/2) / config->speed);
 
     osalDbgAssert((brr >= 0x300) && (brr < 0x100000), "invalid BRR value");
   }
   else
 #endif
   {
-    brr = (uint32_t)(clock / config->speed);
+    brr = (uint32_t)((clock + config->speed/2) / config->speed);
 
     /* Correcting BRR value when oversampling by 8 instead of 16.
        Fraction is still 4 bits wide, but only lower 3 bits used.
diff --git a/os/hal/ports/STM32/LLD/USARTv3/hal_uart_lld.c b/os/hal/ports/STM32/LLD/USARTv3/hal_uart_lld.c
index 2045be401..bbf6f86b2 100644
--- a/os/hal/ports/STM32/LLD/USARTv3/hal_uart_lld.c
+++ b/os/hal/ports/STM32/LLD/USARTv3/hal_uart_lld.c
@@ -262,7 +262,7 @@ static void usart_start(UARTDriver *uartp, uint32_t clock) {
   usart_stop(uartp);
 
   /* Baud rate setting.*/
-  fck = (uint32_t)(clock / uartp->config->speed);
+  fck = (uint32_t)((clock + uartp->config->speed/2) / uartp->config->speed);
 
   /* Correcting USARTDIV when oversampling by 8 instead of 16.
      Fraction is still 4 bits wide, but only lower 3 bits used.