STM32H7xx rework and update, to be completed.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@13304 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio
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@ -2,8 +2,6 @@
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******************************************************************************
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* @file stm32h7xx.h
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* @author MCD Application Team
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* @version V1.1.0
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* @date 31-August-2017
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* @brief CMSIS STM32H7xx Device Peripheral Access Layer Header File.
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*
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* The file is the unique include file that the application programmer
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@ -18,29 +16,13 @@
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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* <h2><center>© Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
|
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
|
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* this list of conditions and the following disclaimer in the documentation
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||||
* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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||||
* may be used to endorse or promote products derived from this software
|
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* without specific prior written permission.
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||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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@ -53,8 +35,8 @@
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* @{
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*/
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#ifndef __STM32H7xx_H
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#define __STM32H7xx_H
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#ifndef STM32H7xx_H
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#define STM32H7xx_H
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#ifdef __cplusplus
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extern "C" {
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@ -71,19 +53,37 @@
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#define STM32H7
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#endif /* STM32H7 */
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/* Uncomment the line below according to the target STM32H7 device used in your
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application
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*/
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#if !defined (STM32H743xx) && !defined (STM32H753xx)
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/* #define STM32H743xx */ /*!< STM32H743VI, STM32H743ZI, STM32H743II, STM32H743BI, STM32H743XI Devices */
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/* #define STM32H753xx */ /*!< STM32H753VI, STM32H753ZI, STM32H753II, STM32H753BI, STM32H753XI Devices */
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#if !defined (STM32H743xx) && !defined (STM32H753xx) && !defined (STM32H750xx) && !defined (STM32H742xx) && \
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!defined (STM32H745xx) && !defined (STM32H755xx) && !defined (STM32H747xx) && !defined (STM32H757xx) && \
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!defined (STM32H7A3xx) && !defined (STM32H7A3xxQ) && !defined (STM32H7B3xx) && !defined (STM32H7B3xxQ) && !defined (STM32H7B0xx) && !defined (STM32H7B0xxQ)
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/* #define STM32H742xx */ /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */
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/* #define STM32H743xx */ /*!< STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI Devices */
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/* #define STM32H753xx */ /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */
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/* #define STM32H750xx */ /*!< STM32H750V, STM32H750I, STM32H750X Devices */
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/* #define STM32H747xx */ /*!< STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI Devices */
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/* #define STM32H757xx */ /*!< STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI Devices */
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/* #define STM32H745xx */ /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices */
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/* #define STM32H755xx */ /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices */
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/* #define STM32H7B0xx */ /*!< STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ */
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/* #define STM32H7A3xx */ /*!< STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6 */
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/* #define STM32H7A3xxQ */ /*!< STM32H7A3QIY6Q, STM32H7A3IIK6Q, STM32H7A3IIT6Q, STM32H7A3LIH6Q, STM32H7A3VIH6Q, STM32H7A3VIT6Q, STM32H7A3AII6Q, STM32H7A3ZIT6Q */
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/* #define STM32H7B3xx */ /*!< STM32H7B3IIK6, STM32H7B3IIT6, STM32H7B3NIH6, STM32H7B3RIT6, STM32H7B3VIH6, STM32H7B3VIT6, STM32H7B3ZIT6 */
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/* #define STM32H7B3xxQ */ /*!< STM32H7B3QIY6Q, STM32H7B3IIK6Q, STM32H7B3IIT6Q, STM32H7B3LIH6Q, STM32H7B3VIH6Q, STM32H7B3VIT6Q, STM32H7B3AII6Q, STM32H7B3ZIT6Q */
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#endif
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/* Tip: To avoid modifying this file each time you need to switch between these
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devices, you can define the device in your toolchain compiler preprocessor.
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*/
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#if defined(DUAL_CORE) && !defined(CORE_CM4) && !defined(CORE_CM7)
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#error "Dual core device, please select CORE_CM4 or CORE_CM7"
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#endif
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#if !defined (USE_HAL_DRIVER)
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/**
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* @brief Comment the line below if you will not use the peripherals drivers.
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@ -94,16 +94,16 @@
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#endif /* USE_HAL_DRIVER */
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/**
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* @brief CMSIS Device version number V1.1.0
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* @brief CMSIS Device version number V1.7.0
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*/
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#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
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#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
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#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
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#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
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#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
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|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
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|(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
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|(__CMSIS_DEVICE_HAL_VERSION_RC))
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|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
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|(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
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|(__CMSIS_DEVICE_HAL_VERSION_RC))
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/**
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* @}
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@ -117,6 +117,30 @@
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#include "stm32h743xx.h"
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#elif defined(STM32H753xx)
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#include "stm32h753xx.h"
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#elif defined(STM32H750xx)
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#include "stm32h750xx.h"
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#elif defined(STM32H742xx)
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#include "stm32h742xx.h"
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#elif defined(STM32H745xx)
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#include "stm32h745xx.h"
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#elif defined(STM32H755xx)
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#include "stm32h755xx.h"
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#elif defined(STM32H747xx)
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#include "stm32h747xx.h"
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#elif defined(STM32H757xx)
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#include "stm32h757xx.h"
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#elif defined(STM32H7B0xx)
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#include "stm32h7b0xx.h"
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#elif defined(STM32H7B0xxQ)
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#include "stm32h7b0xxq.h"
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#elif defined(STM32H7A3xx)
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#include "stm32h7a3xx.h"
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#elif defined(STM32H7B3xx)
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#include "stm32h7b3xx.h"
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#elif defined(STM32H7A3xxQ)
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#include "stm32h7a3xxq.h"
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#elif defined(STM32H7B3xxQ)
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#include "stm32h7b3xxq.h"
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#else
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#error "Please select first the target STM32H7xx device used in your application (in stm32h7xx.h file)"
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#endif
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@ -185,7 +209,7 @@ typedef enum
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}
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#endif /* __cplusplus */
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#endif /* __STM32H7xx_H */
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#endif /* STM32H7xx_H */
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/**
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* @}
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*/
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@ -2,35 +2,17 @@
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******************************************************************************
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* @file system_stm32h7xx.h
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* @author MCD Application Team
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* @version V1.1.0
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* @date 31-August-2017
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* @brief CMSIS Cortex-Mx Device System Source File for STM32H7xx devices.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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* <h2><center>© Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
|
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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@ -46,8 +28,8 @@
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/**
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* @brief Define to prevent recursive inclusion
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*/
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#ifndef __SYSTEM_STM32H7XX_H
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#define __SYSTEM_STM32H7XX_H
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#ifndef SYSTEM_STM32H7XX_H
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#define SYSTEM_STM32H7XX_H
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#ifdef __cplusplus
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extern "C" {
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@ -111,7 +93,7 @@ extern void SystemCoreClockUpdate(void);
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}
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#endif
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#endif /*__SYSTEM_STM32H7XX_H */
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#endif /* SYSTEM_STM32H7XX_H */
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/**
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* @}
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@ -46,7 +46,13 @@
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/* If the device type is not externally defined, for example from the Makefile,
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then a file named board.h is included. This file must contain a device
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definition compatible with the vendor include file.*/
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#if !defined(STM32H743xx) && !defined(STM32H753xx)
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#if !defined(STM32H742xx) && !defined(STM32H750xx) && \
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!defined(STM32H743xx) && !defined(STM32H753xx) && \
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!defined(STM32H747xx) && !defined(STM32H757xx) && \
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!defined(STM32H745xx) && !defined(STM32H755xx) && \
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!defined(STM32H7B0xx) && !defined(STM32H7B0xxQ) && \
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!defined(STM32H7A3xx) && !defined(STM32H7A3xxQ) && \
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!defined(STM32H7B3xx) && !defined(STM32H7B3xxQ)
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#include "board.h"
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#endif
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|
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@ -132,7 +132,7 @@ void hal_lld_init(void) {
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board files.*/
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rccResetAHB1(~0);
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rccResetAHB2(~0);
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rccResetAHB3(~(RCC_AHB3RSTR_CPURST | RCC_AHB3RSTR_FMCRST));
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rccResetAHB3(~(RCC_AHB3RSTR_FMCRST));
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rccResetAHB4(~(STM32_GPIO_EN_MASK));
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rccResetAPB1L(~0);
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rccResetAPB1H(~0);
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@ -230,7 +230,10 @@ void stm32_clock_init(void) {
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/* Registers cleared to reset values.*/
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RCC->CR = RCC_CR_HSION; /* CR Reset value. */
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RCC->ICSCR = 0x40000000U; /* ICSCR Reset value. */
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RCC->HSICFGR = 0x40000000U; /* HSICFGR Reset value. */
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#if !defined(STM32_ENFORCE_H7_REV_V)
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RCC->CSICFGR = 0x20000000U; /* CSICFGR Reset value. */
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#endif
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RCC->CSR = 0x00000000U; /* CSR reset value. */
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RCC->PLLCFGR = 0x01FF0000U; /* PLLCFGR reset value. */
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@ -367,7 +370,8 @@ void stm32_clock_init(void) {
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STM32_I2C4SEL | STM32_LPUART1SEL;
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/* Flash setup.*/
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FLASH->ACR = FLASH_ACR_WRHIGHFREQ_2 | STM32_FLASHBITS;
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FLASH->ACR = FLASH_ACR_WRHIGHFREQ_1 | FLASH_ACR_WRHIGHFREQ_0 |
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STM32_FLASHBITS;
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while ((FLASH->ACR & FLASH_ACR_LATENCY) !=
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(STM32_FLASHBITS & FLASH_ACR_LATENCY)) {
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}
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|
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@ -47,11 +47,29 @@
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* @name Platform identification macros
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* @{
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*/
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#if defined(STM32H743xx) || defined(__DOXYGEN__)
|
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#define PLATFORM_NAME "STM32H743 Very High Performance with DSP and FPU"
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#if defined(STM32H742xx) || defined(__DOXYGEN__)
|
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#define PLATFORM_NAME "STM32H742 Single Core Very High Performance with DSP and FPU"
|
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#elif defined(STM32H743xx) || defined(__DOXYGEN__)
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#define PLATFORM_NAME "STM32H743 Single Core Very High Performance with DSP and FPU"
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|
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#elif defined(STM32H753xx)
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#define PLATFORM_NAME "STM32H753 Very High Performance with DSP and FPU"
|
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#define PLATFORM_NAME "STM32H753 Single Core Very High Performance with DSP and FPU"
|
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|
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#elif defined(STM32H745xx) || defined(__DOXYGEN__)
|
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#define PLATFORM_NAME "STM32H745 Dual Core Very High Performance with DSP and FPU"
|
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|
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#elif defined(STM32H755xx)
|
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#define PLATFORM_NAME "STM32H755 Dual Core Very High Performance with DSP and FPU"
|
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|
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#elif defined(STM32H747xx) || defined(__DOXYGEN__)
|
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#define PLATFORM_NAME "STM32H747 Dual Core Very High Performance with DSP and FPU"
|
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|
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#elif defined(STM32H757xx)
|
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#define PLATFORM_NAME "STM32H757 Dual Core Very High Performance with DSP and FPU"
|
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|
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#elif defined(STM32H750xx)
|
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#define PLATFORM_NAME "STM32H750 Value Line Very High Performance with DSP and FPU"
|
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|
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#else
|
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#error "STM32H7xx device not specified"
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@ -66,6 +84,7 @@
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#endif
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/** @} */
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#if !defined(STM32_ENFORCE_H7_REV_V)
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/**
|
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* @name Absolute Maximum Ratings
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* @{
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@ -73,12 +92,12 @@
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/**
|
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* @brief Absolute maximum system clock.
|
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*/
|
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#define STM32_SYSCLK_MAX 400000000
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#define STM32_SYSCLK_MAX 480000000
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|
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/**
|
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* @brief Absolute maximum HCLK clock.
|
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*/
|
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#define STM32_HCLK_MAX 200000000
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#define STM32_HCLK_MAX (STM32_SYSCLK_MAX / 2)
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|
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/**
|
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* @brief Maximum HSE clock frequency.
|
||||
|
|
@ -143,7 +162,7 @@
|
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/**
|
||||
* @brief Minimum PLLs VCO clock frequency.
|
||||
*/
|
||||
#define STM32_PLLVCO_MIN 150000000
|
||||
#define STM32_PLLVCO_MIN 150000000 /* DS says 192, RM says 150. */
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||||
|
||||
/**
|
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* @brief Threshold PLLs clock frequency.
|
||||
|
|
@ -153,7 +172,7 @@
|
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/**
|
||||
* @brief Maximum PLLs VCOH clock frequency.
|
||||
*/
|
||||
#define STM32_PLLVCO_MAX 836000000
|
||||
#define STM32_PLLVCO_MAX 960000000
|
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|
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/**
|
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* @brief Maximum APB1 clock frequency.
|
||||
|
|
@ -178,19 +197,48 @@
|
|||
/**
|
||||
* @brief Maximum SPI1, SPI2 and SPI3 clock frequency.
|
||||
*/
|
||||
#define STM32_SPI123_MAX 133000000
|
||||
#define STM32_SPI123_MAX 200000000
|
||||
|
||||
/**
|
||||
* @brief Maximum SPI4, SPI5 and SPI6 clock frequency.
|
||||
*/
|
||||
#define STM32_SPI456_MAX 100000000
|
||||
#define STM32_SPI456_MAX 125000000
|
||||
|
||||
/**
|
||||
* @brief Maximum ADC clock frequency.
|
||||
*/
|
||||
#define STM32_ADCCLK_MAX 36000000
|
||||
#define STM32_ADCCLK_MAX 100000000
|
||||
/** @} */
|
||||
|
||||
#else /* defined(STM32_ENFORCE_H7_REV_V) */
|
||||
|
||||
#define STM32_SYSCLK_MAX 400000000
|
||||
#define STM32_HCLK_MAX (STM32_SYSCLK_MAX / 2)
|
||||
#define STM32_HSECLK_MAX 48000000
|
||||
#define STM32_HSECLK_BYP_MAX 50000000
|
||||
#define STM32_HSECLK_MIN 4000000
|
||||
#define STM32_HSECLK_BYP_MIN 4000000
|
||||
#define STM32_LSE_CK_MAX 32768
|
||||
#define STM32_LSE_CK_BYP_MAX 1000000
|
||||
#define STM32_LSE_CK_MIN 32768
|
||||
#define STM32_PLLIN_MIN 1000000
|
||||
#define STM32_PLLIN_THRESHOLD1 2000000
|
||||
#define STM32_PLLIN_THRESHOLD2 4000000
|
||||
#define STM32_PLLIN_THRESHOLD3 8000000
|
||||
#define STM32_PLLIN_MAX 16000000
|
||||
#define STM32_PLLVCO_MIN 150000000
|
||||
#define STM32_PLLVCO_THRESHOLD 420000000
|
||||
#define STM32_PLLVCO_MAX 836000000
|
||||
#define STM32_PCLK1_MAX (STM32_HCLK_MAX / 2)
|
||||
#define STM32_PCLK2_MAX (STM32_HCLK_MAX / 2)
|
||||
#define STM32_PCLK3_MAX (STM32_HCLK_MAX / 2)
|
||||
#define STM32_PCLK4_MAX (STM32_HCLK_MAX / 2)
|
||||
#define STM32_SPI123_MAX 133000000
|
||||
#define STM32_SPI456_MAX 100000000
|
||||
#define STM32_ADCCLK_MAX 36000000
|
||||
|
||||
#endif /* defined(STM32_ENFORCE_H7_REV_V) */
|
||||
|
||||
/**
|
||||
* @name Internal clock sources frequencies
|
||||
* @{
|
||||
|
|
@ -288,6 +336,9 @@
|
|||
* @name Configuration switches to be used in @p mcuconf.h
|
||||
* @{
|
||||
*/
|
||||
#define STM32_ODEN_DISABLED 0U
|
||||
#define STM32_ODEN_ENABLED (SYSCFG_PWRCR_ODEN)
|
||||
|
||||
#define STM32_VOS_SCALE3 (PWR_D3CR_VOS_0)
|
||||
#define STM32_VOS_SCALE2 (PWR_D3CR_VOS_1)
|
||||
#define STM32_VOS_SCALE1 (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0)
|
||||
|
|
@ -601,6 +652,13 @@
|
|||
#define STM32_VOS STM32_VOS_SCALE1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ODEN setting.
|
||||
*/
|
||||
#if !defined(STM32_ODEN) || defined(__DOXYGEN__)
|
||||
#define STM32_ODEN STM32_ODEN_DISABLED
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the HSI clock source.
|
||||
*/
|
||||
|
|
@ -1224,11 +1282,38 @@
|
|||
#error "Using a wrong mcuconf.h file, STM32H7xx_MCUCONF not defined"
|
||||
#endif
|
||||
|
||||
#if (defined(STM32H743xx) || defined(STM32H753xx)) && \
|
||||
!defined(STM32H743_MCUCONF)
|
||||
#if defined(STM32H750xx)&& !defined(STM32H750_MCUCONF)
|
||||
#error "Using a wrong mcuconf.h file, STM32H750_MCUCONF not defined"
|
||||
#endif
|
||||
|
||||
#if defined(STM32H742xx)&& !defined(STM32H742_MCUCONF)
|
||||
#error "Using a wrong mcuconf.h file, STM32H742_MCUCONF not defined"
|
||||
#endif
|
||||
|
||||
#if defined(STM32H743xx)&& !defined(STM32H743_MCUCONF)
|
||||
#error "Using a wrong mcuconf.h file, STM32H743_MCUCONF not defined"
|
||||
#endif
|
||||
|
||||
#if defined(STM32H753xx)&& !defined(STM32H753_MCUCONF)
|
||||
#error "Using a wrong mcuconf.h file, STM32H753_MCUCONF not defined"
|
||||
#endif
|
||||
|
||||
#if defined(STM32H745xx)&& !defined(STM32H745_MCUCONF)
|
||||
#error "Using a wrong mcuconf.h file, STM32H745_MCUCONF not defined"
|
||||
#endif
|
||||
|
||||
#if defined(STM32H755xx)&& !defined(STM32H755_MCUCONF)
|
||||
#error "Using a wrong mcuconf.h file, STM32H755_MCUCONF not defined"
|
||||
#endif
|
||||
|
||||
#if defined(STM32H747xx)&& !defined(STM32H747_MCUCONF)
|
||||
#error "Using a wrong mcuconf.h file, STM32H747_MCUCONF not defined"
|
||||
#endif
|
||||
|
||||
#if defined(STM32H757xx)&& !defined(STM32H757_MCUCONF)
|
||||
#error "Using a wrong mcuconf.h file, STM32H757_MCUCONF not defined"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Board file checks.
|
||||
*/
|
||||
|
|
@ -1243,14 +1328,30 @@
|
|||
#endif
|
||||
|
||||
/**
|
||||
* @name Constants depending on VOS setting
|
||||
* @name Constants depending on VOS and ODEN setting
|
||||
* @{
|
||||
*/
|
||||
#if (STM32_ODEN == STM32_ODEN_ENABLED) || defined(__DOXYGEN__)
|
||||
|
||||
#if (STM32_VOS == STM32_VOS_SCALE1) || defined(__DOXYGEN__)
|
||||
#define STM32_0WS_THRESHOLD 70000000U
|
||||
#define STM32_1WS_THRESHOLD 140000000U
|
||||
#define STM32_2WS_THRESHOLD 210000000U
|
||||
#define STM32_3WS_THRESHOLD 0U
|
||||
#define STM32_3WS_THRESHOLD 225000000U
|
||||
#define STM32_4WS_THRESHOLD 240000000U
|
||||
#define STM32_PLLOUT_MAX 480000000U
|
||||
#define STM32_PLLOUT_MIN 1500000U
|
||||
#else
|
||||
#error "invalid STM32_VOS setting specified with STM32_ODEN enabled"
|
||||
#endif
|
||||
|
||||
#elif STM32_ODEN == STM32_ODEN_DISABLED
|
||||
|
||||
#if STM32_VOS == STM32_VOS_SCALE1
|
||||
#define STM32_0WS_THRESHOLD 70000000U
|
||||
#define STM32_1WS_THRESHOLD 140000000U
|
||||
#define STM32_2WS_THRESHOLD 210000000U
|
||||
#define STM32_3WS_THRESHOLD 225000000U
|
||||
#define STM32_4WS_THRESHOLD 0U
|
||||
#define STM32_PLLOUT_MAX 400000000U
|
||||
#define STM32_PLLOUT_MIN 1500000U
|
||||
|
|
@ -1259,7 +1360,7 @@
|
|||
#define STM32_0WS_THRESHOLD 55000000U
|
||||
#define STM32_1WS_THRESHOLD 110000000U
|
||||
#define STM32_2WS_THRESHOLD 165000000U
|
||||
#define STM32_3WS_THRESHOLD 220000000U
|
||||
#define STM32_3WS_THRESHOLD 225000000U
|
||||
#define STM32_4WS_THRESHOLD 0U
|
||||
#define STM32_PLLOUT_MAX 300000000U
|
||||
#define STM32_PLLOUT_MIN 1500000U
|
||||
|
|
@ -1276,6 +1377,10 @@
|
|||
#else
|
||||
#error "invalid STM32_VOS setting specified"
|
||||
#endif
|
||||
|
||||
#else
|
||||
#error "invalid STM32_ODEN setting specified"
|
||||
#endif
|
||||
/** @} */
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -200,6 +200,15 @@
|
|||
|
||||
#define STM32_QUADSPI1_NUMBER 92
|
||||
|
||||
/*
|
||||
* SDMMC units.
|
||||
*/
|
||||
#define STM32_SDMMC1_HANDLER Vector104
|
||||
#define STM32_SDMMC2_HANDLER Vector230
|
||||
|
||||
#define STM32_SDMMC1_NUMBER 49
|
||||
#define STM32_SDMMC2_NUMBER 131
|
||||
|
||||
/*
|
||||
* SPI units.
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -33,13 +33,16 @@
|
|||
#define STM32_HAS_RNG1 TRUE
|
||||
|
||||
/**
|
||||
* @name STM32F7xx capabilities
|
||||
* @name STM32H7xx capabilities
|
||||
* @{
|
||||
*/
|
||||
/*===========================================================================*/
|
||||
/* STM32H743xx, STM32H753xx. */
|
||||
/* STM32H743xx, STM32H753xx, STM32H745xx, STM32H755xx, STM32H747xx, */
|
||||
/* STM32H757xx. */
|
||||
/*===========================================================================*/
|
||||
#if defined(STM32H743xx) || defined(STM32H753xx) || \
|
||||
defined(STM32H745xx) || defined(STM32H755xx) || \
|
||||
defined(STM32H747xx) || defined(STM32H757xx) || \
|
||||
defined(__DOXYGEN__)
|
||||
|
||||
/* ADC attributes.*/
|
||||
|
|
@ -53,9 +56,8 @@
|
|||
#define STM32_HAS_SDADC3 FALSE
|
||||
|
||||
/* CAN attributes.*/
|
||||
#define STM32_HAS_CAN1 FALSE
|
||||
#define STM32_HAS_CAN2 FALSE
|
||||
#define STM32_HAS_CAN3 FALSE
|
||||
#define STM32_HAS_FDCAN1 TRUE
|
||||
#define STM32_HAS_FDCAN2 TRUE
|
||||
|
||||
/* DAC attributes.*/
|
||||
#define STM32_HAS_DAC1_CH1 TRUE
|
||||
|
|
@ -73,6 +75,9 @@
|
|||
#define STM32_HAS_DMA1 TRUE
|
||||
#define STM32_HAS_DMA2 TRUE
|
||||
|
||||
/* MDMA attributes.*/
|
||||
#define STM32_HAS_MDMA1 TRUE
|
||||
|
||||
/* ETH attributes.*/
|
||||
#define STM32_HAS_ETH TRUE
|
||||
|
||||
|
|
@ -125,12 +130,7 @@
|
|||
|
||||
/* SDMMC attributes.*/
|
||||
#define STM32_HAS_SDMMC1 TRUE
|
||||
#define STM32_SDMMC1_HANDLER Vector104
|
||||
#define STM32_SDMMC1_NUMBER 49
|
||||
|
||||
#define STM32_HAS_SDMMC2 TRUE
|
||||
#define STM32_SDMMC2_HANDLER Vector230
|
||||
#define STM32_SDMMC2_NUMBER 131
|
||||
|
||||
/* SPI attributes.*/
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
|
|
@ -267,6 +267,233 @@
|
|||
#endif /* defined(STM32H743xx) || defined(STM32H753xx) */
|
||||
/** @} */
|
||||
|
||||
/*===========================================================================*/
|
||||
/* STM32H750xx. */
|
||||
/*===========================================================================*/
|
||||
#if defined(STM32H750xx) || \
|
||||
defined(__DOXYGEN__)
|
||||
|
||||
/* ADC attributes.*/
|
||||
#define STM32_HAS_ADC1 TRUE
|
||||
#define STM32_HAS_ADC2 TRUE
|
||||
#define STM32_HAS_ADC3 FALSE
|
||||
#define STM32_HAS_ADC4 FALSE
|
||||
|
||||
#define STM32_HAS_SDADC1 FALSE
|
||||
#define STM32_HAS_SDADC2 FALSE
|
||||
#define STM32_HAS_SDADC3 FALSE
|
||||
|
||||
/* CAN attributes.*/
|
||||
#define STM32_HAS_FDCAN1 TRUE
|
||||
#define STM32_HAS_FDCAN2 TRUE
|
||||
|
||||
/* DAC attributes.*/
|
||||
#define STM32_HAS_DAC1_CH1 TRUE
|
||||
#define STM32_HAS_DAC1_CH2 TRUE
|
||||
#define STM32_HAS_DAC2_CH1 FALSE
|
||||
#define STM32_HAS_DAC2_CH2 FALSE
|
||||
|
||||
/* BDMA attributes.*/
|
||||
#define STM32_HAS_BDMA1 TRUE
|
||||
|
||||
/* DMA attributes.*/
|
||||
#define STM32_ADVANCED_DMA TRUE
|
||||
#define STM32_DMA_SUPPORTS_DMAMUX TRUE
|
||||
|
||||
#define STM32_HAS_DMA1 TRUE
|
||||
#define STM32_HAS_DMA2 TRUE
|
||||
|
||||
/* MDMA attributes.*/
|
||||
#define STM32_HAS_MDMA1 TRUE
|
||||
|
||||
/* ETH attributes.*/
|
||||
#define STM32_HAS_ETH TRUE
|
||||
|
||||
/* EXTI attributes.*/
|
||||
#define STM32_EXTI_ENHANCED
|
||||
#define STM32_EXTI_NUM_LINES 34
|
||||
#define STM32_EXTI_IMR1_MASK 0x1F800000U
|
||||
#define STM32_EXTI_IMR2_MASK 0xFFFFFFFCU
|
||||
|
||||
/* GPIO attributes.*/
|
||||
#define STM32_HAS_GPIOA TRUE
|
||||
#define STM32_HAS_GPIOB TRUE
|
||||
#define STM32_HAS_GPIOC TRUE
|
||||
#define STM32_HAS_GPIOD TRUE
|
||||
#define STM32_HAS_GPIOE TRUE
|
||||
#define STM32_HAS_GPIOH TRUE
|
||||
#define STM32_HAS_GPIOF TRUE
|
||||
#define STM32_HAS_GPIOG TRUE
|
||||
#define STM32_HAS_GPIOI TRUE
|
||||
#define STM32_HAS_GPIOJ TRUE
|
||||
#define STM32_HAS_GPIOK TRUE
|
||||
#define STM32_GPIO_EN_MASK (RCC_AHB4ENR_GPIOAEN | \
|
||||
RCC_AHB4ENR_GPIOBEN | \
|
||||
RCC_AHB4ENR_GPIOCEN | \
|
||||
RCC_AHB4ENR_GPIODEN | \
|
||||
RCC_AHB4ENR_GPIOEEN | \
|
||||
RCC_AHB4ENR_GPIOFEN | \
|
||||
RCC_AHB4ENR_GPIOGEN | \
|
||||
RCC_AHB4ENR_GPIOHEN | \
|
||||
RCC_AHB4ENR_GPIOIEN | \
|
||||
RCC_AHB4ENR_GPIOJEN | \
|
||||
RCC_AHB4ENR_GPIOKEN)
|
||||
|
||||
/* I2C attributes.*/
|
||||
#define STM32_HAS_I2C1 TRUE
|
||||
#define STM32_HAS_I2C2 TRUE
|
||||
#define STM32_HAS_I2C3 TRUE
|
||||
#define STM32_HAS_I2C4 TRUE
|
||||
|
||||
/* QUADSPI attributes.*/
|
||||
#define STM32_HAS_QUADSPI1 TRUE
|
||||
#define STM32_HAS_QUADSPI2 FALSE
|
||||
|
||||
/* RTC attributes.*/
|
||||
#define STM32_HAS_RTC TRUE
|
||||
#define STM32_RTC_HAS_SUBSECONDS TRUE
|
||||
#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE
|
||||
#define STM32_RTC_NUM_ALARMS 2
|
||||
#define STM32_RTC_HAS_INTERRUPTS FALSE
|
||||
|
||||
/* SDMMC attributes.*/
|
||||
#define STM32_HAS_SDMMC1 TRUE
|
||||
#define STM32_HAS_SDMMC2 TRUE
|
||||
|
||||
/* SPI attributes.*/
|
||||
#define STM32_HAS_SPI1 TRUE
|
||||
#define STM32_SPI1_SUPPORTS_I2S TRUE
|
||||
#define STM32_SPI1_I2S_FULLDUPLEX TRUE
|
||||
|
||||
#define STM32_HAS_SPI2 TRUE
|
||||
#define STM32_SPI2_SUPPORTS_I2S TRUE
|
||||
#define STM32_SPI2_I2S_FULLDUPLEX TRUE
|
||||
|
||||
#define STM32_HAS_SPI3 TRUE
|
||||
#define STM32_SPI3_SUPPORTS_I2S TRUE
|
||||
#define STM32_SPI3_I2S_FULLDUPLEX TRUE
|
||||
|
||||
#define STM32_HAS_SPI4 TRUE
|
||||
#define STM32_SPI4_SUPPORTS_I2S FALSE
|
||||
|
||||
#define STM32_HAS_SPI5 TRUE
|
||||
#define STM32_SPI5_SUPPORTS_I2S FALSE
|
||||
|
||||
#define STM32_HAS_SPI6 TRUE
|
||||
#define STM32_SPI6_SUPPORTS_I2S FALSE
|
||||
|
||||
/* TIM attributes.*/
|
||||
#define STM32_TIM_MAX_CHANNELS 6
|
||||
|
||||
#define STM32_HAS_TIM1 TRUE
|
||||
#define STM32_TIM1_IS_32BITS FALSE
|
||||
#define STM32_TIM1_CHANNELS 6
|
||||
|
||||
#define STM32_HAS_TIM2 TRUE
|
||||
#define STM32_TIM2_IS_32BITS TRUE
|
||||
#define STM32_TIM2_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM3 TRUE
|
||||
#define STM32_TIM3_IS_32BITS FALSE
|
||||
#define STM32_TIM3_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM4 TRUE
|
||||
#define STM32_TIM4_IS_32BITS FALSE
|
||||
#define STM32_TIM4_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM5 TRUE
|
||||
#define STM32_TIM5_IS_32BITS TRUE
|
||||
#define STM32_TIM5_CHANNELS 4
|
||||
|
||||
#define STM32_HAS_TIM6 TRUE
|
||||
#define STM32_TIM6_IS_32BITS FALSE
|
||||
#define STM32_TIM6_CHANNELS 0
|
||||
|
||||
#define STM32_HAS_TIM7 TRUE
|
||||
#define STM32_TIM7_IS_32BITS FALSE
|
||||
#define STM32_TIM7_CHANNELS 0
|
||||
|
||||
#define STM32_HAS_TIM8 TRUE
|
||||
#define STM32_TIM8_IS_32BITS FALSE
|
||||
#define STM32_TIM8_CHANNELS 6
|
||||
|
||||
#define STM32_HAS_TIM12 TRUE
|
||||
#define STM32_TIM12_IS_32BITS FALSE
|
||||
#define STM32_TIM12_CHANNELS 2
|
||||
|
||||
#define STM32_HAS_TIM13 TRUE
|
||||
#define STM32_TIM13_IS_32BITS FALSE
|
||||
#define STM32_TIM13_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM14 TRUE
|
||||
#define STM32_TIM14_IS_32BITS FALSE
|
||||
#define STM32_TIM14_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM15 FALSE
|
||||
#define STM32_TIM15_IS_32BITS FALSE
|
||||
#define STM32_TIM15_CHANNELS 2
|
||||
|
||||
#define STM32_HAS_TIM16 FALSE
|
||||
#define STM32_TIM16_IS_32BITS FALSE
|
||||
#define STM32_TIM16_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM17 FALSE
|
||||
#define STM32_TIM17_IS_32BITS FALSE
|
||||
#define STM32_TIM17_CHANNELS 1
|
||||
|
||||
#define STM32_HAS_TIM9 FALSE
|
||||
#define STM32_HAS_TIM10 FALSE
|
||||
#define STM32_HAS_TIM11 FALSE
|
||||
#define STM32_HAS_TIM18 FALSE
|
||||
#define STM32_HAS_TIM19 FALSE
|
||||
#define STM32_HAS_TIM20 FALSE
|
||||
#define STM32_HAS_TIM21 FALSE
|
||||
#define STM32_HAS_TIM22 FALSE
|
||||
|
||||
/* USART attributes.*/
|
||||
#define STM32_HAS_USART1 TRUE
|
||||
#define STM32_HAS_USART2 TRUE
|
||||
#define STM32_HAS_USART3 TRUE
|
||||
#define STM32_HAS_UART4 TRUE
|
||||
#define STM32_HAS_UART5 TRUE
|
||||
#define STM32_HAS_USART6 TRUE
|
||||
#define STM32_HAS_UART7 TRUE
|
||||
#define STM32_HAS_UART8 TRUE
|
||||
#define STM32_HAS_LPUART1 FALSE
|
||||
|
||||
/* USB attributes.*/
|
||||
#define STM32_OTG_STEPPING 2
|
||||
#define STM32_HAS_OTG1 TRUE
|
||||
#define STM32_OTG1_ENDPOINTS 8
|
||||
|
||||
#define STM32_HAS_OTG2 TRUE
|
||||
#define STM32_OTG2_ENDPOINTS 8
|
||||
|
||||
#define STM32_HAS_USB FALSE
|
||||
|
||||
/* IWDG attributes.*/
|
||||
#define STM32_HAS_IWDG TRUE
|
||||
#define STM32_IWDG_IS_WINDOWED TRUE
|
||||
|
||||
/* LTDC attributes.*/
|
||||
#define STM32_HAS_LTDC TRUE
|
||||
|
||||
/* DMA2D attributes.*/
|
||||
#define STM32_HAS_DMA2D TRUE
|
||||
|
||||
/* FSMC attributes.*/
|
||||
#define STM32_HAS_FSMC TRUE
|
||||
#define STM32_FSMC_IS_FMC TRUE
|
||||
|
||||
/* CRC attributes.*/
|
||||
#define STM32_HAS_CRC TRUE
|
||||
#define STM32_CRC_PROGRAMMABLE TRUE
|
||||
|
||||
/* DCMI attributes.*/
|
||||
#define STM32_HAS_DCMI TRUE
|
||||
|
||||
#endif /* defined(STM32H750xx) */
|
||||
|
||||
#endif /* STM32_REGISTRY_H */
|
||||
|
||||
/** @} */
|
||||
|
|
|
|||
|
|
@ -43,6 +43,7 @@
|
|||
*/
|
||||
|
||||
#define STM32H7xx_MCUCONF
|
||||
#define STM32H742_MCUCONF
|
||||
#define STM32H743_MCUCONF
|
||||
#define STM32H753_MCUCONF
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue