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Removed oscillator stabilization delay on STM32 LSE and HSE when bypass mode is enabled. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@16306 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2023-07-01 08:22:28 +00:00
parent 0243fce2db
commit 283b61422b
4 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
os/hal/ports/STM32/LLD/RCCv1/stm32_hse.inc
View File

@ -96,10 +96,10 @@ __STATIC_INLINE void hse_enable(void) {
RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP; RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
#else #else
RCC->CR |= RCC_CR_HSEON; RCC->CR |= RCC_CR_HSEON;
#endif
while ((RCC->CR & RCC_CR_HSERDY) == 0U) { while ((RCC->CR & RCC_CR_HSERDY) == 0U) {
/* Waiting for HSE activation.*/ /* Waiting for HSE activation.*/
} }
#endif
} }
__STATIC_INLINE void hse_disable(void) { __STATIC_INLINE void hse_disable(void) {

2
os/hal/ports/STM32/LLD/RCCv1/stm32_lse.inc
View File

@ -97,11 +97,11 @@ __STATIC_INLINE void lse_init(void) {
#else #else
/* No LSE Bypass.*/ /* No LSE Bypass.*/
RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN; RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN;
#endif
while ((RCC->BDCR & (RCC_BDCR_LSESYSRDY | RCC_BDCR_LSERDY)) != while ((RCC->BDCR & (RCC_BDCR_LSESYSRDY | RCC_BDCR_LSERDY)) !=
(RCC_BDCR_LSESYSRDY | RCC_BDCR_LSERDY)) { (RCC_BDCR_LSESYSRDY | RCC_BDCR_LSERDY)) {
} }
#endif #endif
#endif
} }
/*===========================================================================*/ /*===========================================================================*/

2
os/xhal/ports/STM32/LLD/RCCv1/stm32_hse.inc
View File

@ -96,10 +96,10 @@ __STATIC_INLINE void hse_enable(void) {
RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP; RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
#else #else
RCC->CR |= RCC_CR_HSEON; RCC->CR |= RCC_CR_HSEON;
#endif
while ((RCC->CR & RCC_CR_HSERDY) == 0U) { while ((RCC->CR & RCC_CR_HSERDY) == 0U) {
/* Waiting for HSE activation.*/ /* Waiting for HSE activation.*/
} }
#endif
} }
__STATIC_INLINE void hse_disable(void) { __STATIC_INLINE void hse_disable(void) {

2
os/xhal/ports/STM32/LLD/RCCv1/stm32_lse.inc
View File

@ -97,11 +97,11 @@ __STATIC_INLINE void lse_init(void) {
#else #else
/* No LSE Bypass.*/ /* No LSE Bypass.*/
RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN; RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN;
#endif
while ((RCC->BDCR & (RCC_BDCR_LSESYSRDY | RCC_BDCR_LSERDY)) != while ((RCC->BDCR & (RCC_BDCR_LSESYSRDY | RCC_BDCR_LSERDY)) !=
(RCC_BDCR_LSESYSRDY | RCC_BDCR_LSERDY)) { (RCC_BDCR_LSESYSRDY | RCC_BDCR_LSERDY)) {
} }
#endif #endif
#endif
} }
/*===========================================================================*/ /*===========================================================================*/