Fixed bug 3019738.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2034 35acf78f-673a-0410-8e92-d51de3d6d3f4

docs/reports/STM32F103-72.txt

@@ -95,35 +95,35 @@ Settings: SYSCLK=72, ACR=0x12 (2 wait states)
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.1 (Benchmark, messages #1)
---- Score : 250284 msgs/S, 500568 ctxswc/S
+--- Score : 252041 msgs/S, 504082 ctxswc/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.2 (Benchmark, messages #2)
---- Score : 203498 msgs/S, 406996 ctxswc/S
+--- Score : 204649 msgs/S, 409298 ctxswc/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.3 (Benchmark, messages #3)
---- Score : 203498 msgs/S, 406996 ctxswc/S
+--- Score : 204649 msgs/S, 409298 ctxswc/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.4 (Benchmark, context switch)
---- Score : 838936 ctxswc/S
+--- Score : 848856 ctxswc/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.5 (Benchmark, threads, full cycle)
---- Score : 159280 threads/S
+--- Score : 160345 threads/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.6 (Benchmark, threads, create only)
---- Score : 228043 threads/S
+--- Score : 230238 threads/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.7 (Benchmark, mass reschedule, 5 threads)
---- Score : 62305 reschedules/S, 373830 ctxswc/S
+--- Score : 62631 reschedules/S, 375786 ctxswc/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.8 (Benchmark, round robin context switching)
---- Score : 481292 ctxswc/S
+--- Score : 484540 ctxswc/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.9 (Benchmark, I/O Queues throughput)

os/ports/GCC/ARMCMx/chcore_v7m.c

@@ -30,16 +30,15 @@
 /**
  * @brief   Internal context stacking.
  */
-#define PUSH_CONTEXT(sp) {                                                  \
+#define PUSH_CONTEXT() {                                                    \
   asm volatile ("push    {r4, r5, r6, r7, r8, r9, r10, r11, lr}");          \
 }
 
 /**
  * @brief   Internal context unstacking.
  */
-#define POP_CONTEXT(sp) {                                                   \
-  asm volatile ("pop     {r4, r5, r6, r7, r8, r9, r10, r11, pc}"            \
-                :  : "r" (sp));                                             \
+#define POP_CONTEXT() {                                                     \
+  asm volatile ("pop     {r4, r5, r6, r7, r8, r9, r10, r11, pc}");          \
 }
 
 #if !CH_OPTIMIZE_SPEED
@@ -137,21 +136,21 @@ void _port_switch_from_isr(void) {
 __attribute__((naked))
 #endif
 void port_switch(Thread *ntp, Thread *otp) {
-  register struct intctx *r13 asm ("r13");
 
-  /* Stack overflow check, if enabled.*/
 #if CH_DBG_ENABLE_STACK_CHECK
+  /* Stack overflow check, if enabled.*/
+  register struct intctx *r13 asm ("r13");
   if ((void *)(r13 - 1) < (void *)(otp + 1))
     asm volatile ("movs    r0, #0                               \n\t"
                   "b       chDbgPanic");
 #endif /* CH_DBG_ENABLE_STACK_CHECK */
 
-  PUSH_CONTEXT(r13);
+  PUSH_CONTEXT();
 
-  otp->p_ctx.r13 = r13;
-  r13 = ntp->p_ctx.r13;
+  asm volatile ("str     sp, [%1, #12]                          \n\t"
+                "ldr     sp, [%0, #12]" : : "r" (ntp), "r" (otp));
 
-  POP_CONTEXT(r13);
+  POP_CONTEXT();
 }
 
 /**

readme.txt

@@ -59,6 +59,10 @@
 *****************************************************************************
 
 *** 2.1.0 ***
+- FIX: Fixed non functional CH_DBG_ENABLE_STACK_CHECK option in the Cortex-M3
+  caused by GCC 4.5.0, the fix also improves the context switch performance
+  because GCC 4.5.0 apparently was generating useless instructions within the
+  very critical context switch code (bug 3019738)(backported in 2.0.1).
 - FIX: Fixed insufficient stack space assigned to the idle thread in
   Cortex-M3 port (bug 3019594)(backported in 2.0.1).
 - FIX: Fixed missing check in chIQReadTimeout() and chIQWriteTimeout() (bug