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Fixed HSISYS calculation and missing SWs. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@14422 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
This commit is contained in:
Giovanni Di Sirio 2021-05-23 10:40:17 +00:00
parent eb07eec9a0
commit 296783fd57
2 changed files with 40 additions and 27 deletions
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17
os/hal/ports/STM32/STM32G0xx/hal_lld.c
View File

@ -215,10 +215,10 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
2U, 4U, 8U, 16U, 64U, 128U, 256U, 512U}; 2U, 4U, 8U, 16U, 64U, 128U, 256U, 512U};
static const uint32_t pprediv[16] = {1U, 1U, 1U, 1U, 2U, 4U, 8U, 16U}; static const uint32_t pprediv[16] = {1U, 1U, 1U, 1U, 2U, 4U, 8U, 16U};
const system_limits_t *slp; const system_limits_t *slp;
halfreq_t hsi16clk = 0U, hseclk = 0U, pllselclk; halfreq_t hsi16clk = 0U, hseclk = 0U, pllselclk, hsisysclk;
halfreq_t pllpclk = 0U, pllqclk = 0U, pllrclk = 0U; halfreq_t pllpclk = 0U, pllqclk = 0U, pllrclk = 0U;
halfreq_t sysclk, hclk, pclk, pclktim, mcoclk; halfreq_t sysclk, hclk, pclk, pclktim, mcoclk;
uint32_t mcodiv, flashws; uint32_t mcodiv, flashws, hsidiv;
/* System limits based on desired VOS settings.*/ /* System limits based on desired VOS settings.*/
if ((ccp->pwr_cr1 & PWR_CR1_VOS_Msk) == PWR_CR1_VOS_1) { if ((ccp->pwr_cr1 & PWR_CR1_VOS_Msk) == PWR_CR1_VOS_1) {
@ -236,6 +236,10 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
hsi16clk = STM32_HSI16CLK; hsi16clk = STM32_HSI16CLK;
} }
/* HSISYS clock.*/
hsidiv = 1U << ((ccp->pwr_cr1 & RCC_CR_HSIDIV_Msk) >> RCC_CR_HSIDIV_Pos);
hsisysclk = hsi16clk / hsidiv;
/* HSE clock.*/ /* HSE clock.*/
if ((ccp->rcc_cr & RCC_CR_HSEON) != 0U) { if ((ccp->rcc_cr & RCC_CR_HSEON) != 0U) {
hseclk = STM32_HSECLK; hseclk = STM32_HSECLK;
@ -308,7 +312,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
/* SYSCLK frequency.*/ /* SYSCLK frequency.*/
switch(ccp->rcc_cfgr & RCC_CFGR_SW_Msk) { switch(ccp->rcc_cfgr & RCC_CFGR_SW_Msk) {
case RCC_CFGR_SW_HSI: case RCC_CFGR_SW_HSI:
sysclk = hsi16clk; sysclk = hsisysclk;
break; break;
case RCC_CFGR_SW_HSE: case RCC_CFGR_SW_HSE:
sysclk = hseclk; sysclk = hseclk;
@ -316,6 +320,12 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
case RCC_CFGR_SW_PLL: case RCC_CFGR_SW_PLL:
sysclk = pllrclk; sysclk = pllrclk;
break; break;
case RCC_CFGR_SW_LSI:
sysclk = STM32_LSICLK;
break;
case RCC_CFGR_SW_LSE:
sysclk = STM32_LSECLK;
break;
default: default:
sysclk = 0U; sysclk = 0U;
} }
@ -379,6 +389,7 @@ static bool hal_lld_clock_check_tree(const halclkcfg_t *ccp) {
/* Writing out results.*/ /* Writing out results.*/
clock_points[CLK_SYSCLK] = sysclk; clock_points[CLK_SYSCLK] = sysclk;
clock_points[CLK_HSISYSCLK] = hsisysclk;
clock_points[CLK_PLLPCLK] = pllpclk; clock_points[CLK_PLLPCLK] = pllpclk;
clock_points[CLK_PLLQCLK] = pllqclk; clock_points[CLK_PLLQCLK] = pllqclk;
clock_points[CLK_PLLRCLK] = pllrclk; clock_points[CLK_PLLRCLK] = pllrclk;

18
os/hal/ports/STM32/STM32G0xx/hal_lld.h
View File

@ -73,14 +73,15 @@
* @{ * @{
*/ */
#define CLK_SYSCLK 0U #define CLK_SYSCLK 0U
#define CLK_PLLPCLK 1U #define CLK_HSISYSCLK 1U
#define CLK_PLLQCLK 2U #define CLK_PLLPCLK 2U
#define CLK_PLLRCLK 3U #define CLK_PLLQCLK 3U
#define CLK_HCLK 4U #define CLK_PLLRCLK 4U
#define CLK_PCLK 5U #define CLK_HCLK 5U
#define CLK_PCLKTIM 6U #define CLK_PCLK 6U
#define CLK_MCO 7U #define CLK_PCLKTIM 7U
#define CLK_ARRAY_SIZE 8U #define CLK_MCO 8U
#define CLK_ARRAY_SIZE 9U
/** @} */ /** @} */
/** /**
@ -1491,6 +1492,7 @@ typedef struct {
*/ */
#define hal_lld_get_clock_point(clkpt) \ #define hal_lld_get_clock_point(clkpt) \
((clkpt) == CLK_SYSCLK ? STM32_SYSCLK : \ ((clkpt) == CLK_SYSCLK ? STM32_SYSCLK : \
(clkpt) == CLK_HSISYSCLK ? STM32_HSISYSCLK : \
(clkpt) == CLK_PLLPCLK ? STM32_PLL_P_CLKOUT : \ (clkpt) == CLK_PLLPCLK ? STM32_PLL_P_CLKOUT : \
(clkpt) == CLK_PLLQCLK ? STM32_PLL_Q_CLKOUT : \ (clkpt) == CLK_PLLQCLK ? STM32_PLL_Q_CLKOUT : \
(clkpt) == CLK_PLLRCLK ? STM32_PLL_R_CLKOUT : \ (clkpt) == CLK_PLLRCLK ? STM32_PLL_R_CLKOUT : \