diff --git a/docs/reports/LPC2148-48-ARM.txt b/docs/reports/LPC2148-48-ARM.txt
index f1ce426dd..8f38fa9cf 100644
--- a/docs/reports/LPC2148-48-ARM.txt
+++ b/docs/reports/LPC2148-48-ARM.txt
@@ -5,10 +5,11 @@ Settings: CCLK=48, MAMCR=2, MAMTIM=3 (3 wait states)
 
 *** ChibiOS/RT test suite
 ***
-*** Kernel:       2.1.7unstable
-*** GCC Version:  4.5.1
+*** Kernel:       2.3.3unstable
+*** Compiler:     GCC 4.5.2
 *** Architecture: ARM7
 *** Core Variant: ARM7TDMI
+*** Port Info:    Pure ARM mode
 *** Platform:     LPC214x
 *** Test Board:   Olimex LPC-P2148
 
@@ -98,15 +99,15 @@ Settings: CCLK=48, MAMCR=2, MAMTIM=3 (3 wait states)
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.1 (Benchmark, messages #1)
---- Score : 145386 msgs/S, 290772 ctxswc/S
+--- Score : 148549 msgs/S, 297098 ctxswc/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.2 (Benchmark, messages #2)
---- Score : 113890 msgs/S, 227780 ctxswc/S
+--- Score : 113347 msgs/S, 226694 ctxswc/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.3 (Benchmark, messages #3)
---- Score : 113890 msgs/S, 227780 ctxswc/S
+--- Score : 113347 msgs/S, 226694 ctxswc/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.4 (Benchmark, context switch)
@@ -126,11 +127,11 @@ Settings: CCLK=48, MAMCR=2, MAMTIM=3 (3 wait states)
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.8 (Benchmark, round robin context switching)
---- Score : 276084 ctxswc/S
+--- Score : 276080 ctxswc/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.9 (Benchmark, I/O Queues throughput)
---- Score : 341980 bytes/S
+--- Score : 402384 bytes/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.10 (Benchmark, virtual timers set/reset)
diff --git a/docs/reports/LPC2148-48-THUMB.txt b/docs/reports/LPC2148-48-THUMB.txt
index 199f592f4..95c0ce7e0 100644
--- a/docs/reports/LPC2148-48-THUMB.txt
+++ b/docs/reports/LPC2148-48-THUMB.txt
@@ -5,10 +5,11 @@ Settings: CCLK=48, MAMCR=2, MAMTIM=3 (3 wait states)
 
 *** ChibiOS/RT test suite
 ***
-*** Kernel:       2.1.6unstable
-*** GCC Version:  4.5.1
+*** Kernel:       2.3.3unstable
+*** Compiler:     GCC 4.5.2
 *** Architecture: ARM7
 *** Core Variant: ARM7TDMI
+*** Port Info:    Pure THUMB mode
 *** Platform:     LPC214x
 *** Test Board:   Olimex LPC-P2148
 
@@ -98,15 +99,15 @@ Settings: CCLK=48, MAMCR=2, MAMTIM=3 (3 wait states)
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.1 (Benchmark, messages #1)
---- Score : 106224 msgs/S, 212448 ctxswc/S
+--- Score : 108146 msgs/S, 216292 ctxswc/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.2 (Benchmark, messages #2)
---- Score : 88032 msgs/S, 176064 ctxswc/S
+--- Score : 89014 msgs/S, 178028 ctxswc/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.3 (Benchmark, messages #3)
---- Score : 88032 msgs/S, 176064 ctxswc/S
+--- Score : 89014 msgs/S, 178028 ctxswc/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.4 (Benchmark, context switch)
@@ -130,7 +131,7 @@ Settings: CCLK=48, MAMCR=2, MAMTIM=3 (3 wait states)
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.9 (Benchmark, I/O Queues throughput)
---- Score : 261396 bytes/S
+--- Score : 315532 bytes/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.10 (Benchmark, virtual timers set/reset)
@@ -138,7 +139,7 @@ Settings: CCLK=48, MAMCR=2, MAMTIM=3 (3 wait states)
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.11 (Benchmark, semaphores wait/signal)
---- Score : 350836 wait+signal/S
+--- Score : 350832 wait+signal/S
 --- Result: SUCCESS
 ----------------------------------------------------------------------------
 --- Test Case 11.12 (Benchmark, mutexes lock/unlock)
diff --git a/os/ports/GCC/ARM/chcore.h b/os/ports/GCC/ARM/chcore.h
index 5a36d82c8..20727ce23 100644
--- a/os/ports/GCC/ARM/chcore.h
+++ b/os/ports/GCC/ARM/chcore.h
@@ -62,7 +62,7 @@
  * @brief   If enabled allows the idle thread to enter a low power mode.
  */
 #ifndef ARM_ENABLE_WFI_IDLE
-#define ARM_ENABLE_WFI_IDLE         FALSE
+#define ARM_ENABLE_WFI_IDLE             FALSE
 #endif
 
 /*===========================================================================*/
@@ -93,7 +93,7 @@
  *          - "ARM9".
  *          .
  */
-#define CH_ARCHITECTURE_NAME "ARMx"
+#define CH_ARCHITECTURE_NAME            "ARMx"
 
 /**
  * @brief   Name of the architecture variant (optional).
@@ -103,19 +103,45 @@
  *          - "ARM9"
  *          .
  */
-#define CH_CORE_VARIANT_NAME "ARMxy"
+#define CH_CORE_VARIANT_NAME            "ARMxy"
+
+/**
+ * @brief   Port-specific information string.
+ * @note    The value is for documentation only, the real value changes
+ *          depending on the selected options, the possible values are:
+ *          - "Pure ARM"
+ *          - "Pure THUMB"
+ *          - "Interworking"
+ *          .
+ */
+#define CH_PORT_INFO                    "ARM|THUMB|Interworking"
 
 #elif ARM_CORE == ARM_CORE_ARM7TDMI
 #define CH_ARCHITECTURE_ARM7TDMI
-#define CH_ARCHITECTURE_NAME        "ARM7"
-#define CH_CORE_VARIANT_NAME        "ARM7TDMI"
+#define CH_ARCHITECTURE_NAME            "ARM7"
+#define CH_CORE_VARIANT_NAME            "ARM7TDMI"
 
 #elif ARM_MODEL == ARM_VARIANT_ARM9
 #define CH_ARCHITECTURE_ARM9
-#define CH_ARCHITECTURE_NAME        "ARM9"
-#define CH_CORE_VARIANT_NAME        "ARM9"
+#define CH_ARCHITECTURE_NAME            "ARM9"
+#define CH_CORE_VARIANT_NAME            "ARM9"
 #endif
 
+#if THUMB_PRESENT
+#if THUMB_NO_INTERWORKING
+#define CH_PORT_INFO                    "Pure THUMB mode"
+#else /* !THUMB_NO_INTERWORKING */
+#define CH_PORT_INFO                    "Interworking mode"
+#endif /* !THUMB_NO_INTERWORKING */
+#else /* !THUMB_PRESENT */
+#define CH_PORT_INFO                    "Pure ARM mode"
+#endif /* !THUMB_PRESENT */
+
+/**
+ * @brief   Name of the compiler supported by this port.
+ */
+#define CH_COMPILER_NAME                "GCC "__VERSION__
+
 /*===========================================================================*/
 /* Port implementation part (common).                                        */
 /*===========================================================================*/