From 2c0ead7cbb51c12442a3ffdaf5641a1f23c6329f Mon Sep 17 00:00:00 2001
From: Giovanni Di Sirio <gdisirio@gmail.com>
Date: Sat, 12 Sep 2020 08:08:24 +0000
Subject: [PATCH] Fixed bug #1122.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_20.3.x@13855 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
---
 os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c | 15 +++------------
 readme.txt                                  |  3 ++-
 2 files changed, 5 insertions(+), 13 deletions(-)

diff --git a/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c b/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c
index 42a620e3e..07c17a1ee 100644
--- a/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c
+++ b/os/hal/ports/STM32/LLD/xWDGv1/hal_wdg_lld.c
@@ -85,7 +85,6 @@ void wdg_lld_init(void) {
  */
 void wdg_lld_start(WDGDriver *wdgp) {
 
-#if STM32_IWDG_IS_WINDOWED
   /* Enable IWDG and unlock for write.*/
   wdgp->wdg->KR   = KR_KEY_ENABLE;
   wdgp->wdg->KR   = KR_KEY_WRITE;
@@ -93,24 +92,16 @@ void wdg_lld_start(WDGDriver *wdgp) {
   /* Write configuration.*/
   wdgp->wdg->PR   = wdgp->config->pr;
   wdgp->wdg->RLR  = wdgp->config->rlr;
+
+  /* Wait the registers to be updated.*/
   while (wdgp->wdg->SR != 0)
     ;
 
+#if STM32_IWDG_IS_WINDOWED
   /* This also triggers a refresh.*/
   wdgp->wdg->WINR = wdgp->config->winr;
 #else
-  /* Unlock IWDG.*/
-  wdgp->wdg->KR   = KR_KEY_WRITE;
-
-  /* Write configuration.*/
-  while (wdgp->wdg->SR != 0)
-    ;
-  wdgp->wdg->PR   = wdgp->config->pr;
-  wdgp->wdg->RLR  = wdgp->config->rlr;
-
-  /* Start operations.*/
   wdgp->wdg->KR   = KR_KEY_RELOAD;
-  wdgp->wdg->KR   = KR_KEY_ENABLE;
 #endif
 }
 
diff --git a/readme.txt b/readme.txt
index 7263fccf2..e71945a85 100644
--- a/readme.txt
+++ b/readme.txt
@@ -74,7 +74,8 @@
 *****************************************************************************
 
 *** 20.3.3 ***
-- FIX: Ignored HSIDIV setting on STM32G0xx (bug #1121)
+- FIX: Fixed incorrect STM32 iWDG initialization in windowed mode (bug #1122).
+- FIX: Fixed ignored HSIDIV setting on STM32G0xx (bug #1121)
 
 *** 20.3.2 ***
 - NEW: Support for 3 analog watchdogs in ADCv3 (STM32F3, L4, L4+, G4).